diff options
| author | Robert Norton | 2016-04-29 15:32:05 +0100 |
|---|---|---|
| committer | Robert Norton | 2016-04-29 15:32:05 +0100 |
| commit | f9c25890e174ede61130316d0cfc7b9416400e5a (patch) | |
| tree | 0a77559bc3c823a23cfdb500aff10164132c6eb9 /mips | |
| parent | ef3deb63b3eead7e3b3ec826fd3d4f5695d642df (diff) | |
use the correct exception vector for ccall/creturn.
Diffstat (limited to 'mips')
| -rw-r--r-- | mips/mips_prelude.sail | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail index 9161b929..b3fb9a32 100644 --- a/mips/mips_prelude.sail +++ b/mips/mips_prelude.sail @@ -120,7 +120,7 @@ val extern unit -> unit effect { barr } MEM_sync typedef Exception = enumerate { - Int; Mod; TLBL; TLBS; AdEL; AdES; Sys; Bp; ResI; CpU; Ov; Tr; C2E; + Int; Mod; TLBL; TLBS; AdEL; AdES; Sys; Bp; ResI; CpU; Ov; Tr; C2E; C2Trap; XTLBRefillL; XTLBRefillS } @@ -141,6 +141,7 @@ function (bit[5]) ExceptionCode ((Exception) ex) = case Ov -> mask(0x0c) (* Arithmetic overflow *) case Tr -> mask(0x0d) (* Trap *) case C2E -> mask(0x12) (* C2E coprocessor 2 exception *) + case C2Trap -> mask(0x12) (* C2Trap maps to same exception code, different vector *) case XTLBRefillL -> mask(0x02) case XTLBRefillS -> mask(0x03) } @@ -165,11 +166,17 @@ function unit SignalExceptionMIPS ((Exception) ex) = } }; - (* choose an exception vector to branch to *) - vectorOffset := if ((ex == XTLBRefillL) | (ex == XTLBRefillS)) & ~ (CP0Status.EXL) then - 0x080 - else - 0x180; + (* choose an exception vector to branch to. Some are not supported + e.g. Reset *) + vectorOffset := + if (CP0Status.EXL) then + 0x180 (* Always use common vector if in exception mode already *) + else if ((ex == XTLBRefillL) | (ex == XTLBRefillS)) then + 0x080 + else if (ex == C2Trap) then + 0x280 (* Special vector for CHERI traps *) + else + 0x180; (* Common vector *) (bit[64]) vectorBase := if CP0Status.BEV then 0xFFFFFFFFBFC00200 else |