diff options
| author | Robert Norton | 2016-05-04 13:31:31 +0100 |
|---|---|---|
| committer | Robert Norton | 2016-05-04 13:31:31 +0100 |
| commit | d26a230b63e5e6ba528d3d5930521d23c8bdd727 (patch) | |
| tree | f7962289a933b53d276cbcf1a53c9239864484b5 /mips | |
| parent | 87c56d3a270c4f7cf151a5e2519227bc80ee29b9 (diff) | |
check for PC alignment on instruction fetch.
Diffstat (limited to 'mips')
| -rw-r--r-- | mips/mips_wrappers.sail | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail index 8fe1b4d4..25b8936b 100644 --- a/mips/mips_wrappers.sail +++ b/mips/mips_wrappers.sail @@ -6,7 +6,10 @@ function bit[64] addrWrapper((bit[64]) addr, (MemAccessType) accessType, (WordTy addr function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = - TLBTranslate(vAddr, accessType) + if (vAddr[1..0] != 0b00) then (* bad PC alignment *) + exit (SignalExceptionBadAddr(AdEL, vAddr)) + else + TLBTranslate(vAddr, accessType) function unit SignalException ((Exception) ex) = SignalExceptionMIPS(ex) |