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authorKathy Gray2016-06-07 14:07:12 +0100
committerKathy Gray2016-06-07 14:07:20 +0100
commita0bd975bd9e12cc0434bce918c6cbd555c9f55b5 (patch)
tree790f0a6c3db75c6d40e7eac55462e328a745c8c9 /mips
parenta7e59e7d4fb06a33c0dcb4d5c5aed0fffedac796 (diff)
Fix issue in accessing fields and slices of registers during translate address
Diffstat (limited to 'mips')
-rw-r--r--mips/mips_prelude.sail10
1 files changed, 5 insertions, 5 deletions
diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail
index bf9d8cc0..011c9c0d 100644
--- a/mips/mips_prelude.sail
+++ b/mips/mips_prelude.sail
@@ -367,11 +367,11 @@ function unit incrementCP0Count() = {
(* XXX Sail does not allow reading fields here :-( *)
let (bit[32])status = CP0Status in
let (bit[32])cause = CP0Cause in
- let (bit[8]) ims = status[15..8] in
- let (bit[8]) ips = cause[15..8] in
- let ie = status[0] in
- let exl = status[1] in
- let erl = status[2] in
+ let (bit[8]) ims = CP0Status.IM (*status[15..8]*) in
+ let (bit[8]) ips = CP0Cause.IP (*cause[15..8] *) in
+ let ie = CP0Status.IE in
+ let exl = CP0Status.EXL (*status[1]*) in
+ let erl = CP0Status.ERL (*status[2]*) in
if ((~(exl)) & (~(erl)) & ie & ((ips & ims) != 0x00)) then
exit (SignalException(Int));
}