diff options
| author | Robert Norton | 2016-01-27 14:34:52 +0000 |
|---|---|---|
| committer | Robert Norton | 2016-01-28 14:40:28 +0000 |
| commit | 43d7a4410f0bb3adda9bcb38e28a0abd5ebb3020 (patch) | |
| tree | 7cf5952699a75cb5a50c2ef3ae12c626d6b4e6ae /mips | |
| parent | f2f9a5859d6bae6a1d2eced2393f970c4bba85da (diff) | |
mips.sail: split store cases by word width as sail needs to know which bit of word to store (probably a bug that it does not complain at runtime).
Diffstat (limited to 'mips')
| -rw-r--r-- | mips/mips.sail | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/mips/mips.sail b/mips/mips.sail index f0085f89..fd69a9f8 100644 --- a/mips/mips.sail +++ b/mips/mips.sail @@ -1265,6 +1265,7 @@ function clause decode (0b111100 : (regno) base : (regno) rt : (imm16) offset) = function clause execute (Store(width, conditional, base, rt, offset)) = { (bit[64]) vAddr := EXTS(offset) + rGPR(base); + (bit[64]) rt_val := rGPR(rt); if ~ (isAddressAligned(vAddr, width)) then SignalException(AdES) (* unaligned access *) else @@ -1274,11 +1275,23 @@ function clause execute (Store(width, conditional, base, rt, offset)) = { if (conditional) then { - success := (MEMw_conditional(vAddr, wordWidthBytes(width), rGPR(rt))); + success := switch(width) + { + case B -> MEMw_conditional(vAddr, 1, rt_val[7..0]) + case H -> MEMw_conditional(vAddr, 2, rt_val[15..0]) + case W -> MEMw_conditional(vAddr, 4, rt_val[31..0]) + case D -> MEMw_conditional(vAddr, 8, rt_val) + }; wGPR(rt) := EXTZ([success]) } else - MEMw(vAddr, wordWidthBytes(width)) := rGPR(rt) + switch(width) + { + case B -> MEMw(vAddr, 1) := rt_val[7..0] + case H -> MEMw(vAddr, 2) := rt_val[15..0] + case W -> MEMw(vAddr, 4) := rt_val[31..0] + case D -> MEMw(vAddr, 8) := rt_val + } } } } |