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authorRobert Norton2018-05-17 17:42:20 +0100
committerRobert Norton2018-05-17 17:42:20 +0100
commitb08f0e8538081d8efbbbd6431e739a0b83307678 (patch)
tree8bee68057ce9b570fcd74b89bf224d229f21572d /mips/prelude.sail
parent2c5bbd6f7fbfdf32bafab50e36a1bebcd7cd8dab (diff)
build fixes: add back tag effect skips required for mips. Move UART check in to correct place in main.sail. Remove add_atom and sub_atom from prelude as we get them from arith.sail.
Diffstat (limited to 'mips/prelude.sail')
-rw-r--r--mips/prelude.sail6
1 files changed, 0 insertions, 6 deletions
diff --git a/mips/prelude.sail b/mips/prelude.sail
index 477d0967..a44cb6bb 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -130,9 +130,6 @@ val int_power = {ocaml: "int_power", lem: "pow"} : (int, int) -> int
overload operator ^ = {xor_vec, int_power}
-val add_atom = {ocaml: "add_int", lem: "integerAdd"} : forall 'n 'm.
- (atom('n), atom('m)) -> atom('n + 'm)
-
val add_range = {ocaml: "add_int", lem: "integerAdd"} : forall 'n 'm 'o 'p.
(range('n, 'm), range('o, 'p)) -> range('n + 'o, 'm + 'p)
@@ -142,9 +139,6 @@ val add_vec_int = "add_vec_int" : forall 'n. (bits('n), int) -> bits('n)
overload operator + = {add_range, add_int, add_vec, add_vec_int}
-val sub_atom = {ocaml: "sub_int", lem: "integerMinus", c: "sub_int"} : forall 'n 'm.
- (atom('n), atom('m)) -> atom('n - 'm)
-
val sub_range = {ocaml: "sub_int", lem: "integerMinus"} : forall 'n 'm 'o 'p.
(range('n, 'm), range('o, 'p)) -> range('n - 'p, 'm - 'o)