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authorRobert Norton2018-06-04 14:50:10 +0100
committerRobert Norton2018-06-04 15:12:27 +0100
commit51f621e7e215c30fa9742f84f43de52dacc4aee0 (patch)
tree48bb78640aaee0d4b3089245e79b2a5aa4eebb13 /mips/prelude.sail
parent5efc7e055c1cc6d8452e6de862398aebb035eb23 (diff)
cheri: print debug trace info to stderr to keep it separate from uart output.
Diffstat (limited to 'mips/prelude.sail')
-rw-r--r--mips/prelude.sail1
1 files changed, 1 insertions, 0 deletions
diff --git a/mips/prelude.sail b/mips/prelude.sail
index a44cb6bb..2fa818e3 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -207,6 +207,7 @@ function operator ^^ (bs, n) = replicate_bits (bs, n)
val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n)
val print_bits = "print_bits" : forall 'n. (string, bits('n)) -> unit
+val prerr_bits = "prerr_bits" : forall 'n. (string, bits('n)) -> unit
val print_string = "print_string" : (string, string) -> unit
union exception = {