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authorRobert Norton2018-04-04 17:06:03 +0100
committerRobert Norton2018-04-04 17:06:24 +0100
commit252460bc33fc26d8ef8aa905592fd4029d97d419 (patch)
tree190ac6bde29d8d2846d3ae073e6727fe3de16053 /mips/prelude.sail
parent48f38c64fb68208d0b245f15ec2a3453ed00690f (diff)
Fix another infinite loop in cast bit_to_bool. Following introduction of eq_bool this was preferred over eq_bit when compiling the match on bit in bit_to_bool... Fix is to overload == before including flow.sail but feels a bit inelegant.
Diffstat (limited to 'mips/prelude.sail')
-rw-r--r--mips/prelude.sail6
1 files changed, 5 insertions, 1 deletions
diff --git a/mips/prelude.sail b/mips/prelude.sail
index 9607e508..74ae95b2 100644
--- a/mips/prelude.sail
+++ b/mips/prelude.sail
@@ -23,7 +23,11 @@ val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg}
/* sneaky deref with no effect necessary for bitfield writes */
val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a
-overload operator == = {eq_atom, eq_int, eq_bit, eq_vec, eq_string, eq_real, eq_anything}
+overload operator == = {eq_bit}
+
+$include <flow.sail>
+
+overload operator == = {eq_vec, eq_string, eq_real, eq_anything}
val vector_subrange = {ocaml: "subrange", lem: "subrange_vec_dec"} : forall ('n : Int) ('m : Int) ('o : Int), 'o <= 'm <= 'n.
(bits('n), atom('m), atom('o)) -> bits('m - ('o - 1))