diff options
| author | Robert Norton | 2017-04-03 15:05:05 +0100 |
|---|---|---|
| committer | Robert Norton | 2017-04-03 15:05:05 +0100 |
| commit | f7b406a5cc91bf011c524f1d0775d69182412bc2 (patch) | |
| tree | ba0585a77144dbf3797a01e10cc5c13bde1ca673 /mips/mips_wrappers.sail | |
| parent | 88220a76169452c4a820625bd5c6273823b29939 (diff) | |
Rename TranslateAddress to TranslatePC and remove the accessType argument -- it is only ever used for translating the PC.
Diffstat (limited to 'mips/mips_wrappers.sail')
| -rw-r--r-- | mips/mips_wrappers.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail index b70853f0..b46e35be 100644 --- a/mips/mips_wrappers.sail +++ b/mips/mips_wrappers.sail @@ -54,12 +54,12 @@ function bool effect {wmem} MEMw_conditional_wrapper(addr, size, data) = function bit[64] addrWrapper((bit[64]) addr, (MemAccessType) accessType, (WordType) width) = addr -function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = { +function (bit[64]) TranslatePC ((bit[64]) vAddr) = { incrementCP0Count(); if (vAddr[1..0] != 0b00) then (* bad PC alignment *) (SignalExceptionBadAddr(AdEL, vAddr)) else - TLBTranslate(vAddr, accessType) + TLBTranslate(vAddr, Instruction) } let have_cp2 = false |