diff options
| author | Robert Norton | 2018-07-03 16:24:47 +0100 |
|---|---|---|
| committer | Robert Norton | 2018-07-03 16:25:07 +0100 |
| commit | c1c51761101cd9313df3b111accb6237e558f0d2 (patch) | |
| tree | 40b8db8490bce2b6b4621428e9cc4c9d08257929 /mips/mips_wrappers.sail | |
| parent | 226fd119ca929f24b568b9692403ca477c7511c4 (diff) | |
cheri: refine lwl/lwr cap length checks to be exact. They were previously a bit loose, but conservative.
Diffstat (limited to 'mips/mips_wrappers.sail')
| -rw-r--r-- | mips/mips_wrappers.sail | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail index 0cc098a5..43e759b9 100644 --- a/mips/mips_wrappers.sail +++ b/mips/mips_wrappers.sail @@ -60,6 +60,10 @@ val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) function addrWrapper(addr, accessType, width) = addr +val addrWrapperUnaligned : (bits(64), MemAccessType, WordTypeUnaligned) -> bits(64) +function addrWrapperUnaligned(addr, accessType, width) = + addr + $ifdef _MIPS_TLB_STUB val TranslatePC : bits(64) -> bits(64) effect {rreg, wreg, escape} $else |