diff options
| author | Robert Norton | 2017-10-12 17:14:40 +0100 |
|---|---|---|
| committer | Robert Norton | 2017-10-12 17:14:40 +0100 |
| commit | 64468eda2bc40c874cddd4a6d9972af5ec224dc2 (patch) | |
| tree | 2c1a5d71de3cb83b5536b11016998e3e08b54d73 /mips/mips_tlb.sail | |
| parent | 93dfd61038583eac852e5e3ea66c46817a610bbe (diff) | |
Work around warning in ocaml shallow embedding of mips caused by buggy code generation for dubious casting enumeration to int.
Diffstat (limited to 'mips/mips_tlb.sail')
| -rw-r--r-- | mips/mips_tlb.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mips/mips_tlb.sail b/mips/mips_tlb.sail index 2e40deed..d72e0e75 100644 --- a/mips/mips_tlb.sail +++ b/mips/mips_tlb.sail @@ -108,7 +108,7 @@ function (bit[64], bool) TLBTranslateC ((bit[64]) vAddr, (MemAccessType) accessT case 0b01 -> (Supervisor, None) (* xsseg - supervisor mapped *) case 0b00 -> (User, None) (* xuseg - user mapped *) } in - if (((nat)currentAccessLevel) < ((nat)requiredLevel)) then + if ((int_of_accessLevel(currentAccessLevel)) < (int_of_accessLevel(requiredLevel))) then (SignalExceptionBadAddr(if (accessType == StoreData) then AdES else AdEL, vAddr)) else let (pa, c) = switch(addr) { |