diff options
| author | Robert Norton | 2016-11-03 16:28:20 +0000 |
|---|---|---|
| committer | Robert Norton | 2016-11-03 16:28:31 +0000 |
| commit | aeb83c296e6ca169ef6483562935f7b72bdb2db7 (patch) | |
| tree | 174e7110bee3c300fd87caca121667cf94e53af5 /mips/mips_ri.sail | |
| parent | b1970df86db7589a1415e5b76397119a255e2dde (diff) | |
split out RI node so that ppcmem model does not implement reserved instruction exception behaviour but sequential model does (for test suite).
Diffstat (limited to 'mips/mips_ri.sail')
| -rw-r--r-- | mips/mips_ri.sail | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/mips/mips_ri.sail b/mips/mips_ri.sail new file mode 100644 index 00000000..e1222b98 --- /dev/null +++ b/mips/mips_ri.sail @@ -0,0 +1,42 @@ +(*========================================================================*) +(* *) +(* Copyright (c) 2015-2016 Robert M. Norton *) +(* Copyright (c) 2015-2016 Kathyrn Gray *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +(* mips_ri.sail: only use if want unknown instructions to throw + exception (like real hardware) instead of die (convenient for ppcmem) *) + +union ast member unit RI +function clause decode _ = Some(RI) +function clause execute (RI) = + SignalException (ResI) + |