diff options
| author | Robert Norton | 2016-02-01 17:09:56 +0000 |
|---|---|---|
| committer | Robert Norton | 2016-02-01 17:09:56 +0000 |
| commit | 87ae91e51f744cc9f09b1dbab4d84b81b4881223 (patch) | |
| tree | ce6c7fe20391fd16767df6335d8a4b948f9e6494 /mips/mips.sail | |
| parent | 681872327b67b856b6c2c11a17998ba8edb52e81 (diff) | |
mips.sail: fix mfc0 of config register.
Diffstat (limited to 'mips/mips.sail')
| -rw-r--r-- | mips/mips.sail | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/mips/mips.sail b/mips/mips.sail index 4277f672..5843e9ac 100644 --- a/mips/mips.sail +++ b/mips/mips.sail @@ -1557,13 +1557,14 @@ function clause execute (MFC0(rt, rd, sel, double)) = case (0b01111,0b000) -> EXTZ(0x00000400) (* 15, sel 0: PrID processor ID *) case (0b01111,0b110) -> 0 (* 15, sel 6: CHERI core ID *) case (0b01111,0b111) -> 0 (* 15, sel 7: CHERI thread ID *) - case (0b10000,0b000) -> 0b1 (* M *) (* 16, sel 0: Config0 *) + case (0b10000,0b000) -> EXTZ(0b1 (* M *) (* 16, sel 0: Config0 *) : 0b000000000000000 (* Impl *) : 0b1 (* BE *) : 0b10 (* AT *) : 0b000 (* AR *) - : 0b000 (* 0 *) - : 0b000 (* K0 TODO should be writable*) + : 0b000 (* MT no MMU *) + : 0b0000 (* zero *) + : 0b000) (* K0 TODO should be writable*) case (0b10000,0b001) -> 0 (* 16, sel 1: Config1 *) case _ -> {SignalException(ResI); 0} } in |