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authorRobert Norton2016-02-03 17:32:50 +0000
committerRobert Norton2016-02-03 17:32:50 +0000
commit618df92d2a84832c978bc05f14c8611ded831abd (patch)
treef8c203d7ed24f5887f649d1c7685202cdfec792e /mips/mips.sail
parentb93ee1a8e09e60239792897c28ca2eced0746f25 (diff)
mips: finish implementing address translation on instruction fetch and remove temporary hack in TranslateAddr.
Diffstat (limited to 'mips/mips.sail')
-rw-r--r--mips/mips.sail6
1 files changed, 3 insertions, 3 deletions
diff --git a/mips/mips.sail b/mips/mips.sail
index 35dcc2d8..f89e1198 100644
--- a/mips/mips.sail
+++ b/mips/mips.sail
@@ -192,11 +192,11 @@ function (option<Exception>, option<bit[64]>) TranslateAddress ((bit[64]) vAddr,
case 0b11 -> switch(vAddr[61..31], vAddr[30..29]) { (* xkseg *)
case (0b1111111111111111111111111111111, 0b11) -> (err, None) (* kseg3 mapped 32-bit compat TODO *)
case (0b1111111111111111111111111111111, 0b10) -> (err, None) (* sseg mapped 32-bit compat TODO *)
- case (0b1111111111111111111111111111111, 0b01) -> (None, Some(vAddr)) (* kseg1 unmapped uncached 32-bit compat *)
- case (0b1111111111111111111111111111111, 0b00) -> (None, Some(vAddr)) (* kseg0 unmapped cached 32-bit compat *)
+ case (0b1111111111111111111111111111111, 0b01) -> (None, Some(EXTZ(vAddr[28..0]))) (* kseg1 unmapped uncached 32-bit compat *)
+ case (0b1111111111111111111111111111111, 0b00) -> (None, Some(EXTZ(vAddr[28..0]))) (* kseg0 unmapped cached 32-bit compat *)
case (_, _) -> (err, None) (* xkseg mapped TODO *)
}
- case 0b10 -> (None, Some(0b10010 : (vAddr[58..0]))) (* xkphys bits 61-59 are cache mode which we ignore *)
+ case 0b10 -> (None, Some(EXTZ(vAddr[58..0]))) (* xkphys bits 61-59 are cache mode which we ignore *)
case 0b01 -> (err, None) (* xsseg - supervisor mapped TODO *)
case 0b00 -> (err, None) (* xuseg - user mapped TODO *)
}