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authorRobert Norton2018-02-22 17:23:48 +0000
committerRobert Norton2018-02-22 17:23:48 +0000
commitbac62a260ce9aa8f83bb71515daf1829133b0127 (patch)
tree03b24eea504d09dc6fa3267fc9740aef6b66e446 /lib/vector_dec.sail
parent5308167903db5e81c07a5aff9f20c83f33afcb9c (diff)
parentc63741a21b5a1f77f85987f15f6aac3321a91f0a (diff)
Merge branch 'sail2' of github.com:rems-project/sail into sail2
Diffstat (limited to 'lib/vector_dec.sail')
-rw-r--r--lib/vector_dec.sail12
1 files changed, 12 insertions, 0 deletions
diff --git a/lib/vector_dec.sail b/lib/vector_dec.sail
index e24f5111..8a55ed61 100644
--- a/lib/vector_dec.sail
+++ b/lib/vector_dec.sail
@@ -13,6 +13,18 @@ val "zero_extend" : forall 'n 'm, 'm >= 'n. (bits('n), atom('m)) -> bits('m)
/* Used for creating long bitvector literals in the C backend. */
val "append_64" : forall 'n. (bits('n), bits(64)) -> bits('n + 64)
+val vector_access = {
+ ocaml: "access",
+ lem: "access_list_dec",
+ c: "vector_access"
+} : forall ('n : Int) ('m : Int) ('a : Type), 0 <= 'm < 'n. (vector('n, dec, 'a), atom('m)) -> 'a
+
+val vector_update = {
+ ocaml: "update",
+ lem: "update_list_dec",
+ c: "vector_update"
+} : forall 'n ('a : Type). (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a)
+
val add_bits = {
ocaml: "add_vec",
c: "add_bits"