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authorAlasdair Armstrong2019-02-21 20:03:20 +0000
committerAlasdair Armstrong2019-02-21 20:03:20 +0000
commit9c13d5888fdd12aa46f9a3b1a752cf040bc94939 (patch)
tree0c3223d649f69b216daa5f9ef81fba4aa7b94caa /doc/riscv.tex
parentc0de36691f70867bbe1f9cd01f0ee4340b7fb2d5 (diff)
Fix manual, and include Alexandre's typo fixes
Diffstat (limited to 'doc/riscv.tex')
-rw-r--r--doc/riscv.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/riscv.tex b/doc/riscv.tex
index 586efdf4..ee0c07e1 100644
--- a/doc/riscv.tex
+++ b/doc/riscv.tex
@@ -61,7 +61,7 @@ register Xs : vector(32, dec, xlen_t)
\sailval{wX}
\sailfn{wX}
-\sailoverloadHHX
+\sailoverloadIIX
We also give a function \ll{MEMr} for reading memory, this function
just points at a builtin we have defined elsewhere. Note that
@@ -138,4 +138,4 @@ end execute
The actual code for this example, as well as our more complete
\riscv\ specification can be found on our github at
-\anonymise{\url{https://github.com/rems-project/sail/blob/sail2/riscv/riscv_duopod.sail}}.
+\anonymise{\url{https://github.com/rems-project/sail-riscv/blob/master/model/riscv_duopod.sail}}.