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authorJon French2018-05-15 17:50:05 +0100
committerJon French2018-05-15 17:50:05 +0100
commite2d8fe4d847b6e8f71eecd7aa6d15799bd2a2e11 (patch)
treeaf5ca7ac35244a706f9631ab8f1a4dada172f27d /doc/examples/my_replicate_bits.sail
parented3bb9702bd1f76041a3798f453714b0636a1b6b (diff)
parent77b393e4f53d14955d301cbd16e22d2e7b026ede (diff)
Merge branch 'sail2' into mappings
Diffstat (limited to 'doc/examples/my_replicate_bits.sail')
-rw-r--r--doc/examples/my_replicate_bits.sail3
1 files changed, 2 insertions, 1 deletions
diff --git a/doc/examples/my_replicate_bits.sail b/doc/examples/my_replicate_bits.sail
index bd45a32d..c9972cd6 100644
--- a/doc/examples/my_replicate_bits.sail
+++ b/doc/examples/my_replicate_bits.sail
@@ -11,7 +11,8 @@ val "shiftl" : forall 'm. (bits('m), int) -> bits('m)
val operator >> = {
ocaml: "shiftr_ocaml",
c: "shiftr_c",
- lem: "shiftr_lem"
+ lem: "shiftr_lem",
+ _: "shiftr"
} : forall 'm. (bits('m), int) -> bits('m)
val "or_vec" : forall 'n. (bits('n), bits('n)) -> bits('n)