diff options
| author | Robert Norton | 2016-05-03 14:54:17 +0100 |
|---|---|---|
| committer | Robert Norton | 2016-05-03 14:54:17 +0100 |
| commit | 9ac80b4fd49c73e1090ab09304ed3b04510667ff (patch) | |
| tree | 00f458bac2d603b869ff95815f094ec594d8647a /cheri | |
| parent | ba696d4b1a6c563fb99d84e084795dad23c509ab (diff) | |
fix cheri and mips sail following change to type of TranslateAddress -- can now write registers hence call SignalException instead of returning option<err> .
Diffstat (limited to 'cheri')
| -rw-r--r-- | cheri/cheri_prelude.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cheri/cheri_prelude.sail b/cheri/cheri_prelude.sail index 6aaa9a0c..7c5e34a9 100644 --- a/cheri/cheri_prelude.sail +++ b/cheri/cheri_prelude.sail @@ -407,12 +407,12 @@ function bit[64] addrWrapper((bit[64]) addr, (MemAccessType) accessType, (WordTy vAddr64; } -function (option<Exception>, option<bit[64]>) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = +function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = let (bit[257]) x = PCC in let (bit[64]) base = x[127..64] in let (bit[64]) length = x[63..0] in let (bit[64]) absPC = (base + vAddr) in if ((unsigned(vAddr) + 4) > unsigned(length)) then - (Some(C2E), None) (* XXX take exception properly *) + exit (raise_c2_exception_noreg(CapEx_LengthViolation)) (* XXX take exception properly *) else TLBTranslate(absPC, accessType) |