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authorRobert Norton2016-05-12 19:19:44 +0100
committerRobert Norton2016-05-12 19:19:44 +0100
commit73cbdc8a34c14a8c6ad1bb1912ad2f1e6b38980c (patch)
tree5178806140614e4c4658dc07f8f42afa95b67527 /cheri
parentf2d1251696941469f9356c7d5a809cf21bda0e24 (diff)
Implement count/compare registers for timer interrupts and rdhwr instruction.
Diffstat (limited to 'cheri')
-rw-r--r--cheri/cheri_prelude.sail6
1 files changed, 5 insertions, 1 deletions
diff --git a/cheri/cheri_prelude.sail b/cheri/cheri_prelude.sail
index 4ab99fdc..0cb2a1f3 100644
--- a/cheri/cheri_prelude.sail
+++ b/cheri/cheri_prelude.sail
@@ -407,7 +407,9 @@ function bit[64] addrWrapper((bit[64]) addr, (MemAccessType) accessType, (WordTy
vAddr64;
}
-function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) =
+function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = {
+ incrementCP0Count();
+ (* XXX Sail does not allow reading fields here :-( *)
let (bit[257]) x = PCC in
let (bit[64]) base = x[127..64] in
let (bit[64]) length = x[63..0] in
@@ -418,6 +420,7 @@ function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType
exit (raise_c2_exception_noreg(CapEx_LengthViolation)) (* XXX take exception properly *)
else
TLBTranslate(absPC, accessType)
+}
function unit checkCP2usable () =
{
@@ -427,3 +430,4 @@ function unit checkCP2usable () =
exit (SignalException(CpU));
}
}
+