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authorAlasdair Armstrong2018-07-27 16:29:40 +0100
committerAlasdair Armstrong2018-07-27 16:29:40 +0100
commit313c004c1829700697ea2fe1281cc1f7afe5904a (patch)
tree8af9ee022502c8d422daf98178000df5e9317e97 /cheri/sail_latex/sailfnExceptionCode.tex
parent4861ebb08ccd3e13af19b9c12f2164b66a5d2bb0 (diff)
Check in snapshot of cheri latex
Diffstat (limited to 'cheri/sail_latex/sailfnExceptionCode.tex')
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+function #\hyperref[zExceptionCode]{ExceptionCode}# (ex) : Exception -> #\hyperref[zbits]{bits}#(5)=
+ let x : #\hyperref[zbits]{bits}#(8) = match ex
+ {
+ Interrupt => 0x00, /* Interrupt */
+ TLBMod => 0x01, /* TLB modification exception */
+ TLBL => 0x02, /* TLB #\hyperref[zexception]{exception}# (load or fetch) */
+ TLBS => 0x03, /* TLB #\hyperref[zexception]{exception}# (store) */
+ AdEL => 0x04, /* Address #\hyperref[zerror]{error}# (load or fetch) */
+ AdES => 0x05, /* Address #\hyperref[zerror]{error}# (store) */
+ Sys => 0x08, /* Syscall */
+ Bp => 0x09, /* Breakpoint */
+ ResI => 0x0a, /* Reserved instruction */
+ CpU => 0x0b, /* Coprocessor Unusable */
+ Ov => 0x0c, /* Arithmetic overflow */
+ Tr => 0x0d, /* Trap */
+ C2E => 0x12, /* C2E coprocessor 2 exception */
+ C2Trap => 0x12, /* C2Trap maps to same exception code, different vector */
+ XTLBRefillL => 0x02,
+ XTLBRefillS => 0x03,
+ XTLBInvL => 0x02,
+ XTLBInvS => 0x03,
+ MCheck => 0x18
+ } in x[4..0]