diff options
| author | Robert Norton | 2018-03-14 18:02:10 +0000 |
|---|---|---|
| committer | Robert Norton | 2018-03-14 18:04:09 +0000 |
| commit | 7aef4970c36b45f50dc61d66353dc759b438e706 (patch) | |
| tree | ca5399a81d8019975778dc14c66fbfbf6daa52d0 /cheri/cheri_prelude_common.sail | |
| parent | 26c7468c15c15424535afebc12e995a3a746476f (diff) | |
Add and use execute_branch and execute_branch_pcc functions to align code with existing MIPS and CHERI specs.
Diffstat (limited to 'cheri/cheri_prelude_common.sail')
| -rw-r--r-- | cheri/cheri_prelude_common.sail | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cheri/cheri_prelude_common.sail b/cheri/cheri_prelude_common.sail index 0072ded7..09e07f70 100644 --- a/cheri/cheri_prelude_common.sail +++ b/cheri/cheri_prelude_common.sail @@ -185,6 +185,13 @@ bitfield CapCauseReg : bits(16) = { register CapCause : CapCauseReg +val execute_branch_pcc : CapStruct -> unit effect {wreg} +function execute_branch_pcc(newPCC) = { + delayedPC = to_bits(64, getCapOffset(newPCC)); + delayedPCC = capStructToCapReg(newPCC); + branchPending = 0b1; +} + function SignalException (ex) = { if (not (CP0Status.EXL())) then { |