Merge remote-tracking branch 'origin/master' into experiments

1 files changed, 335 insertions, 0 deletions

diff --git a/arm/gen/herdtools_ast_to_shallow_ast.hgen b/arm/gen/herdtools_ast_to_shallow_ast.hgen
new file mode 100644
index 00000000..5a19e483
--- /dev/null
+++ b/arm/gen/herdtools_ast_to_shallow_ast.hgen
@@ -0,0 +1,335 @@
+| `AArch64TMStart t -> TMStart (translate_reg "t" t)
+
+| `AArch64TMCommit -> TMCommit
+
+| `AArch64TMAbort (retry,reason) ->
+    TMAbort
+      (translate_boolean "retry" retry,
+        translate_bit5 "reason" reason)
+
+| `AArch64TMTest -> TMTest
+
+| `AArch64ImplementationDefinedStopFetching ->
+    ImplementationDefinedStopFetching
+
+| `AArch64ImplementationDefinedThreadStart ->
+    ImplementationDefinedThreadStart
+
+| `AArch64ImplementationDefinedTestBeginEnd(isEnd) ->
+    ImplementationDefinedTestBeginEnd
+      (translate_boolean "isEnd" isEnd)
+
+| `AArch64AddSubCarry(d,n,m,datasize,sub_op,setflags) ->
+    AddSubCarry
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_boolean "setflags" setflags)
+
+| `AArch64AddSubExtendRegister (d,n,m,datasize,sub_op,setflags,extend_type,shift) ->
+    AddSubExtendRegister
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_boolean "setflags" setflags,
+        translate_extendType "extend_type" extend_type,
+        translate_range0_7 "shift" shift)
+
+| `AArch64AddSubShiftedRegister (d,n,m,datasize,sub_op,setflags,shift_type,shift_amount) ->
+    AddSubShiftedRegister
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_boolean "setflags" setflags,
+        translate_shiftType "shift_type" shift_type,
+        translate_range0_63 "shift_amount" shift_amount)
+
+| `AArch64AddSubImmediate (d,n,datasize,sub_op,setflags,imm) ->
+    AddSubImmediate
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_boolean "setflags" setflags,
+        translate_reg_size_bits "imm" imm)
+
+| `AArch64Address (d,page,imm) ->
+    Address0
+      (translate_reg "d" d,
+        translate_boolean "page" page,
+        translate_bit64 "imm" imm)
+
+| `AArch64LogicalImmediate (d,n,datasize,setflags,op,imm) ->
+    LogicalImmediate
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "setflags" setflags,
+        translate_logicalOp "op" op,
+        translate_reg_size_bits "imm" imm)
+
+| `AArch64LogicalShiftedRegister (d,n,m,datasize,setflags,op,shift_type,shift_amount,invert) ->
+  LogicalShiftedRegister
+    (translate_reg "d" d,
+      translate_reg "n" n,
+      translate_reg "m" m,
+      translate_reg_size "datasize" datasize,
+      translate_boolean "setflags" setflags,
+      translate_logicalOp "op" op,
+      translate_shiftType "shift_type" shift_type,
+      translate_range0_63 "shift_amount" shift_amount,
+      translate_boolean "invert" invert)
+
+| `AArch64Shift (d,n,m,datasize,shift_type) ->
+    Shift
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_shiftType "shift_type" shift_type)
+
+| `AArch64BranchConditional (offset,condition) ->
+    BranchConditional
+      (translate_bit64 "offset" offset,
+        translate_bit4 "condition" condition)
+
+| `AArch64BranchImmediate (branch_type,offset) ->
+    BranchImmediate
+      (translate_branchType "branch_type" branch_type,
+        translate_bit64 "offset" offset)
+
+| `AArch64BitfieldMove (d,n,datasize,inzero,extend,_R,_S,wmask,tmask) ->
+    BitfieldMove
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "inzero" inzero,
+        translate_boolean "extend" extend,
+        translate_uinteger "_R" _R,
+        translate_uinteger "_S" _S,
+        translate_reg_size_bits "wmask" wmask,
+        translate_reg_size_bits "tmask" tmask)
+
+| `AArch64BranchRegister (n,branch_type) ->
+    BranchRegister
+      (translate_reg "n" n,
+        translate_branchType "branch_type" branch_type)
+
+| `AArch64CompareAndBranch (t,datasize,iszero,offset) ->
+    CompareAndBranch
+      (translate_reg "t" t,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "iszero" iszero,
+        translate_bit64 "offset" offset)
+
+| `AArch64ConditionalCompareImmediate (n,datasize,sub_op,condition,flags,imm) ->
+    ConditionalCompareImmediate
+      (translate_reg "n" n,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_bit4 "condition" condition,
+        translate_bit4 "flags" flags,
+        translate_reg_size_bits "imm" imm)
+
+| `AArch64ConditionalCompareRegister (n,m,datasize,sub_op,condition,flags) ->
+    ConditionalCompareRegister
+      (translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_bit4 "condition" condition,
+        translate_bit4 "flags" flags)
+
+| `AArch64ClearExclusiveMonitor (imm) ->
+    ClearExclusiveMonitor
+      (translate_uinteger "imm" imm)
+
+| `AArch64CountLeading (d,n,datasize,opcode) ->
+    CountLeading
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg_size "datasize" datasize,
+        translate_countOp "opcode" opcode)
+
+| `AArch64CRC (d,n,m,size,crc32c) ->
+    CRC
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_data_size "size" size,
+        translate_boolean "crc32c" crc32c)
+
+| `AArch64ConditionalSelect (d,n,m,datasize,condition,else_inv,else_inc) ->
+    ConditionalSelect
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_bit4 "condition" condition,
+        translate_boolean "else_inv" else_inv,
+        translate_boolean "else_inc" else_inc)
+
+| `AArch64Barrier (op,domain,types) ->
+    Barrier2
+      (translate_memBarrierOp "op" op,
+        translate_mBReqDomain "domain" domain,
+        translate_mBReqTypes "types" types)
+
+| `AArch64ExtractRegister (d,n,m,datasize,lsb) ->
+    ExtractRegister
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_uinteger "lsb" lsb)
+
+| `AArch64Hint (op) ->
+  Hint
+    (translate_systemHintOp "op" op)
+
+| `AArch64LoadStoreAcqExc (n,t,t2,s,acctype,excl,pair,memop,elsize,regsize,datasize) ->
+    LoadStoreAcqExc
+      (translate_reg "n" n,
+        translate_reg "t" t,
+        translate_reg "t2" t2,
+        translate_reg "s" s,
+        translate_accType "acctype" acctype,
+        translate_boolean "excl" excl,
+        translate_boolean "pair" pair,
+        translate_memOp "memop" memop,
+        translate_uinteger "elsize" elsize,
+        translate_reg_size "regsize" regsize,
+        translate_data_size "datasize" datasize)
+
+| `AArch64LoadStorePair (wback,postindex,n,t,t2,acctype,memop,signed,datasize,offset) ->
+    LoadStorePair
+      (translate_boolean "wback" wback,
+        translate_boolean "postindex" postindex,
+        translate_reg "n" n,
+        translate_reg "t" t,
+        translate_reg "t2" t2,
+        translate_accType "acctype" acctype,
+        translate_memOp "memop" memop,
+        translate_boolean "signed" signed,
+        translate_data_size "datasize" datasize,
+        translate_bit64 "offset" offset)
+
+| `AArch64LoadImmediate (n,t,acctype,memop,signed,wback,postindex,offset,regsize,datasize) ->
+    LoadImmediate
+      (translate_reg "n" n,
+        translate_reg "t" t,
+        translate_accType "acctype" acctype,
+        translate_memOp "memop" memop,
+        translate_boolean "signed" signed,
+        translate_boolean "wback" wback,
+        translate_boolean "postindex" postindex,
+        translate_bit64 "offset" offset,
+        translate_reg_size "regsize" regsize,
+        translate_data_size "datasize" datasize)
+
+| `AArch64LoadLiteral (t,memop,signed,size,offset,datasize) ->
+    LoadLiteral
+      (translate_reg "t" t,
+        translate_memOp "memop" memop,
+        translate_boolean "signed" signed,
+        translate_uinteger "size" size,
+        translate_bit64 "offset" offset,
+        translate_data_size "datasize" datasize)
+
+| `AArch64LoadRegister (n,t,m,acctype,memop,signed,wback,postindex,extend_type,shift,regsize,datasize) ->
+    LoadRegister
+      (translate_reg "n" n,
+        translate_reg "t" t,
+        translate_reg "m" m,
+        translate_accType "acctype" acctype,
+        translate_memOp "memop" memop,
+        translate_boolean "signed" signed,
+        translate_boolean "wback" wback,
+        translate_boolean "postindex" postindex,
+        translate_extendType "extend_type" extend_type,
+        translate_uinteger "shift" shift,
+        translate_reg_size "regsize" regsize,
+        translate_data_size "datasize" datasize)
+
+| `AArch64MultiplyAddSub (d,n,m,a,destsize,datasize,sub_op) ->
+    MultiplyAddSub
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg "a" a,
+        translate_reg_size "destsize" destsize,
+        translate_data_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op)
+
+| `AArch64MoveWide (d,datasize,imm,pos,opcode) ->
+    MoveWide
+      (translate_reg "d" d,
+        translate_reg_size "datasize" datasize,
+        translate_bit16 "imm" imm,
+        translate_uinteger "pos" pos,
+        translate_moveWideOp "opcode" opcode)
+
+| `AArch64Reverse (d,n,datasize,op) ->
+    Reverse
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg_size "datasize" datasize,
+        translate_revOp "op" op)
+
+| `AArch64Division (d,n,m,datasize,unsigned) ->
+    Division
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg_size "datasize" datasize,
+        translate_boolean "unsigned" unsigned)
+
+| `AArch64MultiplyAddSubLong (d,n,m,a,destsize,datasize,sub_op,unsigned) ->
+    MultiplyAddSubLong
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg "a" a,
+        translate_reg_size "destsize" destsize,
+        translate_data_size "datasize" datasize,
+        translate_boolean "sub_op" sub_op,
+        translate_boolean "unsigned" unsigned)
+
+| `AArch64MultiplyHigh (d,n,m,a,destsize,datasize,unsigned) ->
+    MultiplyHigh
+      (translate_reg "d" d,
+        translate_reg "n" n,
+        translate_reg "m" m,
+        translate_reg "a" a,
+        translate_reg_size "destsize" destsize,
+        translate_data_size "datasize" datasize,
+        translate_boolean "unsigned" unsigned)
+
+| `AArch64TestBitAndBranch (t,datasize,bit_pos,bit_val,offset) ->
+    TestBitAndBranch
+      (translate_reg "t" t,
+        translate_reg_size "datasize" datasize,
+        translate_uinteger "bit_pos" bit_pos,
+        translate_bit "bit_val" bit_val,
+        translate_bit64 "offset" offset)
+
+| `AArch64MoveSystemRegister (t,sys_op0,sys_op1,sys_op2,sys_crn,sys_crm,read) ->
+    MoveSystemRegister
+      (translate_reg "t" t,
+        translate_uinteger "sys_op0" sys_op0,
+        translate_uinteger "sys_op1" sys_op1,
+        translate_uinteger "sys_op2" sys_op2,
+        translate_uinteger "sys_crn" sys_crn,
+        translate_uinteger "sys_crm" sys_crm,
+        translate_boolean "read" read)
+
+| `AArch64MoveSystemImmediate (operand,field) ->
+    MoveSystemImmediate
+      (translate_bit4 "operand" operand,
+        translate_pSTATEField "field" field)