diff options
| author | Shaked Flur | 2019-03-08 21:28:09 +0000 |
|---|---|---|
| committer | Shaked Flur | 2019-03-08 21:28:09 +0000 |
| commit | 25be39a23ad9828b2d67ef7f66ecc52708ed8a3a (patch) | |
| tree | be4193009843e48a1af291b2fbb86776b86bb18a /aarch64_small | |
| parent | 70bd4e69c0e520d46c65129a731714eb04ca6847 (diff) | |
wib
Diffstat (limited to 'aarch64_small')
| -rw-r--r-- | aarch64_small/armV8.sail | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/aarch64_small/armV8.sail b/aarch64_small/armV8.sail index d52099c0..f125ec72 100644 --- a/aarch64_small/armV8.sail +++ b/aarch64_small/armV8.sail @@ -478,7 +478,7 @@ function clause decodeSystem (0b1101010100@[L]@0b01@(op1 : bits(3))@(CRn : bits( sysop = SysOp(op1,CRn,CRm,op2); match sysop { - Sys_AT => {not_implemented("AT"); None ();}, + Sys_AT => not_implemented("AT"), Sys_DC => match (op1, CRm, op2) { @@ -490,7 +490,7 @@ function clause decodeSystem (0b1101010100@[L]@0b01@(op1 : bits(3))@(CRn : bits( (0b011, 0b1010, 0b001) => Some(DataCache(t,CVAC)), (0b011, 0b1011, 0b001) => Some(DataCache(t,CVAU)), (0b011, 0b1110, 0b001) => Some(DataCache(t,CIVAC)), - _ => {assert(false); None ();} + _ => error("should never happen") }, Sys_IC => @@ -498,10 +498,10 @@ function clause decodeSystem (0b1101010100@[L]@0b01@(op1 : bits(3))@(CRn : bits( (0b000, 0b0001, 0b000) => Some(InstructionCache(t,IALLUIS)), (0b000, 0b0101, 0b000) => Some(InstructionCache(t,IALLU)), (0b011, 0b0101, 0b001) => Some(InstructionCache(t,IVAU)), - _ => {assert(false); None ();} + _ => error("should never happen") }, - Sys_TLBI => {not_implemented("TLBI"); None ();}, + Sys_TLBI => not_implemented("TLBI"), Sys_SYS => { sys_op0 : uinteger = 1; |