checking in in-progress translation of Shaked's handwritten sail1 ARM model to sail2

1 files changed, 61 insertions, 0 deletions

diff --git a/aarch64_small/armV8_A32_sys_regs.sail b/aarch64_small/armV8_A32_sys_regs.sail
new file mode 100644
index 00000000..9a7f49c4
--- /dev/null
+++ b/aarch64_small/armV8_A32_sys_regs.sail
@@ -0,0 +1,61 @@
+/*========================================================================*/
+/*                                                                        */
+/*  Copyright (c) 2015-2017 Shaked Flur                                   */
+/*  Copyright (c) 2015-2017 Kathyrn Gray                                  */
+/*  All rights reserved.                                                  */
+/*                                                                        */
+/*  This software was developed by the University of Cambridge Computer   */
+/*  Laboratory as part of the Rigorous Engineering of Mainstream Systems  */
+/*  (REMS) project, funded by EPSRC grant EP/K008528/1.                   */
+/*                                                                        */
+/*  Redistribution and use in source and binary forms, with or without    */
+/*  modification, are permitted provided that the following conditions    */
+/*  are met:                                                              */
+/*  1. Redistributions of source code must retain the above copyright     */
+/*     notice, this list of conditions and the following disclaimer.      */
+/*  2. Redistributions in binary form must reproduce the above copyright  */
+/*     notice, this list of conditions and the following disclaimer in    */
+/*     the documentation and/or other materials provided with the         */
+/*     distribution.                                                      */
+/*                                                                        */
+/*  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''    */
+/*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     */
+/*  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A       */
+/*  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR   */
+/*  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,          */
+/*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT      */
+/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF      */
+/*  USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND   */
+/*  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,    */
+/*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    */
+/*  OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF    */
+/*  SUCH DAMAGE.                                                          */
+/*========================================================================*/
+
+/*************************************************************************/
+/* General system control registers */
+
+register SCR : SCRType /* Secure Configuration Register */
+
+/*************************************************************************/
+/* Debug registers */
+
+bitfield DBGOSDLR_type : bits(32) =
+{
+  /*RES0 : 31..1,*/
+  DLK : 0,
+}
+register DBGOSDLR : DBGOSDLR_type /* Debug OS Double Lock Register */
+
+register DBGPRCR : DBGPRCR_type /* Debug Power Control Register */
+
+
+/*************************************************************************/
+/* Performance Monitors registers */
+
+/*************************************************************************/
+/* Generic Timer registers */
+
+/*************************************************************************/
+/* Generic Interrupt Controller CPU interface registers */
+