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authorBrian Campbell2018-07-13 10:15:30 +0100
committerBrian Campbell2018-07-13 10:15:30 +0100
commit82784b669df18e33c48449020f29f36980d12bf3 (patch)
treee8c9d854b3edd3d34c64e745705e9cce4dc877a1 /aarch64
parent6586abcc185fa4e0f3853a73d91f097fbde16aca (diff)
parent3c4a27d7041d71fb229970dacab013cf84669755 (diff)
Merge branch 'sail2' of github.com:rems-project/sail into sail2
Diffstat (limited to 'aarch64')
-rw-r--r--aarch64/no_devices.sail4
1 files changed, 2 insertions, 2 deletions
diff --git a/aarch64/no_devices.sail b/aarch64/no_devices.sail
index 882aa6b3..57dad4e2 100644
--- a/aarch64/no_devices.sail
+++ b/aarch64/no_devices.sail
@@ -1,6 +1,6 @@
val ___WriteRAM = "write_ram" : forall 'n 'm.
- (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+ (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> bool effect {wmem}
val __InitRAM : forall 'm. (atom('m), int, bits('m), bits(8)) -> unit
@@ -25,7 +25,7 @@ val __WriteRAM : forall 'n 'm.
function __WriteRAM(addr_length, bytes, hex_ram, addr, data) =
{
- ___WriteRAM(addr_length, bytes, hex_ram, addr, data)
+ let _ = ___WriteRAM(addr_length, bytes, hex_ram, addr, data) in ()
}
function __TraceMemoryWrite(bytes, addr, data) = ()