diff options
| author | Alastair Reid | 2018-07-03 15:13:29 +0100 |
|---|---|---|
| committer | Alastair Reid | 2018-07-04 16:30:54 +0100 |
| commit | 0e9828b2aea47e54b4f692da5e5e09036e58cc91 (patch) | |
| tree | dc7023ce6fb0c84eaf62bd4be1e8414a683ffa04 /aarch64 | |
| parent | c093e0d61eda7b076492e565995649ad0c04919c (diff) | |
AArch64 Prelude: Move cycle count primop to prelude
Diffstat (limited to 'aarch64')
| -rw-r--r-- | aarch64/elfmain.sail | 2 | ||||
| -rwxr-xr-x | aarch64/prelude.sail | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail index 44b6c14a..24579b79 100644 --- a/aarch64/elfmain.sail +++ b/aarch64/elfmain.sail @@ -13,8 +13,6 @@ let CNT_IRQ = [0x0000_000d, 0x0000_000a, 0x0000_03ff, 0x000 // SGI Interrupts are 0-15, PPI interrupts are 16-31, so SPI interrupts have an offset of 32. let SPI_OFFSET = 32 -val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem} - // Advance CPU by one cycle val Step_CPU : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem} diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail index 73a084c4..6ce47ae3 100755 --- a/aarch64/prelude.sail +++ b/aarch64/prelude.sail @@ -358,3 +358,5 @@ val __Sleeping = {ocaml: "sleeping", lem: "sleeping", smt: "sleeping", interpret val __GetVerbosity = {c: "sail_get_verbosity"}: unit -> bits(64) effect {rreg, undef} +val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem} + |