Add no_devices.sail to be compatible with latest AArch64 prelude and

update aarch64 model

1 files changed, 35 insertions, 0 deletions

diff --git a/aarch64/no_devices.sail b/aarch64/no_devices.sail
new file mode 100644
index 00000000..882aa6b3
--- /dev/null
+++ b/aarch64/no_devices.sail
@@ -0,0 +1,35 @@
+
+val ___WriteRAM = "write_ram" : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+
+val __InitRAM : forall 'm. (atom('m), int, bits('m), bits(8)) -> unit
+
+function __InitRAM (_, _, _, _) = ()
+
+val ___ReadRAM = "read_ram" : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val __ReadRAM : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+function __ReadRAM(addr_length, bytes, hex_ram, addr) =
+{
+  ___ReadRAM(addr_length, bytes, hex_ram, addr)
+}
+
+val __TraceMemoryWrite : forall 'n 'm.
+  (atom('n), bits('m), bits(8 * 'n)) -> unit
+
+val __WriteRAM : forall 'n 'm.
+  (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+
+function __WriteRAM(addr_length, bytes, hex_ram, addr, data) =
+{
+  ___WriteRAM(addr_length, bytes, hex_ram, addr, data)
+}
+
+function __TraceMemoryWrite(bytes, addr, data) = ()
+
+val __TraceMemoryRead : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit
+
+function __TraceMemoryRead(bytes, addr, data) = ()
\ No newline at end of file