diff options
| author | Alasdair Armstrong | 2018-01-26 22:53:22 +0000 |
|---|---|---|
| committer | Alasdair Armstrong | 2018-01-26 22:53:22 +0000 |
| commit | 3ea0add3e9b0e6c5ba9c74d533d7c44874d95beb (patch) | |
| tree | f6211e002678c3a7633a270f7bad978b7bddb3ae /aarch64/main.sail | |
| parent | 481f492ecc3179f5ea8293dab45c3712871c219e (diff) | |
Fixed loading ARM elf files
Also refactored the hand written ARM prelude and pulled out some common functionality into files in sail/lib
Diffstat (limited to 'aarch64/main.sail')
| -rw-r--r-- | aarch64/main.sail | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/aarch64/main.sail b/aarch64/main.sail index b48f84d9..eaaf4f7f 100644 --- a/aarch64/main.sail +++ b/aarch64/main.sail @@ -1,12 +1,14 @@ -val fetch_and_execute : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem} +$include <elf.sail> -function fetch_and_execute () = while true do { - let instr = aget_Mem(_PC, 4, AccType_IFETCH); - decode(instr); - if __BranchTaken then __BranchTaken = false else _PC = _PC + 4 -} +// Simple top level fetch and execute loop. +val fetch_and_execute : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem} -val elf_entry = "Elf_loader.elf_entry" : unit -> int +function fetch_and_execute () = + while true do { + let instr = aget_Mem(_PC, 4, AccType_IFETCH); + decode(instr); + if __BranchTaken then __BranchTaken = false else _PC = _PC + 4 + } val main : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem} |
