diff options
| author | Thomas Bauereiss | 2018-01-27 11:41:26 +0000 |
|---|---|---|
| committer | Thomas Bauereiss | 2018-01-27 11:41:26 +0000 |
| commit | f6b35a7dba6acad62afb9d481e2bf2dfdbc312b4 (patch) | |
| tree | ca03831cf840c37929186af211d180c3c31ee6de | |
| parent | 3ea0add3e9b0e6c5ba9c74d533d7c44874d95beb (diff) | |
Add Makefile for RISC-V
| -rw-r--r-- | riscv/Makefile | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/riscv/Makefile b/riscv/Makefile new file mode 100644 index 00000000..fabaaafc --- /dev/null +++ b/riscv/Makefile @@ -0,0 +1,24 @@ +SAIL_SRCS = prelude.sail riscv_types.sail riscv.sail +SAIL_DIR ?= $(realpath ..) + +export SAIL_DIR + +all: riscv Riscv_embed_sequential.thy + +riscv: $(SAIL_SRCS) main.sail + $(SAIL_DIR)/sail -ocaml -o riscv $^ + +Riscv_embed_sequential.thy: riscv_embed_sequential.lem riscv_extras_embed_sequential.lem + lem -isa -outdir . -lib ../src/lem_interp -lib ../src/gen_lib \ + riscv_extras_embed_sequential.lem \ + riscv_embed_types_sequential.lem \ + riscv_embed_sequential.lem + +riscv_embed_sequential.lem: $(SAIL_SRCS) + $(SAIL_DIR)/sail -lem -o riscv -lem_sequential -lem_mwords -lem_lib Riscv_extras_embed $^ + +clean: + -rm -rf riscv _sbuild + -rm -f riscv_embed_sequential.lem riscv_embed_types_sequential.lem + -rm -f Riscv_embed_sequential.thy Riscv_embed_types_sequential.thy \ + Riscv_extras_embed_sequential.thy |
