diff options
| author | Prashanth Mundkur | 2018-11-30 10:29:04 -0800 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-11-30 10:29:04 -0800 |
| commit | e25d469d7dfccc46db663ebcd4e00a5bfcac499a (patch) | |
| tree | 7cc653d7457eb9cd9e554ccd965772401d023728 | |
| parent | 4fd0c147e6c53ec64b7e4a8cd0324f6e8e56714f (diff) | |
RISC-V: update the riscv/readme to point to the new repository.
| -rw-r--r-- | riscv/README | 24 |
1 files changed, 2 insertions, 22 deletions
diff --git a/riscv/README b/riscv/README index b925821e..2748c897 100644 --- a/riscv/README +++ b/riscv/README @@ -1,23 +1,3 @@ -Booting Linux with the C backend: ---------------------------------- -The C model needs an ELF-version of the BBL (Berkeley-Boot-Loader) that contains -the Linux kernel as an embedded payload. It also needs a DTB (device-tree blob) -file describing the platform. Once those are available, the model should be run -as: - -$ ./riscv_sim -b spike.dtb bbl > execution-trace.log 2>&1 & -$ tail -f term.log - -The term.log file contains the console boot messages. - - -Booting Linux with the OCaml backend: -------------------------------------- - -The OCaml model only needs the ELF-version of the BBL, since it can generate its -own DTB. - -$ ./platform bbl > execution-trace.log - -The console output is sent to stderr. +Please use the repository at +https://github.com/rems-project/sail-riscv |