diff options
| author | Robert Norton | 2018-04-11 15:51:12 +0100 |
|---|---|---|
| committer | Robert Norton | 2018-04-12 12:32:22 +0100 |
| commit | c45b3e5aefc637fec1a3b7caa1ad01f2a795d7bc (patch) | |
| tree | bb58ae914ebe03eb15b543febcf3fc62859a3534 | |
| parent | a952a8815550b9ccefd4c067f87e15cbdf8d5d9e (diff) | |
Add missing read of UserLocal register using dmtc0 4, sel 2. Write was present but read was missing except via rdhwr.
| -rw-r--r-- | mips/mips_insts.sail | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail index 885608d1..a3781426 100644 --- a/mips/mips_insts.sail +++ b/mips/mips_insts.sail @@ -1433,6 +1433,7 @@ function clause execute (MFC0(rt, rd, sel, double)) = { (0b00010,0b000) => TLBEntryLo0.bits(), /* 2, TLB EntryLo0 */ (0b00011,0b000) => TLBEntryLo1.bits(), /* 3, TLB EntryLo1 */ (0b00100,0b000) => TLBContext.bits(), /* 4, TLB Context */ + (0b00100,0b010) => CP0UserLocal, (0b00101,0b000) => zero_extend(TLBPageMask @ 0x000), /* 5, TLB PageMask */ (0b00110,0b000) => zero_extend(TLBWired), /* 6, TLB Wired */ (0b00111,0b000) => zero_extend(CP0HWREna), /* 7, HWREna */ |