diff options
| author | Robert Norton | 2016-08-03 15:40:51 +0100 |
|---|---|---|
| committer | Robert Norton | 2016-09-14 14:22:00 +0100 |
| commit | c0599e6ea1fc97a8254040a82a9455b3adc46720 (patch) | |
| tree | 89c5917b644f033ef04fb2ab6bf42bd759920d6d | |
| parent | 02802d39d80669883edcc2fe9708f47c14472ee7 (diff) | |
Use cap_size to check for address alignment in csc/clc instead of hardcoded 32-byte alignment test.
| -rw-r--r-- | cheri/cheri_insts.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cheri/cheri_insts.sail b/cheri/cheri_insts.sail index 2885aea6..06a27dcb 100644 --- a/cheri/cheri_insts.sail +++ b/cheri/cheri_insts.sail @@ -766,7 +766,7 @@ function clause execute (CSC(cs, cb, rt, rd, offset, conditional)) = raise_c2_exception(CapEx_LengthViolation, cb) else if (vAddr < ((nat) (cb_val.base))) then raise_c2_exception(CapEx_LengthViolation, cb) - else if (vAddr64[4..0] != 0b00000) then + else if ((vAddr mod cap_size) != 0) then SignalExceptionBadAddr(AdES, vAddr64) else { @@ -815,7 +815,7 @@ function clause execute (CLC(cd, cb, rt, offset, linked)) = raise_c2_exception(CapEx_LengthViolation, cb) else if (vAddr < ((nat) (cb_val.base))) then raise_c2_exception(CapEx_LengthViolation, cb) - else if (vAddr64[4..0] != 0b00000) then + else if ((vAddr mod cap_size) != 0) then SignalExceptionBadAddr(AdEL, vAddr64) else { |