diff options
| author | Prashanth Mundkur | 2018-04-16 17:57:00 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-04-16 18:25:31 -0700 |
| commit | b655ffcff8f0220295f7f2dafde7036f12215abd (patch) | |
| tree | f9b865620381d48e7c6b6d078dce6301b8ab26da | |
| parent | 09867e0204bf29b17b16226764f9796e344bdaa4 (diff) | |
Implement the s-mode views of mie/mip, and their legalizers.
| -rw-r--r-- | riscv/riscv.sail | 11 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 66 |
2 files changed, 67 insertions, 10 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 69baea30..fe11af98 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -525,13 +525,13 @@ function readCSR csr: bits(12) -> xlenbits = 0x100 => mstatus.bits(), /* FIXME: legalize view*/ 0x102 => sedeleg.bits(), 0x103 => sideleg.bits(), - 0x104 => mie.bits(), /* FIXME: legalize view */ + 0x104 => lower_mie(mie, mideleg).bits(), 0x105 => stvec.bits(), 0x140 => sscratch, 0x141 => sepc, 0x142 => scause.bits(), 0x143 => stval, - 0x144 => mip.bits(), /* FIXME: legalize view */ + 0x144 => lower_mip(mip, mideleg).bits(), 0x180 => satp, /* others */ @@ -558,17 +558,16 @@ function writeCSR (csr : bits(12), value : xlenbits) -> unit = 0x344 => mip = legalize_mip(mip, value), /* supervisor mode */ - /* FIXME: need legalizers for interrupt regs and satp */ 0x100 => mstatus = legalize_sstatus(mstatus, value), 0x102 => sedeleg = legalize_sedeleg(sedeleg, value), - 0x103 => sideleg->bits() = value, - 0x104 => sie->bits() = value, + 0x103 => sideleg->bits() = value, /* TODO: does this need legalization? */ + 0x104 => mie = legalize_sie(mie, mideleg, value), 0x105 => stvec = legalize_tvec(stvec, value), 0x140 => sscratch = value, 0x141 => sepc = legalize_xepc(value), 0x142 => scause->bits() = value, 0x143 => stval = value, - 0x144 => mip->bits() = value, + 0x144 => mip = legalize_sip(mip, mideleg, value), 0x180 => satp = legalize_satp(cur_Architecture(), satp, value), _ => print_bits("unhandled write to CSR ", csr) diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 93a0199a..4807e31c 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -124,7 +124,6 @@ bitfield Minterrupts : bits(64) = { MSI : 3, /* software interrupts */ SSI : 1, USI : 0, - } register mip : Minterrupts /* Pending */ register mie : Minterrupts /* Enabled */ @@ -311,9 +310,68 @@ function legalize_sedeleg(s : Sedeleg, v : xlenbits) -> Sedeleg = { } /* TODO: handle views for interrupt delegation */ -register sideleg : Minterrupts -register sip : Minterrupts -register sie : Minterrupts +bitfield Sinterrupts : bits(64) = { + SEI : 9, /* external interrupts */ + UEI : 8, + + STI : 5, /* timers interrupts */ + UTI : 4, + + SSI : 1, /* software interrupts */ + USI : 0 +} + +/* Provides the sip read view of mip as delegated by mideleg. */ +function lower_mip(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { + let s : Sinterrupts = Mk_Sinterrupts(EXTZ(0b0)); + /* M-mode interrupts delegated to S-mode should appear as S-mode interrupts */ + let s = update_SEI(s, (m.SEI() & d.SEI()) | (m.MEI() & d.MEI())); + let s = update_STI(s, (m.STI() & d.STI()) | (m.MTI() & d.MTI())); + let s = update_SSI(s, (m.SSI() & d.SSI()) | (m.MSI() & d.MSI())); + + let s = update_UEI(s, m.UEI() & d.UEI()); + let s = update_UTI(s, m.UTI() & d.UTI()); + let s = update_USI(s, m.USI() & d.USI()); + s +} +/* Provides the sie read view of mie as delegated by mideleg. */ +function lower_mie(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { + let s : Sinterrupts = Mk_Sinterrupts(EXTZ(0b0)); + let s = update_SEI(s, m.SEI() & d.SEI()); + let s = update_STI(s, m.STI() & d.STI()); + let s = update_SSI(s, m.SSI() & d.SSI()); + let s = update_UEI(s, m.UEI() & d.UEI()); + let s = update_UTI(s, m.UTI() & d.UTI()); + let s = update_USI(s, m.USI() & d.USI()); + s +} +/* Provides the sip write view of mip as delegated by mideleg. */ +function lift_sip(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = { + let m : Minterrupts = o; + let m = update_SSI(m, s.SSI() & d.SSI()); + let m = update_UEI(m, m.UEI() & d.UEI()); + let m = update_USI(m, m.USI() & d.USI()); + m +} +function legalize_sip(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = { + lift_sip(m, d, Mk_Sinterrupts(v)) +} +/* Provides the sie write view of mie as delegated by mideleg. */ +function lift_sie(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = { + let m : Minterrupts = o; + let m = if d.SEI() == true then update_SEI(m, s.SEI()) else m; + let m = if d.STI() == true then update_STI(m, s.STI()) else m; + let m = if d.SSI() == true then update_SSI(m, s.SSI()) else m; + let m = if d.UEI() == true then update_UEI(m, s.UEI()) else m; + let m = if d.UTI() == true then update_UTI(m, s.UTI()) else m; + let m = if d.USI() == true then update_USI(m, s.USI()) else m; + m +} +function legalize_sie(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = { + lift_sie(m, d, Mk_Sinterrupts(v)) +} + +register sideleg : Sinterrupts bitfield Satp64 : bits(64) = { Mode : 63 .. 60, |
