Initial bits of supervisor state.

2 files changed, 89 insertions, 1 deletions

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 1471f504..e5380bd2 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -529,6 +529,7 @@ function isCSRImplemented csr : bits(12) -> bool =
 
 function readCSR csr: bits(12) -> xlenbits =
   match csr {
+    /* machine mode */
     0xF11 => mvendorid,
     0xF12 => marchid,
     0xF13 => mimpid,
@@ -543,13 +544,33 @@ function readCSR csr: bits(12) -> xlenbits =
     0x342 => mcause.bits(),
     0x343 => mtval,
     0x344 => mip.bits(),
+
+    /* supervisor mode */
+    0x100 => mstatus.bits(), /* FIXME: legalize view*/
+    0x102 => sedeleg.bits(),
+    0x103 => sideleg.bits(),
+    0x104 => mie.bits(),  /* FIXME: legalize view */
+    0x105 => stvec.bits(),
+    0x140 => sscratch,
+    0x141 => sepc,
+    0x142 => scause.bits(),
+    0x143 => stval,
+    0x144 => mip.bits(),  /* FIXME: legalize view */
+    0x180 => satp,
+
+    /* others */
+    0xC00 => mcycle,
+    0xC01 => mtime,
+    0xC02 => minstret,
+
     _     => { print_bits("unhandled read to CSR ", csr);
                0x0000_0000_0000_0000 }
   }
 
 function writeCSR (csr : bits(12), value : xlenbits) -> unit =
-  /* FIXME: need legalizers */
+  /* FIXME: need legalizers in many places */
   match csr {
+    /* machine mode */
     0x300 => mstatus->bits() = value,
     0x302 => medeleg->bits() = value,
     0x303 => mideleg->bits() = value,
@@ -560,6 +581,20 @@ function writeCSR (csr : bits(12), value : xlenbits) -> unit =
     0x342 => mcause->bits() = value,
     0x343 => mtval = value,
     0x344 => mip->bits() = value,
+
+    /* supervisor mode */
+    0x100 => mstatus->bits() = value,
+    0x102 => sedeleg->bits() = value,
+    0x103 => sideleg->bits() = value,
+    0x104 => mie->bits() = value,
+    0x105 => stvec->bits() = value,
+    0x140 => sscratch = value,
+    0x141 => sepc = value,
+    0x142 => scause->bits() = value,
+    0x143 => stval = value,
+    0x144 => mip->bits() = value,
+    0x180 => satp = value,
+
     _     => print_bits("unhandled write to CSR ", csr)
   }
 
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 43deacb0..dfad6f51 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -132,6 +132,11 @@ register mepc : xlenbits
 register mtval : xlenbits
 register mscratch : xlenbits
 
+/* time/cycles */
+register mcycle : xlenbits
+register mtime : xlenbits
+register minstret : xlenbits
+
 /* informational registers */
 register mvendorid : xlenbits
 register mimpid : xlenbits
@@ -143,6 +148,54 @@ register mhartid : xlenbits
 register pmpaddr0 : xlenbits
 register pmpcfg0 : xlenbits
 
+/* supervisor mode registers */
+
+bitfield Sstatus : bits(64) = {
+  SD   : 63,
+  UXL  : 33 .. 32,
+  MXR  : 19,
+  SUM  : 18,
+  XS   : 16 .. 15,
+  FS   : 14 .. 13,
+  SPP  : 8,
+  SPIE : 5,
+  UPIE : 4,
+  SIE  : 1,
+  UIE  : 0
+}
+/* This is a view, so there is no register defined. */
+
+bitfield Sedeleg : bits(64) = {
+  UEnvCall          : 8,
+  SAMO_Access_Fault : 7,
+  SAMO_Addr_Align   : 6,
+  Load_Access_Fault : 5,
+  Load_Addr_Align   : 4,
+  Breakpoint        : 3,
+  Illegal_Instr     : 2,
+  Fetch_Access_Fault: 1,
+  Fetch_Addr_Align  : 0
+}
+register sedeleg : Sedeleg
+
+/* TODO: handle views for interrupt delegation */
+register sideleg : Minterrupts
+register sip     : Minterrupts
+register sie     : Minterrupts
+
+bitfield satp64 : bits(64) = {
+  Mode : 63 .. 60,
+  Asid : 59 .. 44,
+  PPN  : 43 .. 0
+}
+
+register stvec : Mtvec
+register sscratch : xlenbits
+register sepc : xlenbits
+register scause : Mcause
+register stval : xlenbits
+register satp : xlenbits
+
 /* instruction control flow */
 
 struct sync_exception = {