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| author | Robert Norton | 2016-01-26 17:34:16 +0000 |
|---|---|---|
| committer | Robert Norton | 2016-01-26 17:34:16 +0000 |
| commit | 8b08f604226d47474c7b2a98909bcc2008b4856c (patch) | |
| tree | ea2a9b6380efe30ab7b17500aabb460008049fd4 | |
| parent | ec2d51546b5f6194048773da144b497194817357 (diff) | |
mips.sail: beginning of mfc0 implementation.
| -rw-r--r-- | mips/mips.sail | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/mips/mips.sail b/mips/mips.sail index 5b2dda70..3e6910c7 100644 --- a/mips/mips.sail +++ b/mips/mips.sail @@ -1490,6 +1490,20 @@ function clause decode (0b010000 : 0b00100 : (regno) rt : 0b10111 : 0b0000000000 function clause decode (0b010000 : 0b00100 : (regno) rt : 0b11010 : 0b00000000000) = Some(HCF()) (* simulator halt instruction "MTC0 rt, $26" (cheri specific behaviour) *) +union ast member (regno, regno, bit[3], bool) MFC0 +function clause decode (0b010000 : 0b00000 : (regno) rt : (regno) rd : 0b00000000 : (bit[3]) sel) = + Some(MFC0(rt, rd, sel, false) (* MCF0 *)) +function clause decode (0b010000 : 0b00001 : (regno) rt : (regno) rd : 0b00000000 : (bit[3]) sel) = + Some(MFC0(rt, rd, sel, true) (* DMCF0 *)) +function clause execute (MFC0(rt, rd, sel, double)) = + let (bit[64]) result = switch (rd, sel) + { + case (0b01111,0b000) -> 0 (* 15: PrID *) + case _ -> {SignalException(ResI); 0} + } in + wGPR(rt) := if (double) then result else EXTS(result[31..0]) + + function clause execute (HCF) = () (* halt instruction actually executed by interpreter framework *) |