Refactor main.sail

1 files changed, 38 insertions, 36 deletions

diff --git a/mips/main.sail b/mips/main.sail
index 8ec91ba6..54fb34ee 100644
--- a/mips/main.sail
+++ b/mips/main.sail
@@ -1,39 +1,35 @@
 
 register instCount : int
 
-val fetch_and_execute : unit -> unit effect {barr, eamem, escape, rmem, rreg, wmv, wreg, undef, wmvt, rmemt}
+val fetch_and_execute : unit -> bool effect {barr, eamem, escape, rmem, rreg, wmv, wreg, undef, wmvt, rmemt}
 function fetch_and_execute () = {
-  while true do {
-    PC = nextPC;
-    inBranchDelay = branchPending;
-    branchPending = 0b0;
-    nextPC = if inBranchDelay then delayedPC else PC + 4;
-    cp2_next_pc();
-    instCount = instCount + 1;
-    print_bits("PC: ", PC);
-    try {
-      let pc_pa = TranslatePC(PC);
-      /*print_bits("pa: ", pc_pa);*/
-      let instr = MEMr_wrapper(pc_pa, 4);
-      /*print_bits("hex: ", instr);*/
-      let instr_ast = decode(instr);
-      match instr_ast {
-        Some(HCF()) => {
-                       print("simulation stopped due to halt instruction.");
-                       return ();
-                     },
-        Some(ast) => execute(ast),
-        None()    => {print("Decode failed"); exit (())} /* Never expect this -- unknown instruction should actually result in reserved instruction ISA-level exception (see mips_ri.sail). */
-      }
-    } catch {
-      ISAException() => print("EXCEPTION")
-      /* ISA-level exception occurrred either during TranslatePC or execute --
-         just continue from nextPC, which should have been set to the appropriate
-         exception vector (along with clearing branchPending etc.) . */
-    };
+  PC = nextPC;
+  inBranchDelay = branchPending;
+  branchPending = 0b0;
+  nextPC = if inBranchDelay then delayedPC else PC + 4;
+  cp2_next_pc();
+  instCount = instCount + 1;
+  print_bits("PC: ", PC);
+  try {
+    let pc_pa = TranslatePC(PC);
+    /*print_bits("pa: ", pc_pa);*/
+    let instr = MEMr_wrapper(pc_pa, 4);
+    /*print_bits("hex: ", instr);*/
+    let instr_ast = decode(instr);
+    match instr_ast {
+      Some(HCF()) => {
+                     print("simulation stopped due to halt instruction.");
+                     false
+                   },
+      Some(ast) => { execute(ast); true },
+      None()    => { print("Decode failed"); exit (()) } /* Never expect this -- unknown instruction should actually result in reserved instruction ISA-level exception (see mips_ri.sail). */
+    }
+  } catch {
+    ISAException() => { print("EXCEPTION"); true }
+    /* ISA-level exception occurrred either during TranslatePC or execute --
+       just continue from nextPC, which should have been set to the appropriate
+       exception vector (along with clearing branchPending etc.) . */
   };
-  skip_rmemt();
-  skip_wmvt();
 }
 
 val elf_entry = {
@@ -42,7 +38,13 @@ val elf_entry = {
   c: "elf_entry"
 } : unit -> int
 
-val main : unit -> unit effect {barr, eamem, escape, rmem, rreg, undef, wmv, wreg, rmemt, wmvt}
+val init_registers : bits(64) -> unit effect {wreg}
+
+function init_registers (initialPC) = {
+  init_cp0_state();
+  init_cp2_state();
+  nextPC = initialPC;
+}
 
 function dump_mips_state () : unit -> unit = {
   print_bits("DEBUG MIPS PC ", PC);
@@ -51,12 +53,12 @@ function dump_mips_state () : unit -> unit = {
   }
 }
 
+val main : unit -> unit effect {barr, eamem, escape, rmem, rreg, undef, wmv, wreg, rmemt, wmvt}
+
 function main () = {
-  init_cp0_state();
-  init_cp2_state();
-  nextPC = to_bits(64, elf_entry());
+  init_registers(to_bits(64, elf_entry()));
   startTime = get_time_ns();
-  fetch_and_execute();
+  while (fetch_and_execute()) do ();
   endTime = get_time_ns();
   elapsed = endTime - startTime;
   inst_1e9 = instCount * 1000000000;