RISC-V: Flesh out more of the tandem checks in the C platform simulator.

2 files changed, 134 insertions, 7 deletions

diff --git a/riscv/riscv_sail.h b/riscv/riscv_sail.h
index b89a448a..596a8263 100644
--- a/riscv/riscv_sail.h
+++ b/riscv/riscv_sail.h
@@ -1,18 +1,41 @@
-/* Top-level entry points into the Sail model. */
+/* Top-level interfaces to the Sail model.
+   Ideally, this would be autogenerated.
+ */
 
 typedef int unit;
 #define UNIT 0
 typedef uint64_t mach_bits;
 
+void model_init(void);
+void model_fini(void);
+
 unit zinit_platform(unit);
 unit zinit_sys(unit);
 bool zstep(sail_int);
 
-void model_init(void);
-void model_fini(void);
-
 extern bool zhtif_done;
 extern mach_bits zhtif_exit_code;
 extern bool have_exception;
+
+/* machine state */
+
+extern uint32_t zcur_privilege;
+
 extern mach_bits zPC;
+
+extern mach_bits
+        zx1,  zx2,  zx3,  zx4,  zx5,  zx6,  zx7,
+  zx8,  zx9,  zx10, zx11, zx12, zx13, zx14, zx15,
+  zx16, zx17, zx18, zx19, zx20, zx21, zx22, zx23,
+  zx24, zx25, zx26, zx27, zx28, zx29, zx30, zx31;
+
+extern mach_bits zmepc, zmtval;
+extern mach_bits zsepc, zstval;
+
+struct zMcause {mach_bits zMcause_chunk_0;};
+struct zMcause zmcause, zscause;
+
 extern mach_bits zminstret;
+
+struct zMisa {mach_bits zMisa_chunk_0;};
+struct zMisa zmisa;
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c
index e2062053..c11e6268 100644
--- a/riscv/riscv_sim.c
+++ b/riscv/riscv_sim.c
@@ -10,6 +10,23 @@
 #include "riscv_sail.h"
 #include "tv_spike_intf.h"
 
+/* Selected CSRs from riscv-isa-sim/riscv/encoding.h */
+#define CSR_STVEC 0x105
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+
 struct tv_spike_t *s = NULL;
 
 static bool do_dump_dts = false;
@@ -79,7 +96,7 @@ uint64_t load_sail(char *f)
 /* for now, override the reset-vector using the elf entry */
 void init_spike(const char *f, uint64_t entry)
 {
-  s = tv_init("RV64IMAFDC");
+  s = tv_init("RV64IMAC");
   tv_set_verbose(s, 1);
   tv_load_elf(s, f);
   tv_reset(s);
@@ -94,10 +111,83 @@ void init_sail(uint64_t entry)
   zPC = entry;
 }
 
+int init_check(struct tv_spike_t *s)
+{
+  int passed = 1;
+  passed &= tv_check_csr(s, CSR_MISA, zmisa.zMisa_chunk_0);
+  return passed;
+}
+
+void finish(int ec)
+{
+  model_fini();
+  tv_free(s);
+  exit(ec);
+}
+
+int compare_states(struct tv_spike_t *s)
+{
+  int passed = 1;
+
+  // fix default C enum map for cur_privilege
+  uint8_t priv = (zcur_privilege == 2) ? 3 : zcur_privilege;
+  passed &= tv_check_priv(s, priv);
+
+  passed &= tv_check_pc(s, zPC);
+
+  passed &= tv_check_gpr(s, 1, zx1);
+  passed &= tv_check_gpr(s, 2, zx2);
+  passed &= tv_check_gpr(s, 3, zx3);
+  passed &= tv_check_gpr(s, 4, zx4);
+  passed &= tv_check_gpr(s, 5, zx5);
+  passed &= tv_check_gpr(s, 6, zx6);
+  passed &= tv_check_gpr(s, 7, zx7);
+  passed &= tv_check_gpr(s, 8, zx8);
+  passed &= tv_check_gpr(s, 9, zx9);
+  passed &= tv_check_gpr(s, 10, zx10);
+  passed &= tv_check_gpr(s, 11, zx11);
+  passed &= tv_check_gpr(s, 12, zx12);
+  passed &= tv_check_gpr(s, 13, zx13);
+  passed &= tv_check_gpr(s, 14, zx14);
+  passed &= tv_check_gpr(s, 15, zx15);
+  passed &= tv_check_gpr(s, 15, zx15);
+  passed &= tv_check_gpr(s, 16, zx16);
+  passed &= tv_check_gpr(s, 17, zx17);
+  passed &= tv_check_gpr(s, 18, zx18);
+  passed &= tv_check_gpr(s, 19, zx19);
+  passed &= tv_check_gpr(s, 20, zx20);
+  passed &= tv_check_gpr(s, 21, zx21);
+  passed &= tv_check_gpr(s, 22, zx22);
+  passed &= tv_check_gpr(s, 23, zx23);
+  passed &= tv_check_gpr(s, 24, zx24);
+  passed &= tv_check_gpr(s, 25, zx25);
+  passed &= tv_check_gpr(s, 25, zx25);
+  passed &= tv_check_gpr(s, 26, zx26);
+  passed &= tv_check_gpr(s, 27, zx27);
+  passed &= tv_check_gpr(s, 28, zx28);
+  passed &= tv_check_gpr(s, 29, zx29);
+  passed &= tv_check_gpr(s, 30, zx30);
+  passed &= tv_check_gpr(s, 31, zx31);
+
+  /* some selected CSRs for now */
+
+  passed &= tv_check_csr(s, CSR_MCAUSE, zmcause.zMcause_chunk_0);
+  passed &= tv_check_csr(s, CSR_MEPC, zmepc);
+  passed &= tv_check_csr(s, CSR_MTVAL, zmtval);
+
+  passed &= tv_check_csr(s, CSR_SCAUSE, zscause.zMcause_chunk_0);
+  passed &= tv_check_csr(s, CSR_SEPC, zsepc);
+  passed &= tv_check_csr(s, CSR_STVAL, zstval);
+
+  return passed;
+}
+
 void run_sail(void)
 {
   bool spike_done;
   bool stepped;
+  bool diverged = false;
+
   /* initialize the step number */
   mach_int step_no = 0;
 
@@ -131,13 +221,25 @@ void run_sail(void)
         fprintf(stdout, "Spike done, but not Sail!\n");
         exit(1);
       }
+
+      if (!compare_states(s)) {
+        diverged = true;
+        break;
+      }
+
       /* TODO: update time */
     }
   }
 
+ dump_state:
+  if (diverged) {
+    /* TODO */
+  }
+  finish(diverged);
+
  step_exception:
-  model_fini();
-  tv_free(s);
+  fprintf(stdout, "Sail exception!");
+  goto dump_state;
 }
 
 int main(int argc, char **argv)
@@ -148,5 +250,7 @@ int main(int argc, char **argv)
   init_sail(entry);
   init_spike(file, entry);
 
+  if (!init_check(s)) finish(1);
+
   run_sail();
 }