Initial handling of CSR reads/writes.

2 files changed, 56 insertions, 3 deletions

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 4e222add..9ef2365d 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -437,9 +437,36 @@ function isCSRImplemented csr : bits(12) -> bool =
     _     => false
   }
 
-function readCSR csr: bits(12) -> bits(64) = 0x0000_0000_0000_0000
+function readCSR csr: bits(12) -> regval =
+  match csr {
+    0x300 => mstatus.bits(),
+    0x302 => medeleg.bits(),
+    0x303 => mideleg.bits(),
+    0x304 => mie.bits(),
+    0x305 => mtvec,
+    0x340 => mscratch,
+    0x341 => mepc,
+    0x342 => mcause,
+    0x343 => mtval,
+    0x344 => mip.bits(),
+    _     => { print_bits("unhandled read to CSR ", csr);
+               0x0000_0000_0000_0000 }
+  }
 
-function writeCSR (csr : bits(12), value : bits(64)) -> unit = ()
+function writeCSR (csr : bits(12), value : bits(64)) -> unit =
+  match csr {
+    0x300 => mstatus->bits() = value,
+    0x302 => medeleg->bits() = value,
+    0x303 => mideleg->bits() = value,
+    0x304 => mie->bits() = value,
+    0x305 => mtvec = value,
+    0x340 => mscratch = value,
+    0x341 => mepc = value,
+    0x342 => mcause = value,
+    0x343 => mtval = value,
+    0x344 => mip->bits() = value,
+    _     => print_bits("unhandled write to CSR ", csr)
+  }
 
 function haveCSRPriv (csr : bits(12), isWrite : bool) -> bool =
   let isRO = csr[11..10] == 0b11 in
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 84002ed7..0eaadec4 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -39,6 +39,31 @@ enum ExceptionCode = {
   Store_PageFault
 }
 
+val exc_to_bits : ExceptionCode -> bits(4)
+function exc_to_bits e =
+  match (e) {
+    Misaligned_Fetch => 0x0,
+    Fetch_Access => 0x1,
+    Illegal_Instr => 0x2,
+    Breakpoint => 0x3,
+    Misaligned_Load => 0x4,
+
+    Load_Access => 0x5,
+    Misaligned_Store => 0x6,
+    Store_Access => 0x7,
+
+    User_ECall => 0x8,
+    Supervisor_ECall => 0x9,
+    ReservedExc0 => 0xa,
+    Machine_ECall => 0xb,
+
+    Fetch_PageFault => 0xc,
+    Load_PageFault => 0xd,
+    ReservedExc1 => 0xe,
+    Store_PageFaul => 0xf
+  }
+
+
 /* machine mode registers */
 
 /* FIXME: currently we have only those used by riscv-tests. */
@@ -141,6 +166,7 @@ register medeleg : Medeleg
 register mepc : regval
 register mtval : regval
 register mtvec : regval
+register mcause : regval
 register mscratch : regval
 
 /* other registers */
@@ -193,7 +219,7 @@ function handle_exception_ctl(cur_priv : privilege, ctl : ctl_result,
   match (cur_priv, ctl) {
     (_, CTL_TRAP(e)) => {
       mepc            = pc;
-      mcause          = e.trap;
+      mcause          = EXTZ(exc_to_bits(e.trap));
 
       mstatus->MPIE() = mstatus.MIE();
       mstatus->MIE()  = false;