RISC-V: Refactor c platform bits.

4 files changed, 52 insertions, 11 deletions

diff --git a/riscv/Makefile b/riscv/Makefile
index 80b3ebf7..5b615971 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -4,7 +4,8 @@ SAIL_DIR ?= $(realpath ..)
 SAIL ?= $(SAIL_DIR)/sail
 C_WARNINGS ?=
 #-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function
-C_SRCS = riscv_prelude.c riscv_platform.c
+C_INCS = riscv_prelude.h riscv_platform_impl.h riscv_platform.h
+C_SRCS = riscv_prelude.c riscv_platform_impl.c riscv_platform.c
 
 export SAIL_DIR
 
@@ -38,7 +39,7 @@ coverage: _sbuild/coverage.native
 riscv.c: $(SAIL_SRCS) main.sail Makefile
 	$(SAIL) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h $(SAIL_SRCS) main.sail 1> $@
 
-riscv_c: riscv.c riscv_prelude.h $(C_SRCS) Makefile
+riscv_c: riscv.c $(C_INCS) $(C_SRCS) Makefile
 	gcc $(C_WARNINGS) -O2 riscv.c $(C_SRCS) ../lib/*.c -lgmp -lz -I ../lib -o riscv_c
 
 latex: $(SAIL_SRCS) Makefile
diff --git a/riscv/riscv_platform.c b/riscv/riscv_platform.c
index 7f6ec470..31ec09c4 100644
--- a/riscv/riscv_platform.c
+++ b/riscv/riscv_platform.c
@@ -1,41 +1,44 @@
 #include "sail.h"
 #include "rts.h"
 #include "riscv_prelude.h"
+#include "riscv_platform_impl.h"
+
+/* This file contains the definitions of the C externs of Sail model. */
 
 bool plat_enable_dirty_update(unit u)
-{ return false; }
+{ return rv_enable_dirty_update; }
 
 bool plat_enable_misaligned_access(unit u)
-{ return false; }
+{ return rv_enable_misaligned; }
 
 mach_bits plat_ram_base(unit u)
 {
-  return UINT64_C(0x80000000);
+  return rv_ram_base;
 }
 
 mach_bits plat_ram_size(unit u)
 {
-  return UINT64_C(0x80000000);
+  return rv_rom_base;
 }
 
 mach_bits plat_rom_base(unit u)
 {
-  return UINT64_C(0x1000);
+  return rv_rom_base;
 }
 
 mach_bits plat_rom_size(unit u)
 {
-  return UINT64_C(0x100);
+  return rv_rom_size;
 }
 
 mach_bits plat_clint_base(unit u)
 {
-  return UINT64_C(0x2000000);
+  return rv_clint_base;
 }
 
 mach_bits plat_clint_size(unit u)
 {
-  return UINT64_C(0xc0000);
+  return rv_clint_size;
 }
 
 bool within_phys_mem(mach_bits addr, sail_int len)
@@ -62,7 +65,7 @@ void plat_insns_per_tick(sail_int *rop, unit u)
 
 mach_bits plat_htif_tohost(unit u)
 {
-  return UINT64_C(0x80001000);
+  return rv_htif_tohost;
 }
 
 unit memea(mach_bits len, sail_int n)
diff --git a/riscv/riscv_platform_impl.c b/riscv/riscv_platform_impl.c
new file mode 100644
index 00000000..1a1d42a7
--- /dev/null
+++ b/riscv/riscv_platform_impl.c
@@ -0,0 +1,17 @@
+#include "riscv_platform_impl.h"
+
+/* Settings of the platform implementation, with common defaults. */
+
+bool rv_enable_dirty_update = false;
+bool rv_enable_misaligned   = false;
+
+uint64_t rv_ram_base = UINT64_C(0x80000000);
+uint64_t rv_ram_size = UINT64_C(0x80000000);
+
+uint64_t rv_rom_base = UINT64_C(0x1000);
+uint64_t rv_rom_size = UINT64_C(0x100);
+
+uint64_t rv_clint_base = UINT64_C(0x2000000);
+uint64_t rv_clint_size = UINT64_C(0xc0000);
+
+uint64_t rv_htif_tohost = UINT64_C(0x80001000);
diff --git a/riscv/riscv_platform_impl.h b/riscv/riscv_platform_impl.h
new file mode 100644
index 00000000..baae2749
--- /dev/null
+++ b/riscv/riscv_platform_impl.h
@@ -0,0 +1,20 @@
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Settings of the platform implementation. */
+
+extern bool rv_enable_dirty_update;
+extern bool rv_enable_misaligned;
+
+extern uint64_t rv_ram_base;
+extern uint64_t rv_ram_size;
+
+extern uint64_t rv_rom_base;
+extern uint64_t rv_rom_size;
+
+extern uint64_t rv_clint_base;
+extern uint64_t rv_clint_size;
+
+extern uint64_t rv_htif_tohost;