diff options
| author | Robert Norton | 2018-09-21 15:09:08 +0100 |
|---|---|---|
| committer | Robert Norton | 2018-09-21 15:11:56 +0100 |
| commit | 2bdc5d09389c8fccd8100c0c07c54b2b8895c76a (patch) | |
| tree | 62264926985604d5d5e8aed4aa5130d7fed13417 | |
| parent | 30e1cdf6aabe611208c50e35058ea18442aa4078 (diff) | |
Remove cheri and mips specs -- they now have their own repository.
1644 files changed, 5 insertions, 16220 deletions
@@ -19,10 +19,6 @@ some Sail specifications and related tools. * The Sail source code (in [src/](src/)) -* A Sail specification of a MIPS ISA (in [mips/](mips/)) - -* A Sail specification of the CHERI MIPS ISA (in [cheri/](cheri/)) - * A Sail specification of ARMv8.3-A generated from ARM's publically released ASL specification (in [aarch64/](aarch64/)) @@ -40,6 +36,9 @@ hand-written fragment of ARMv8-A, but these are currently not up-to-date with the latest version of Sail, which is the (default) sail2 branch on Github. +The mips and cheri-mips specifications that used to be here have moved to +https://github.com/CTSRD-CHERI/sail-cheri-mips . + OPAM Installation ================= diff --git a/cheri/.gitignore b/cheri/.gitignore deleted file mode 100644 index f7f98624..00000000 --- a/cheri/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -cheri.lem -cheri_types.lem -cheriScript.sml -cheri_typesScript.sml -mips_extrasScript.sml
\ No newline at end of file diff --git a/cheri/Holmakefile b/cheri/Holmakefile deleted file mode 100644 index d64fc3fd..00000000 --- a/cheri/Holmakefile +++ /dev/null @@ -1,11 +0,0 @@ -LEMDIR=../../lem/hol-lib - -INCLUDES = $(LEMDIR) ../lib/hol - -all: cheriTheory.uo -.PHONY: all - -ifdef POLY -BASE_HEAP = ../lib/hol/sail-heap - -endif diff --git a/cheri/LOOKING_FOR_SOMETHING.txt b/cheri/LOOKING_FOR_SOMETHING.txt new file mode 100644 index 00000000..7cd539a3 --- /dev/null +++ b/cheri/LOOKING_FOR_SOMETHING.txt @@ -0,0 +1 @@ +The cheri spec. now lives at https://github.com/CTSRD-CHERI/sail-cheri-mips . diff --git a/cheri/Makefile b/cheri/Makefile deleted file mode 100644 index 3d02bfad..00000000 --- a/cheri/Makefile +++ /dev/null @@ -1,137 +0,0 @@ -THIS_MAKEFILE := $(realpath $(lastword $(MAKEFILE_LIST))) -SAIL_DIR:=$(realpath $(dir $(THIS_MAKEFILE))..) -export SAIL_DIR -SAIL_LIB_DIR:=$(SAIL_DIR)/lib -MIPS_SAIL_DIR:=$(SAIL_DIR)/mips -CHERI_SAIL_DIR:=$(SAIL_DIR)/cheri -SAIL:=$(SAIL_DIR)/sail -SAIL_LIB_HEADERS:= - -MIPS_PRE:=$(MIPS_SAIL_DIR)/prelude.sail $(MIPS_SAIL_DIR)/mips_prelude.sail -MIPS_TLB:=$(MIPS_SAIL_DIR)/mips_tlb.sail -MIPS_TLB_STUB:=$(MIPS_SAIL_DIR)/mips_tlb_stub.sail -MIPS_INSTS:=$(MIPS_SAIL_DIR)/mips_insts.sail -MIPS_EPILOGUE:=$(MIPS_SAIL_DIR)/mips_ri.sail $(MIPS_SAIL_DIR)/mips_epilogue.sail -CHERI_PRE:=$(CHERI_SAIL_DIR)/cheri_types.sail $(CHERI_SAIL_DIR)/cheri_prelude_256.sail $(CHERI_SAIL_DIR)/cheri_prelude_common.sail -CHERI128_PRE:=$(CHERI_SAIL_DIR)/cheri_types.sail $(CHERI_SAIL_DIR)/cheri_prelude_128.sail $(CHERI_SAIL_DIR)/cheri_prelude_common.sail -CHERI_INSTS:=$(CHERI_SAIL_DIR)/cheri_insts.sail - -CHERI_SAILS:=$(SAIL_LIB_HEADERS) $(MIPS_PRE) $(MIPS_TLB) $(CHERI_PRE) $(MIPS_INSTS) $(CHERI_INSTS) $(MIPS_EPILOGUE) -CHERI_MONO_SAILS:=$(SAIL_LIB_HEADERS) $(MIPS_PRE) $(SAIL_LIB_DIR)/mono_rewrites.sail $(MIPS_TLB) $(CHERI_PRE) $(MIPS_INSTS) $(CHERI_INSTS) $(MIPS_EPILOGUE) -CHERI_NO_TLB_SAILS:=$(SAIL_LIB_HEADERS) $(MIPS_PRE) $(MIPS_TLB_STUB) $(CHERI_PRE) $(MIPS_INSTS) $(CHERI_INSTS) $(MIPS_EPILOGUE) -CHERI128_SAILS:=$(SAIL_LIB_HEADERS) $(MIPS_PRE) $(MIPS_TLB) $(CHERI128_PRE) $(MIPS_INSTS) $(CHERI_INSTS) $(MIPS_EPILOGUE) -CHERI128_NO_TLB_SAILS:=$(SAIL_LIB_HEADERS) $(MIPS_PRE) $(MIPS_TLB_STUB) $(CHERI128_PRE) $(MIPS_INSTS) $(CHERI_INSTS) $(MIPS_EPILOGUE) -CHERI_MAIN:=$(MIPS_SAIL_DIR)/main.sail - -cheri: $(CHERI_SAILS) $(CHERI_MAIN) - $(SAIL) -ocaml -o $@ $^ - -cheri_coverage: $(CHERI_SAILS) $(CHERI_MAIN) - $(SAIL) -ocaml-coverage -ocaml -o $@ $^ - -cheri_trace: $(CHERI_SAILS) $(CHERI_MAIN) - $(SAIL) -ocaml_trace -o $@ $^ - -coverage_report: bisect*.out - bisect-ppx-report -I _sbuild/_build -html $@ $^ - -cheri.c: $(CHERI_SAILS) $(CHERI_MAIN) - $(SAIL) -memo_z3 -O -c $^ 1> $@ - -C_OPT=-O2 -GCOV_FLAGS= -cheri_c: cheri.c ../lib/sail.h Makefile - gcc $(C_OPT) $(GCOV_FLAGS) $< ../lib/*.c -lgmp -lz -I ../lib/ -o $@ - -# Note that for coverage purposes O1 appears optimal. O0 means lots of obviously dead code but O2 risks reducing granularity too much. -cheri_c_gcov: C_OPT=-O1 -cheri_c_gcov: GCOV_FLAGS=-fprofile-arcs -ftest-coverage -cheri_c_gcov: cheri_c - -gcovr: - gcovr -r . --html --html-detail -o index.html - -latex_128: $(MIPS_SAIL_DIR)/prelude.sail $(CHERI_SAIL_DIR)/cheri_types.sail $(CHERI_SAIL_DIR)/cheri_prelude_128.sail - rm -rf sail_latexcc - $(SAIL) -latex -latex_prefix sailcc -o sail_latexcc $^ - -latex_256: $(CHERI_SAILS) - rm -rf sail_latex - $(SAIL) -latex $^ - -latex: latex_128 latex_256 - -# to install latex in the right place - specific to PS checkouts -CHERI_ARCH_PATH=/home/pes20/repos/ctsrd/reports/cheri-architecture -install_latex: - rm -rf $(CHERI_ARCH_PATH)/sail_latex/*.tex - cp sail_latex/*.tex $(CHERI_ARCH_PATH)/sail_latex - rm -rf $(CHERI_ARCH_PATH)/sail_latexcc/*.tex - cp sail_latexcc/*.tex $(CHERI_ARCH_PATH)/sail_latexcc - -cheri128: $(CHERI128_SAILS) $(CHERI_MAIN) - $(SAIL) -ocaml -o $@ $^ - -cheri128_trace: $(CHERI128_SAILS) $(CHERI_MAIN) - $(SAIL) -ocaml_trace -o $@ $^ - -cheri128.c: $(CHERI128_SAILS) $(CHERI_MAIN) - $(SAIL) -memo_z3 -O -c $^ 1> $@ - -cheri128_c: cheri128.c ../lib/sail.h Makefile - gcc $(C_OPT) $(GCOV_FLAGS) $< ../lib/*.c -lgmp -lz -I ../lib/ -o $@ - -# Note that for coverage purposes O1 appears optimal. O0 means lots of obviously dead code but O2 risks reducing granularity too much. -cheri128_c_gcov: C_OPT=-O1 -cheri128_c_gcov: GCOV_FLAGS=-fprofile-arcs -ftest-coverage -cheri128_c_gcov: cheri128_c - -LOC_FILES:=$(CHERI_SAILS) $(CHERI_MAIN) -include ../etc/loc.mk - -# TODO Using bit lists for now in Lem generation; for machine words, -# monomorphisation is needed due to some variable length bitvectors, e.g. in -# CLoad as of commit b34c3fb, in the TLB translation, and in compressed -# capability functions - -cheri_no_tlb.lem: $(CHERI_NO_TLB_SAILS) - $(SAIL) -lem -o cheri_no_tlb -lem_lib Mips_extras -undefined_gen -memo_z3 $^ -cheri_no_tlb_types.lem: cheri_no_tlb.lem - -cheri.lem: $(CHERI_MONO_SAILS) $(CHERI_MAIN) - $(SAIL) -lem -o cheri -auto_mono -mono_rewrites -lem_mwords -lem_lib Mips_extras -undefined_gen -memo_z3 $^ -cheri_types.lem: cheri.lem - -cheri128_no_tlb.lem: $(CHERI128_NO_TLB_SAILS) - $(SAIL) -lem -o cheri128_no_tlb -lem_lib Mips_extras -undefined_gen -memo_z3 $^ -cheri128_no_tlb_types.lem: cheri128_no_tlb.lem - -cheri128.lem: $(CHERI128_SAILS) - $(SAIL) -lem -o cheri128 -lem_lib Mips_extras -undefined_gen -memo_z3 $^ -cheri128_types.lem: cheri128.lem - -C%.thy: c%.lem c%_types.lem $(MIPS_SAIL_DIR)/mips_extras.lem - lem -isa -outdir . -lib Sail=$(SAIL_DIR)/src/gen_lib -lib Sail=$(SAIL_DIR)/src/lem_interp $^ - sed -i 's/datatype ast/datatype (plugins only: size) ast/' C$*_types.thy - -%Script.sml: %.lem %_types.lem $(MIPS_SAIL_DIR)/mips_extras.lem - lem -hol -outdir . -lib $(SAIL_DIR)/lib/hol -i $(SAIL_DIR)/lib/hol/sail2_prompt_monad.lem -i $(SAIL_DIR)/lib/hol/sail2_prompt.lem -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^ - -%Theory.uo: %Script.sml - Holmake $@ - -cheri.v cheri_types.v: $(CHERI_SAILS) - $(SAIL) -coq -o cheri -coq_lib mips_extras -undefined_gen -memo_z3 -dcoq_undef_axioms $^ - -CHERI_COQ = cheri_types.v mips_extras.v cheri.v -COQ_LIBS = -R ../../bbv/theories bbv -R ../lib/coq Sail - -%.vo: %.v - coqc $(COQ_LIBS) $< -cheri.vo: cheri_types.vo mips_extras.vo - -clean: - rm -rf cheri cheri_trace cheri_coverage cheri128 cheri128_trace _sbuild inst_*.sail cheri.c sail_latex sail_latexcc coverage_report - rm -f cheriScript.sml cheri_typesScript.sml mips_extrasScript.sml - rm -f cheri.v cheri_types.v $(CHERI_COQ:%.v=%.vo) $(CHERI_COQ:%.v=%.glob) $(CHERI_COQ:%.v=.%.aux) - -Holmake cleanAll diff --git a/cheri/ROOT b/cheri/ROOT deleted file mode 100644 index 244413d5..00000000 --- a/cheri/ROOT +++ /dev/null @@ -1,4 +0,0 @@ -session "Sail-CHERI" = "Sail" + - options [document = false] - theories - Cheri_lemmas diff --git a/cheri/cheri_insts.sail b/cheri/cheri_insts.sail deleted file mode 100644 index f1038ed6..00000000 --- a/cheri/cheri_insts.sail +++ /dev/null @@ -1,1353 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* Old encodings */ -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b000) = Some(CGetPerm(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b001) = Some(CGetType(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b010) = Some(CGetBase(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b011) = Some(CGetLen(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b101) = Some(CGetTag(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b110) = Some(CGetSealed(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ 0b00000 @ 0b00000000 @ 0b100) = Some(CGetCause(rd)) - -function clause decode (0b010010 @ 0b00110 @ 0b000000000000000000000) = Some(CReturn()) - -function clause decode (0b010010 @ 0b01101 @ rd : regno @ cb : regno @ 0b00000000 @ 0b010) = Some(CGetOffset(rd, cb)) /* NB encoding does not follow pattern */ -function clause decode (0b010010 @ 0b00100 @ 0b00000 @ 0b00000 @ rt : regno @ 0b000 @ 0b100) = Some(CSetCause(rt)) -function clause decode (0b010010 @ 0b00100 @ cd : regno @ cb : regno @ rt : regno @ 0b000 @ 0b000) = Some(CAndPerm(cd, cb, rt)) -function clause decode (0b010010 @ 0b01100 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b000) = Some(CToPtr(rd, cb, ct)) - -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b000) = Some(CPtrCmp(rd, cb, ct, CEQ)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b001) = Some(CPtrCmp(rd, cb, ct, CNE)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b010) = Some(CPtrCmp(rd, cb, ct, CLT)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b011) = Some(CPtrCmp(rd, cb, ct, CLE)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b100) = Some(CPtrCmp(rd, cb, ct, CLTU)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b101) = Some(CPtrCmp(rd, cb, ct, CLEU)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b110) = Some(CPtrCmp(rd, cb, ct, CEXEQ)) -function clause decode (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b111) = Some(CPtrCmp(rd, cb, ct, CNEXEQ)) -function clause decode (0b010010 @ 0b01101 @ cd : regno @ cb : regno @ rt : regno @ 0b000 @ 0b000) = Some(CIncOffset(cd, cb, rt)) -function clause decode (0b010010 @ 0b01101 @ cd : regno @ cb : regno @ rt : regno @ 0b000 @ 0b001) = Some(CSetOffset(cd, cb, rt)) -function clause decode (0b010010 @ 0b00001 @ cd : regno @ cb : regno @ rt : regno @ 0b000000) = Some(CSetBounds(cd, cb, rt)) - -function clause decode (0b010010 @ 0b00100 @ cd : regno @ cb : regno @ 0b00000 @ 0b000@ 0b101) = Some(CClearTag(cd, cb)) -function clause decode (0b010010 @ 0b00100 @ cd : regno @ cb : regno @ rt : regno @ 0b000@ 0b111) = Some(CFromPtr(cd, cb, rt)) -function clause decode (0b010010 @ 0b01011 @ cs : regno @ 0b00000 @ rt : regno @ 0b000@ 0b000) = Some(CCheckPerm(cs, rt)) -function clause decode (0b010010 @ 0b01011 @ cs : regno @ cb : regno @ 0b00000 @ 0b000@ 0b001) = Some(CCheckType(cs, cb)) -function clause decode (0b010010 @ 0b00010 @ cd : regno @ cs : regno @ ct : regno @ 0b000@ 0b000) = Some(CSeal(cd, cs, ct)) -function clause decode (0b010010 @ 0b00011 @ cd : regno @ cs : regno @ ct : regno @ 0b000@ 0b000) = Some(CUnseal(cd, cs, ct)) -function clause decode (0b010010 @ 0b00111 @ cd : regno @ cb : regno @ 0b00000 @ 0b000000) = Some(CJALR(cd, cb, true)) /* CJALR */ -function clause decode (0b010010 @ 0b01000 @ 0b00000 @ cb : regno @ 0b00000 @ 0b000000) = Some(CJALR(0b00000, cb, false)) /* CJR */ - - -/* -New encodings as per CHERI ISA Appendix B.2. - -NB: Must be careful about order of matching because unused register -fields are re-used as additional function codes. -*/ - -/* One arg */ -function clause decode (0b010010 @ 0b00000 @ rd : regno @ 0b00001 @ 0b11111 @ 0b111111) = Some(CGetCause(rd)) -function clause decode (0b010010 @ 0b00000 @ rs : regno @ 0b00010 @ 0b11111 @ 0b111111) = Some(CSetCause(rs)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ 0b00000 @ 0b11111 @ 0b111111) = Some(CGetPCC(cd)) -function clause decode (0b010010 @ 0b00000 @ cb : regno @ 0b00011 @ 0b11111 @ 0b111111) = Some(CJALR(0b00000, cb, false)) /* CJR */ - -/* Two arg */ -function clause decode (0b010010 @ 0b00000 @ cs : regno @ rt : regno @ 0b01000 @ 0b111111) = Some(CCheckPerm(cs, rt)) -function clause decode (0b010010 @ 0b00000 @ cs : regno @ cb : regno @ 0b01001 @ 0b111111) = Some(CCheckType(cs, cb)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ 0b01011 @ 0b111111) = Some(CClearTag(cd, cb)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ 0b01010 @ 0b111111) = Some(CMOVX(cd, cs, 0b00000, false)) /* CMOVE */ -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ 0b01100 @ 0b111111) = Some(CJALR(cd, cb, true)) /* CJALR */ - -/* Capability Inspection */ -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000 @ 0b111111) = Some(CGetPerm(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00001 @ 0b111111) = Some(CGetType(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00010 @ 0b111111) = Some(CGetBase(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00011 @ 0b111111) = Some(CGetLen(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00100 @ 0b111111) = Some(CGetTag(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00101 @ 0b111111) = Some(CGetSealed(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00110 @ 0b111111) = Some(CGetOffset(rd, cb)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ rs : regno @ 0b00111 @ 0b111111) = Some(CGetPCCSetOffset(cd, rs)) - -function clause decode (0b010010 @ 0b00000 @ cd : regno @ sel : regno @ 0b01101 @ 0b111111) = Some(CReadHwr(cd, sel)) -function clause decode (0b010010 @ 0b00000 @ cb : regno @ sel : regno @ 0b01110 @ 0b111111) = Some(CWriteHwr(cb, sel)) - -function clause decode (0b010010 @ 0b00000 @ cb : regno @ sel : regno @ 0b01111 @ 0b111111) = Some(CGetAddr(cb, sel)) - -/* Three operand */ - -/* Capability Modification */ -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ ct : regno @ 0b001011) = Some(CSeal(cd, cs, ct)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ ct : regno @ 0b001100) = Some(CUnseal(cd, cs, ct)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001101) = Some(CAndPerm(cd, cs, rt)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001111) = Some(CSetOffset(cd, cs, rt)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001000) = Some(CSetBounds(cd, cs, rt)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001001) = Some(CSetBoundsExact(cd, cs, rt)) - - -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ rt : regno @ 0b010001) = Some(CIncOffset(cd, cb, rt)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ ct : regno @ 0b011101) = Some(CBuildCap(cd, cb, ct)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ ct : regno @ 0b011110) = Some(CCopyType(cd, cb, ct)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ ct : regno @ 0b011111) = Some(CCSeal(cd, cs, ct)) - -/* Pointer Arithmetic */ -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ ct : regno @ 0b010010) = Some(CToPtr(rd, cb, ct)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ rs : regno @ 0b010011) = Some(CFromPtr(cd, cb, rs)) -function clause decode (0b010010 @ 0b00000 @ rt : regno @ cb : regno @ cs : regno @ 0b001010) = Some(CSub(rt, cb, cs)) -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rs : regno @ 0b011011) = Some(CMOVX(cd, cs, rs, false)) /* CMOVZ */ -function clause decode (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rs : regno @ 0b011100) = Some(CMOVX(cd, cs, rs, true)) /* CMOVN */ - -/* Pointer Comparison */ -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010100) = Some(CPtrCmp(rd, cb, cs, CEQ)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010101) = Some(CPtrCmp(rd, cb, cs, CNE)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010110) = Some(CPtrCmp(rd, cb, cs, CLT)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010111) = Some(CPtrCmp(rd, cb, cs, CLE)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b011000) = Some(CPtrCmp(rd, cb, cs, CLTU)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b011001) = Some(CPtrCmp(rd, cb, cs, CLEU)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b011010) = Some(CPtrCmp(rd, cb, cs, CEXEQ)) -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b100001) = Some(CPtrCmp(rd, cb, cs, CNEXEQ)) - -function clause decode (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ ct : regno @ 0b100000) = Some(CTestSubset(rd, cb, ct)) - -function clause decode (0b010010 @ 0b01001 @ cd : regno @ imm : bits(16)) = Some(CBX(cd, imm, true)) /* CBTU */ -function clause decode (0b010010 @ 0b01010 @ cd : regno @ imm : bits(16)) = Some(CBX(cd, imm, false)) /* CBTS */ -function clause decode (0b010010 @ 0b10001 @ cd : regno @ imm : bits(16)) = Some(CBZ(cd, imm, false)) /* CBEZ */ -function clause decode (0b010010 @ 0b10010 @ cd : regno @ imm : bits(16)) = Some(CBZ(cd, imm, true)) /* CBNZ */ - -function clause decode (0b010010 @ 0b00101 @ 0b00000 @ 0b00000 @ 0b11111111111) = Some(CReturn()) -function clause decode (0b010010 @ 0b00101 @ cs : regno @ cb : regno @ selector : bits(11)) = Some(CCall(cs, cb, selector)) - -function clause decode (0b010010 @ 0b01111 @ 0b00000 @ imm : bits(16)) = Some(ClearRegs(GPLo, imm)) -function clause decode (0b010010 @ 0b01111 @ 0b00001 @ imm : bits(16)) = Some(ClearRegs(GPHi, imm)) -function clause decode (0b010010 @ 0b01111 @ 0b00010 @ imm : bits(16)) = Some(ClearRegs(CLo, imm)) -function clause decode (0b010010 @ 0b01111 @ 0b00011 @ imm : bits(16)) = Some(ClearRegs(CHi, imm)) - -function clause decode (0b010010 @ 0b10011 @ cd : regno @ cb : regno @ imm : bits(11)) = Some(CIncOffsetImmediate(cd, cb, imm)) -function clause decode (0b010010 @ 0b10100 @ cd : regno @ cb : regno @ imm : bits(11)) = Some(CSetBoundsImmediate(cd, cb, imm)) - -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b00) = Some(CLoad(rd, cb, rt, offset, false, B, false)) /* CLBU */ -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b1 @ 0b00) = Some(CLoad(rd, cb, rt, offset, true, B, false)) /* CLB */ -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b01) = Some(CLoad(rd, cb, rt, offset, false, H, false)) /* CLHU */ -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b1 @ 0b01) = Some(CLoad(rd, cb, rt, offset, true, H, false)) /* CLH */ -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b10) = Some(CLoad(rd, cb, rt, offset, false, W, false)) /* CLWU */ -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b1 @ 0b10) = Some(CLoad(rd, cb, rt, offset, true, W, false)) /* CLW */ -function clause decode (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b11) = Some(CLoad(rd, cb, rt, offset, false, D, false)) /* CLD */ - -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b00) = Some(CLoad(rd, cb, 0b00000, 0b00000000, false, B, true)) /* CLLBU */ -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b1 @ 0b00) = Some(CLoad(rd, cb, 0b00000, 0b00000000, true, B, true)) /* CLLB */ -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b01) = Some(CLoad(rd, cb, 0b00000, 0b00000000, false, H, true)) /* CLLHU */ -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b1 @ 0b01) = Some(CLoad(rd, cb, 0b00000, 0b00000000, true, H, true)) /* CLLH */ -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b10) = Some(CLoad(rd, cb, 0b00000, 0b00000000, false, W, true)) /* CLLWU */ -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b1 @ 0b10) = Some(CLoad(rd, cb, 0b00000, 0b00000000, true, W, true)) /* CLLW */ -function clause decode (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b11) = Some(CLoad(rd, cb, 0b00000, 0b00000000, false, D, true)) /* CLLD */ - -function clause decode (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b00) = Some(CStore(rs, cb, rt, 0b00000, offset, B, false)) /* CSB */ -function clause decode (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b01) = Some(CStore(rs, cb, rt, 0b00000, offset, H, false)) /* CSH */ -function clause decode (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b10) = Some(CStore(rs, cb, rt, 0b00000, offset, W, false)) /* CSW */ -function clause decode (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : bits(8) @ 0b0 @ 0b11) = Some(CStore(rs, cb, rt, 0b00000, offset, D, false)) /* CSD */ - -function clause decode (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b00) = Some(CStore(rs, cb, 0b00000, rd, 0b00000000, B, true)) /* CSCB */ -function clause decode (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b01) = Some(CStore(rs, cb, 0b00000, rd, 0b00000000, H, true)) /* CSCH */ -function clause decode (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b10) = Some(CStore(rs, cb, 0b00000, rd, 0b00000000, W, true)) /* CSCW */ -function clause decode (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b11) = Some(CStore(rs, cb, 0b00000, rd, 0b00000000, D, true)) /* CSCD */ - -function clause decode (0b111110 @ cs : regno @ cb : regno@ rt : regno @ offset : bits(11)) = Some(CSC(cs, cb, rt, 0b00000, offset, false)) -function clause decode (0b010010 @ 0b10000 @ cs : regno @ cb : regno@ rd : regno @ 0b00 @ 0b0111) = Some(CSC(cs, cb, 0b00000, rd, 0b00000000000, true)) /* CSCC */ - -function clause decode (0b110110 @ cd : regno @ cb : regno @ rt : regno @ offset : bits(11)) = Some(CLC(cd, cb, rt, sign_extend(offset), false)) /* CLC */ -function clause decode (0b010010 @ 0b10000 @ cd : regno @ cb : regno@ 0b0000000 @ 0b1111) = Some(CLC(cd, cb, 0b00000, 0x0000, true)) /* CLLC */ -function clause decode (0b011101 @ cd : regno @ cb : regno @ offset : bits(16)) = Some(CLC(cd, cb, 0b00000, offset, false)) /* CLCBI */ - -function clause decode (0b010010 @ 0b00100 @ rt : regno @ 0x0006) = Some(C2Dump(rt)) - -/* Operations that extract parts of a capability into GPR */ - -union clause ast = CGetPerm : (regno, regno) -union clause ast = CGetType : (regno, regno) -union clause ast = CGetBase : (regno, regno) -union clause ast = CGetLen : (regno, regno) -union clause ast = CGetTag : (regno, regno) -union clause ast = CGetSealed : (regno, regno) -union clause ast = CGetOffset : (regno, regno) -union clause ast = CGetAddr : (regno, regno) - -function clause execute (CGetPerm(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = zero_extend(getCapPerms(capVal)); -} - -function clause execute (CGetType(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = if (capVal.sealed) - then zero_extend(capVal.otype) - else (bitone ^^ 64) -} - -function clause execute (CGetBase(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = to_bits(64, getCapBase(capVal)); -} - -function clause execute (CGetOffset(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = to_bits(64, getCapOffset(capVal)); -} - -function clause execute (CGetLen(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - let len65 = getCapLength(capVal) in - wGPR(rd) = to_bits(64, if len65 > MAX_U64 then MAX_U64 else len65); -} - -function clause execute (CGetTag(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = zero_extend(capVal.tag); -} - -function clause execute (CGetSealed(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = zero_extend(capVal.sealed); -} - -function clause execute (CGetAddr(rd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = readCapReg(cb) in - wGPR(rd) = to_bits(64, getCapCursor(capVal)); -} - -union clause ast = CGetPCC : regno -function clause execute (CGetPCC(cd)) = -{ - checkCP2usable(); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else - let pcc = (capRegToCapStruct(PCC)) in - let (success, pcc2) = setCapOffset(pcc, PC) in - {assert (success, ""); /* guaranteed to be in-bounds */ - writeCapReg(cd, pcc2)}; -} - - -union clause ast = CGetPCCSetOffset : (regno, regno) -function clause execute (CGetPCCSetOffset(cd, rs)) = -{ - checkCP2usable(); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else - let pcc = (capRegToCapStruct(PCC)) in - let rs_val = rGPR(rs) in - let (success, newPCC) = setCapOffset(pcc, rs_val) in - if (success) then - writeCapReg(cd, newPCC) - else - writeCapReg(cd, int_to_cap(rs_val)); -} -/* Get and Set CP2 cause register */ - -union clause ast = CGetCause : regno -function clause execute (CGetCause(rd)) = -{ - checkCP2usable(); - if not (pcc_access_system_regs ()) then - raise_c2_exception_noreg(CapEx_AccessSystemRegsViolation) - else - wGPR(rd) = zero_extend(CapCause.bits()) -} - -union clause ast = CSetCause : regno -function clause execute (CSetCause(rt)) = -{ - checkCP2usable(); - if not (pcc_access_system_regs ()) then - raise_c2_exception_noreg(CapEx_AccessSystemRegsViolation) - else - { - let rt_val = rGPR(rt); - CapCause->ExcCode() = rt_val[15..8]; - CapCause->RegNum() = rt_val[7..0]; - } -} - -union clause ast = CReadHwr : (regno, regno) -function clause execute (CReadHwr(cd, sel)) = -{ - checkCP2usable(); - let (needSup, needAccessSys) : (bool, bool) = match unsigned(sel) { - 0 => (false, false), /* DDC -- no access control */ - 1 => (false, false), /* CTLSU -- no access control */ - 8 => (false, true), /* CTLSP -- privileged TLS */ - 22 => (true, false), /* KR1C */ - 23 => (true, false), /* KR2C */ - 29 => (true, true), /* KCC */ - 30 => (true, true), /* KDC */ - 31 => (true, true), /* EPCC */ - _ => SignalException(ResI) - }; - if register_inaccessible(cd) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if needAccessSys & not(pcc_access_system_regs()) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, sel) - else if needSup & not(grantsAccess(getAccessLevel(), Supervisor)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, sel) - else { - capVal : CapStruct = match unsigned(sel) { - 0 => capRegToCapStruct(DDC), - 1 => capRegToCapStruct(CTLSU), - 8 => capRegToCapStruct(CTLSP), - 22 => capRegToCapStruct(KR1C), - 23 => capRegToCapStruct(KR2C), - 29 => capRegToCapStruct(KCC), - 30 => capRegToCapStruct(KDC), - 31 => capRegToCapStruct(EPCC), - _ => {assert(false, "should be unreachable code"); undefined} - }; - writeCapReg(cd, capVal); - }; -} - -union clause ast = CWriteHwr : (regno, regno) -function clause execute (CWriteHwr(cb, sel)) = -{ - checkCP2usable(); - let (needSup, needAccessSys) : (bool, bool) = match unsigned(sel) { - 0 => (false, false), /* DDC -- no access control */ - 1 => (false, false), /* CTLSU -- no access control */ - 8 => (false, true), /* CTLSP -- privileged TLS */ - 22 => (true, false), /* KR1C */ - 23 => (true, false), /* KR2C */ - 29 => (true, true), /* KCC */ - 30 => (true, true), /* KDC */ - 31 => (true, true), /* EPCC */ - _ => SignalException(ResI) - }; - if register_inaccessible(cb) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if needAccessSys & not(pcc_access_system_regs()) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, sel) - else if needSup & not(grantsAccess(getAccessLevel(), Supervisor)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, sel) - else { - capVal = readCapReg(cb); - match unsigned(sel) { - 0 => DDC = capStructToCapReg(capVal), - 1 => CTLSU = capStructToCapReg(capVal), - 8 => CTLSP = capStructToCapReg(capVal), - 22 => KR1C = capStructToCapReg(capVal), - 23 => KR2C = capStructToCapReg(capVal), - 29 => KCC = capStructToCapReg(capVal), - 30 => KDC = capStructToCapReg(capVal), - 31 => EPCC = capStructToCapReg(capVal), - _ => assert(false, "should be unreachable code") - }; - }; -} - -union clause ast = CAndPerm : (regno, regno, regno) -function clause execute(CAndPerm(cd, cb, rt)) = -{ - checkCP2usable(); - let cb_val = readCapReg(cb); - let rt_val = rGPR(rt); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else - let perms = getCapPerms(cb_val) in - let newCap = setCapPerms(cb_val, (perms & rt_val[30..0])) in - writeCapReg(cd, newCap); -} - - - -union clause ast = CToPtr : (regno, regno, regno) -function clause execute(CToPtr(rd, cb, ct)) = -{ - checkCP2usable(); - let ct_val = readCapRegDDC(ct); - let cb_val = readCapReg(cb); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else if not (ct_val.tag) then - raise_c2_exception(CapEx_TagViolation, ct) - else if (cb_val.tag) & (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else - { - let cbBase = getCapBase(cb_val) in - let cbTop = getCapTop(cb_val) in - let ctBase = getCapBase(ct_val) in - let ctTop = getCapTop(ct_val) in - wGPR(rd) = if (not (cb_val.tag)) | - (cbBase < ctBase) | - (cbTop > ctTop) then - zeros() - else - to_bits(64, getCapCursor(cb_val) - ctBase) - } -} - - - -union clause ast = CSub : (regno, regno, regno) -function clause execute(CSub(rd, cb, ct)) = -{ - checkCP2usable(); - let ct_val = readCapReg(ct); - let cb_val = readCapReg(cb); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else - { - wGPR(rd) = to_bits(64, getCapCursor(cb_val) - getCapCursor(ct_val)) - } -} - -union clause ast = CPtrCmp : (regno, regno, regno, CPtrCmpOp) -function clause execute(CPtrCmp(rd, cb, ct, op)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else - { - let cb_val = readCapReg(cb); - let ct_val = readCapReg(ct); - equal = false; - ltu = false; - lts = false; - if (cb_val.tag != ct_val.tag) then - { - if not (cb_val.tag) then - { - ltu = true; - lts = true; - } - } - else - { - cursor1 = getCapCursor(cb_val); - cursor2 = getCapCursor(ct_val); - equal = (cursor1 == cursor2); - ltu = (cursor1 < cursor2); - lts = to_bits(64, cursor1) <_s to_bits(64, cursor2); - }; - let cmp : bool = match op { - CEQ => equal, - CNE => not (equal), - CLT => lts, - CLE => lts | equal, - CLTU => ltu, - CLEU => ltu | equal, - CEXEQ => cb_val == ct_val, - CNEXEQ => cb_val != ct_val - }; - wGPR(rd) = zero_extend (cmp) - } -} - -union clause ast = CIncOffset : (regno, regno, regno) -function clause execute (CIncOffset(cd, cb, rt)) = -{ - checkCP2usable(); - cb_val = readCapReg(cb); - rt_val = rGPR(rt); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if ((cb_val.tag) & (cb_val.sealed) & (rt_val != 0x0000000000000000)) then - raise_c2_exception(CapEx_SealViolation, cb) - else - let (success, newCap) = incCapOffset(cb_val, rt_val) in - if (success) then - writeCapReg(cd, newCap) - else - writeCapReg(cd, int_to_cap(to_bits(64, getCapBase(cb_val)) + rt_val)) -} - -union clause ast = CIncOffsetImmediate : (regno, regno, bits(11)) -function clause execute (CIncOffsetImmediate(cd, cb, imm)) = -{ - checkCP2usable(); - let cb_val = readCapReg(cb); - let imm64 : bits(64) = sign_extend(imm) in - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if ((cb_val.tag) & (cb_val.sealed)) then - raise_c2_exception(CapEx_SealViolation, cb) - else - let (success, newCap) = incCapOffset(cb_val, imm64) in - if (success) then - writeCapReg(cd, newCap) - else - writeCapReg(cd, int_to_cap(to_bits(64, getCapBase(cb_val)) + imm64)) -} - -union clause ast = CSetOffset : (regno, regno, regno) -function clause execute (CSetOffset(cd, cb, rt)) = -{ - checkCP2usable(); - let cb_val = readCapReg(cb); - let rt_val = rGPR(rt); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if ((cb_val.tag) & (cb_val.sealed)) then - raise_c2_exception(CapEx_SealViolation, cb) - else - let (success, newCap) = setCapOffset(cb_val, rt_val) in - if (success) then - writeCapReg(cd, newCap) - else - writeCapReg(cd, int_to_cap(to_bits(64, getCapBase(cb_val)) + rt_val)) -} - -union clause ast = CSetBounds : (regno, regno, regno) -function clause execute (CSetBounds(cd, cb, rt)) = -{ - checkCP2usable(); - let cb_val = readCapReg(cb); - let rt_val = unsigned(rGPR(rt)); - cursor = getCapCursor(cb_val); - base = getCapBase(cb_val); - top = getCapTop(cb_val); - newTop = cursor + rt_val; - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if (cursor < base) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (newTop > top) then - raise_c2_exception(CapEx_LengthViolation, cb) - else - let (_, newCap) = setCapBounds(cb_val, to_bits(64, cursor), to_bits(65, newTop)) in - writeCapReg(cd, newCap) /* ignore exact */ -} - -union clause ast = CSetBoundsImmediate : (regno, regno, bits(11)) -function clause execute (CSetBoundsImmediate(cd, cb, imm)) = -{ - checkCP2usable(); - cb_val = readCapReg(cb); - immU = unsigned(imm); - cursor = getCapCursor(cb_val); - base = getCapBase(cb_val); - top = getCapTop(cb_val); - newTop = cursor + immU; - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if (cursor < base) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (newTop > top) then - raise_c2_exception(CapEx_LengthViolation, cb) - else - let (_, newCap) = setCapBounds(cb_val, to_bits(64, cursor), to_bits(65, newTop)) in - writeCapReg(cd, newCap) /* ignore exact */ -} - -union clause ast = CSetBoundsExact : (regno, regno, regno) -function clause execute (CSetBoundsExact(cd, cb, rt)) = -{ - checkCP2usable(); - cb_val = readCapReg(cb); - rt_val = unsigned(rGPR(rt)); - cursor = getCapCursor(cb_val); - base = getCapBase(cb_val); - top = getCapTop(cb_val); - newTop = cursor + rt_val; - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if (cursor < base) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (newTop > top) then - raise_c2_exception(CapEx_LengthViolation, cb) - else - let (exact, newCap) = setCapBounds(cb_val, to_bits(64, cursor), to_bits(65, newTop)) in - if not (exact) then - raise_c2_exception(CapEx_InexactBounds, cb) - else - writeCapReg(cd, newCap) -} - -union clause ast = CClearTag : (regno, regno) -function clause execute (CClearTag(cd, cb)) = -{ - checkCP2usable(); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else - { - cb_val = readCapReg(cb); - writeCapReg(cd, {cb_val with tag=false}); - } -} - -union clause ast = CMOVX : (regno,regno,regno,bool) -function clause execute (CMOVX(cd, cb, rt, ismovn)) = -{ - checkCP2usable(); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if ((rGPR(rt) == zeros()) ^ ismovn) then - writeCapReg(cd) = readCapReg(cb); -} - -union clause ast = ClearRegs : (ClearRegSet, bits(16)) -function clause execute (ClearRegs(regset, m)) = -{ - if ((regset == CLo) | (regset == CHi)) then - checkCP2usable(); - if (regset == CHi) then - foreach (i from 0 to 15) - let r = to_bits(5, i+16) in - if (m[i] & register_inaccessible(r)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, r); - foreach (i from 0 to 15) - if (m[i]) then - match regset { - GPLo => wGPR(to_bits(5, i)) = zeros(), - GPHi => wGPR(to_bits(5, i+16)) = zeros(), - CLo => if i == 0 then - DDC = capStructToCapReg(null_cap) - else - writeCapReg(to_bits(5, i)) = null_cap, - CHi => writeCapReg(to_bits(5, i+16)) = null_cap - } -} - -union clause ast = CFromPtr : (regno, regno, regno) -function clause execute (CFromPtr(cd, cb, rt)) = -{ - checkCP2usable(); - cb_val = readCapRegDDC(cb); - rt_val = rGPR(rt); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (rt_val == 0x0000000000000000) then - writeCapReg(cd, null_cap) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else - let (success, newCap) = setCapOffset(cb_val, rt_val) in - if (success) then - writeCapReg(cd, newCap) - else - writeCapReg(cd, int_to_cap(to_bits(64, getCapBase(cb_val)) + rt_val)) -} - -union clause ast = CBuildCap : (regno, regno, regno) -function clause execute (CBuildCap(cd, cb, ct)) = -{ - checkCP2usable(); - cb_val = readCapRegDDC(cb); - ct_val = readCapReg(ct); - cb_base = getCapBase(cb_val); - ct_base = getCapBase(ct_val); - cb_top = getCapTop(cb_val); - ct_top = getCapTop(ct_val); - cb_perms = getCapPerms(cb_val); - ct_perms = getCapPerms(ct_val); - ct_offset = getCapOffset(ct_val); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if ct_base < cb_base then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ct_top > cb_top then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ct_base > ct_top then /* check for length < 0 - possible because ct might be untagged */ - raise_c2_exception(CapEx_LengthViolation, ct) - else if (ct_perms & cb_perms) != ct_perms then - raise_c2_exception(CapEx_UserDefViolation, cb) - else - let (exact, cd1) = setCapBounds(cb_val, to_bits(64, ct_base), to_bits(65, ct_top)) in - let (representable, cd2) = setCapOffset(cd1, to_bits(64, ct_offset)) in - let cd3 = setCapPerms(cd2, ct_perms) in - { - assert(exact, ""); /* base and top came from ct originally so will be exact */ - assert(representable, ""); /* similarly offset should be representable XXX except for fastRepCheck */ - writeCapReg(cd, cd3); - } -} - -union clause ast = CCopyType : (regno, regno, regno) -function clause execute (CCopyType(cd, cb, ct)) = -{ - checkCP2usable(); - cb_val = readCapReg(cb); - ct_val = readCapReg(ct); - cb_base = getCapBase(cb_val); - cb_top = getCapTop(cb_val); - ct_otype = unsigned(ct_val.otype); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if (ct_val.sealed) then { - if ct_otype < cb_base then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ct_otype >= cb_top then - raise_c2_exception(CapEx_LengthViolation, cb) - else - let (success, cap) = setCapOffset(cb_val, to_bits(64, ct_otype - cb_base)) in { - assert(success, ""); /* offset is in bounds so must succeed */ - writeCapReg(cd, cap); - } - } else - writeCapReg(cd, int_to_cap(bitone ^^ 64)) -} - -union clause ast = CCheckPerm : (regno, regno) -function clause execute (CCheckPerm(cs, rt)) = -{ - checkCP2usable(); - cs_val = readCapReg(cs); - cs_perms : bits(64) = zero_extend(getCapPerms(cs_val)); - rt_perms = rGPR(rt); - if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if ((cs_perms & rt_perms) != rt_perms) then - raise_c2_exception(CapEx_UserDefViolation, cs) -} - -union clause ast = CCheckType : (regno, regno) -function clause execute (CCheckType(cs, cb)) = -{ - checkCP2usable(); - cs_val = readCapReg(cs); - cb_val = readCapReg(cb); - if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if not (cs_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cs) - else if not (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if ((cs_val.otype) != (cb_val.otype)) then - raise_c2_exception(CapEx_TypeViolation, cs) -} - -union clause ast = CTestSubset : (regno, regno, regno) -function clause execute (CTestSubset(rd, cb, ct)) = -{ - checkCP2usable(); - cb_val = readCapRegDDC(cb); - ct_val = readCapReg(ct); - ct_top = getCapTop(ct_val); - ct_base = getCapBase(ct_val); - ct_perms = getCapPerms(ct_val); - cb_top = getCapTop(cb_val); - cb_base = getCapBase(cb_val); - cb_perms = getCapPerms(cb_val); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else { - result : bits(1) = if (cb_val.tag != ct_val.tag) then - 0b0 - else if (ct_base < cb_base) then - 0b0 - else if (ct_top > cb_top) then - 0b0 - else if ((ct_perms & cb_perms) != ct_perms) then - 0b0 - else - 0b1; - wGPR(rd) = zero_extend(result); - } -} - -union clause ast = CSeal : (regno, regno, regno) -function clause execute (CSeal(cd, cs, ct)) = -{ - checkCP2usable(); - cs_val = readCapReg(cs); - ct_val = readCapReg(ct); - ct_cursor = getCapCursor(ct_val); - ct_top = getCapTop(ct_val); - ct_base = getCapBase(ct_val); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if not (ct_val.tag) then - raise_c2_exception(CapEx_TagViolation, ct) - else if (cs_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cs) - else if (ct_val.sealed) then - raise_c2_exception(CapEx_SealViolation, ct) - else if not (ct_val.permit_seal) then - raise_c2_exception(CapEx_PermitSealViolation, ct) - else if (ct_cursor < ct_base) then - raise_c2_exception(CapEx_LengthViolation, ct) - else if (ct_cursor >= ct_top) then - raise_c2_exception(CapEx_LengthViolation, ct) - else if (ct_cursor > max_otype) then - raise_c2_exception(CapEx_LengthViolation, ct) - else - let (success, newCap) = sealCap(cs_val, to_bits(24, ct_cursor)) in - if not (success) then - raise_c2_exception(CapEx_InexactBounds, cs) - else - writeCapReg(cd, newCap) -} - -union clause ast = CCSeal : (regno, regno, regno) -function clause execute (CCSeal(cd, cs, ct)) = -{ - checkCP2usable(); - cs_val = readCapReg(cs); - ct_val = readCapReg(ct); - ct_cursor = getCapCursor(ct_val); - ct_top = getCapTop(ct_val); - ct_base = getCapBase(ct_val); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if (not (ct_val.tag)) | (getCapCursor(ct_val) == unsigned(bitone ^^ 64)) then - writeCapReg(cd, cs_val) - else if (cs_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cs) - else if (ct_val.sealed) then - raise_c2_exception(CapEx_SealViolation, ct) - else if not (ct_val.permit_seal) then - raise_c2_exception(CapEx_PermitSealViolation, ct) - else if (ct_cursor < ct_base) then - raise_c2_exception(CapEx_LengthViolation, ct) - else if (ct_cursor >= ct_top) then - raise_c2_exception(CapEx_LengthViolation, ct) - else if (ct_cursor > max_otype) then - raise_c2_exception(CapEx_LengthViolation, ct) - else - let (success, newCap) = sealCap(cs_val, to_bits(24, ct_cursor)) in - if not (success) then - raise_c2_exception(CapEx_InexactBounds, cs) - else - writeCapReg(cd, newCap) -} - -union clause ast = CUnseal : (regno, regno, regno) -function clause execute (CUnseal(cd, cs, ct)) = -{ - checkCP2usable(); - cs_val = readCapReg(cs); - ct_val = readCapReg(ct); - ct_cursor = getCapCursor(ct_val); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(ct)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, ct) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if not (ct_val.tag) then - raise_c2_exception(CapEx_TagViolation, ct) - else if not (cs_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cs) - else if (ct_val.sealed) then - raise_c2_exception(CapEx_SealViolation, ct) - else if (ct_cursor != unsigned(cs_val.otype)) then - raise_c2_exception(CapEx_TypeViolation, ct) - else if not (ct_val.permit_unseal) then - raise_c2_exception(CapEx_PermitUnsealViolation, ct) - else if (ct_cursor < getCapBase(ct_val)) then - raise_c2_exception(CapEx_LengthViolation, ct) - else if (ct_cursor >= getCapTop(ct_val)) then - raise_c2_exception(CapEx_LengthViolation, ct) - else - writeCapReg(cd, {cs_val with - sealed=false, - otype=zeros(), - global=(cs_val.global & ct_val.global) - }) -} - -union clause ast = CCall : (regno, regno, bits(11)) -function clause execute (CCall(cs, cb, 0b00000000000)) = /* selector=0 */ -{ - /* Partial implementation of CCall with checks in hardware, but raising a trap to perform trusted stack manipulation */ - checkCP2usable(); - cs_val = readCapReg(cs); - cb_val = readCapReg(cb); - cs_cursor = getCapCursor(cs_val); - if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if not (cs_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cs) - else if not (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if ((cs_val.otype) != (cb_val.otype)) then - raise_c2_exception(CapEx_TypeViolation, cs) - else if not (cs_val.permit_execute) then - raise_c2_exception(CapEx_PermitExecuteViolation, cs) - else if (cb_val.permit_execute) then - raise_c2_exception(CapEx_PermitExecuteViolation, cb) - else if (cs_cursor < getCapBase(cs_val)) then - raise_c2_exception(CapEx_LengthViolation, cs) - else if (cs_cursor >= getCapTop(cs_val)) then - raise_c2_exception(CapEx_LengthViolation, cs) - else - raise_c2_exception(CapEx_CallTrap, cs); -} - -function clause execute (CCall(cs, cb, 0b00000000001)) = /* selector=1 */ -{ - /* Jump-like implementation of CCall that unseals arguments */ - checkCP2usable(); - cs_val = readCapReg(cs); - cb_val = readCapReg(cb); - cs_cursor = getCapCursor(cs_val); - if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cs_val.tag) then - raise_c2_exception(CapEx_TagViolation, cs) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if not (cs_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cs) - else if not (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if ((cs_val.otype) != (cb_val.otype)) then - raise_c2_exception(CapEx_TypeViolation, cs) - else if not (cs_val.permit_ccall) then - raise_c2_exception(CapEx_PermitCCallViolation, cs) - else if not (cb_val.permit_ccall) then - raise_c2_exception(CapEx_PermitCCallViolation, cb) - else if not (cs_val.permit_execute) then - raise_c2_exception(CapEx_PermitExecuteViolation, cs) - else if (cb_val.permit_execute) then - raise_c2_exception(CapEx_PermitExecuteViolation, cb) - else if (cs_cursor < getCapBase(cs_val)) then - raise_c2_exception(CapEx_LengthViolation, cs) - else if (cs_cursor >= getCapTop(cs_val)) then - raise_c2_exception(CapEx_LengthViolation, cs) - else - { - execute_branch_pcc({cs_val with - sealed=false, - otype=zeros() - }); - inCCallDelay = 0b1; - C26 = capStructToCapReg({cb_val with - sealed=false, - otype=zeros() - }); - } -} - -union clause ast = CReturn : unit -function clause execute (CReturn()) = -{ - checkCP2usable(); - raise_c2_exception_noreg(CapEx_ReturnTrap) -} - -union clause ast = CBX : (regno, bits(16), bool) -function clause execute (CBX(cb, imm, notset)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (((readCapReg(cb)).tag) ^ notset) then - { - let offset : bits(64) = (sign_extend(imm @ 0b00) + 4) in - execute_branch(PC + offset); - } -} - -union clause ast = CBZ : (regno, bits(16), bool) -function clause execute (CBZ(cb, imm, notzero)) = -{ - checkCP2usable(); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if (((readCapReg(cb)) == null_cap) ^ notzero) then - { - let offset : bits(64) = (sign_extend(imm @ 0b00) + 4) in - execute_branch(PC + offset); - } -} - -union clause ast = CJALR : (regno, regno, bool) -function clause execute(CJALR(cd, cb, link)) = -{ - checkCP2usable(); - cb_val = readCapReg(cb); - cb_ptr = getCapCursor(cb_val); - cb_top = getCapTop(cb_val); - cb_base= getCapBase(cb_val); - if (link & register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if not (cb_val.permit_execute) then - raise_c2_exception(CapEx_PermitExecuteViolation, cb) - else if (cb_ptr < cb_base) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ((cb_ptr + 4) > cb_top) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ((cb_ptr % 4) != 0) then - SignalException(AdEL) - else - { - if (link) then - let pcc = capRegToCapStruct(PCC) in - let (success, linkCap) = setCapOffset(pcc, PC+8) in - if (success) then - writeCapReg(cd, linkCap) - else - assert(false, ""); - execute_branch_pcc(cb_val); - } -} - -union clause ast = CLoad : (regno, regno, regno, bits(8), bool, WordType, bool) -function clause execute (CLoad(rd, cb, rt, offset, signext, width, linked)) = -{ - checkCP2usable(); - cb_val = readCapRegDDC(cb); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if not (cb_val.permit_load) then - raise_c2_exception(CapEx_PermitLoadViolation, cb) - else - { - let 'size = wordWidthBytes(width); - let cursor = getCapCursor(cb_val); - let vAddr = (cursor + unsigned(rGPR(rt)) + size*signed(offset)) % pow2(64); - let vAddr64 = to_bits(64, vAddr); - if ((vAddr + size) > getCapTop(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (vAddr < getCapBase(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if not (isAddressAligned(vAddr64, width)) then - SignalExceptionBadAddr(AdEL, vAddr64) - else - { - pAddr = (TLBTranslate(vAddr64, LoadData)); - memResult : bits(64) = if (linked) then - { - CP0LLBit = 0b1; - CP0LLAddr = pAddr; - extendLoad(MEMr_reserve_wrapper(pAddr, size), signext) - } - else - extendLoad(MEMr_wrapper(pAddr, size), signext); - wGPR(rd) = memResult; - } - } -} - -union clause ast = CStore : (regno, regno, regno, regno, bits(8), WordType, bool) - -function clause execute (CStore(rs, cb, rt, rd, offset, width, conditional)) = -{ - checkCP2usable(); - cb_val = readCapRegDDC(cb); - if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if not (cb_val.permit_store) then - raise_c2_exception(CapEx_PermitStoreViolation, cb) - else - { - size = wordWidthBytes(width); - cursor = getCapCursor(cb_val); - vAddr = (cursor + unsigned(rGPR(rt)) + size * signed(offset)) % pow2(64); - vAddr64= to_bits(64, vAddr); - if ((vAddr + size) > getCapTop(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (vAddr < getCapBase(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if not (isAddressAligned(vAddr64, width)) then - SignalExceptionBadAddr(AdES, vAddr64) - else - { - pAddr = (TLBTranslate(vAddr64, StoreData)); - rs_val = rGPR(rs); - if (conditional) then - { - success : bool = if (CP0LLBit[0]) then - match width - { - B => MEMw_conditional_wrapper(pAddr, 1, rs_val[7..0]), - H => MEMw_conditional_wrapper(pAddr, 2, rs_val[15..0]), - W => MEMw_conditional_wrapper(pAddr, 4, rs_val[31..0]), - D => MEMw_conditional_wrapper(pAddr, 8, rs_val) - } - else - false; - wGPR(rd) = zero_extend(success); - } - else - match width - { - B => MEMw_wrapper(pAddr, 1) = rs_val[7..0], - H => MEMw_wrapper(pAddr, 2) = rs_val[15..0], - W => MEMw_wrapper(pAddr, 4) = rs_val[31..0], - D => MEMw_wrapper(pAddr, 8) = rs_val - } - } - } -} - -union clause ast = CSC : (regno, regno, regno, regno, bits(11), bool) -function clause execute (CSC(cs, cb, rt, rd, offset, conditional)) = -{ - checkCP2usable(); - cs_val = readCapReg(cs); - cb_val = readCapRegDDC(cb); - if (register_inaccessible(cs)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cs) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if not (cb_val.permit_store) then - raise_c2_exception(CapEx_PermitStoreViolation, cb) - else if not (cb_val.permit_store_cap) then - raise_c2_exception(CapEx_PermitStoreCapViolation, cb) - else if not (cb_val.permit_store_local_cap) & (cs_val.tag) & not (cs_val.global) then - raise_c2_exception(CapEx_PermitStoreLocalCapViolation, cb) - else - { - cursor = getCapCursor(cb_val); - vAddr = (cursor + unsigned(rGPR(rt)) + 16 * signed(offset)) % pow2(64); - vAddr64= to_bits(64, vAddr); - if ((vAddr + cap_size) > getCapTop(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (vAddr < getCapBase(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ((vAddr % cap_size) != 0) then - SignalExceptionBadAddr(AdES, vAddr64) - else - { - let (pAddr, noStoreCap) = TLBTranslateC(vAddr64, StoreData) in - if (cs_val.tag & noStoreCap) then - raise_c2_exception(CapEx_TLBNoStoreCap, cs) - else if (conditional) then - { - success = if (CP0LLBit[0]) then - MEMw_tagged_conditional(pAddr, cs_val.tag, capStructToMemBits(cs_val)) - else - false; - wGPR(rd) = zero_extend(success); - } - else - MEMw_tagged(pAddr, cs_val.tag, capStructToMemBits(cs_val)); - } - } -} - -union clause ast = CLC : (regno, regno, regno, bits(16), bool) -function clause execute (CLC(cd, cb, rt, offset, linked)) = -{ - checkCP2usable(); - cb_val = readCapRegDDC(cb); - if (register_inaccessible(cd)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cd) - else if (register_inaccessible(cb)) then - raise_c2_exception(CapEx_AccessSystemRegsViolation, cb) - else if not (cb_val.tag) then - raise_c2_exception(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - raise_c2_exception(CapEx_SealViolation, cb) - else if not (cb_val.permit_load) then - raise_c2_exception(CapEx_PermitLoadViolation, cb) - else - { - cursor = getCapCursor(cb_val); - vAddr = (cursor + unsigned(rGPR(rt)) + 16 * signed(offset)) % pow2(64); - vAddr64= to_bits(64, vAddr); - if ((vAddr + cap_size) > getCapTop(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if (vAddr < getCapBase(cb_val)) then - raise_c2_exception(CapEx_LengthViolation, cb) - else if ((vAddr % cap_size) != 0) then - SignalExceptionBadAddr(AdEL, vAddr64) - else - { - let (pAddr, suppressTag) = TLBTranslateC(vAddr64, LoadData) in - let 'cd = unsigned(cd) in - if (linked) then - { - CP0LLBit = 0b1; - CP0LLAddr = pAddr; - let (tag, mem) = MEMr_tagged_reserve(pAddr) in - (*CapRegs[cd]) = memBitsToCapBits(tag & (cb_val.permit_load_cap) & (not (suppressTag)), mem); - } - else - { - let (tag, mem) = MEMr_tagged(pAddr) in - (*CapRegs[cd]) = memBitsToCapBits(tag & (cb_val.permit_load_cap) & (not (suppressTag)), mem); - } - } - } -} - -union clause ast = C2Dump : regno -function clause execute (C2Dump (rt)) = - () /* Currently a NOP */ diff --git a/cheri/cheri_prelude_128.sail b/cheri/cheri_prelude_128.sail deleted file mode 100644 index da761c91..00000000 --- a/cheri/cheri_prelude_128.sail +++ /dev/null @@ -1,331 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* 128 bit cap + tag */ -type CapReg = bits(129) - -struct CapStruct = { - tag : bool , - uperms : bits(4) , - access_system_regs : bool , - permit_unseal : bool , - permit_ccall : bool , - permit_seal : bool , - permit_store_local_cap : bool , - permit_store_cap : bool , - permit_load_cap : bool , - permit_store : bool , - permit_load : bool , - permit_execute : bool , - global : bool , - reserved : bits(2) , - E : bits(6) , - sealed : bool , - B : bits(20), - T : bits(20), - otype : bits(24), - address : bits(64) -} - -let null_cap : CapStruct = struct { - tag = false, - uperms = zeros(), - access_system_regs = false, - permit_unseal = false, - permit_ccall = false, - permit_seal = false, - permit_store_local_cap = false, - permit_store_cap = false, - permit_load_cap = false, - permit_store = false, - permit_load = false, - permit_execute = false, - global = false, - reserved = zeros(), - E = 0b110000, /* 48, encoded as 0 in memory due to xor */ - sealed = false, - B = zeros(), - T = 0x10000, - otype = zeros(), - address = zeros() -} - -let default_cap : CapStruct = struct { - tag = true, - uperms = ones(), - access_system_regs = true, - permit_unseal = true, - permit_ccall = true, - permit_seal = true, - permit_store_local_cap = true, - permit_store_cap = true, - permit_load_cap = true, - permit_store = true, - permit_load = true, - permit_execute = true, - global = true, - reserved = zeros(), - E = 0b110000, /* 48, encoded as 0 in memory due to xor */ - sealed = false, - B = zeros(), - T = 0x10000, - otype = zeros(), - address = zeros() -} - -let 'cap_size = 16 - -function capRegToCapStruct(c) : CapReg -> CapStruct = - let s : bool = c[104] in - let Bc : bits(20) = if s then c[103..96] @ 0x000 else c[103..84] in - let Tc : bits(20) = if s then c[83..76] @ 0x000 else c[83..64] in - let otype : bits(24) = if s then c[95..84] @ c[75..64] else zeros() in - struct { - tag = c[128], - uperms = c[127..124], - access_system_regs = c[123], - permit_unseal = c[122], - permit_ccall = c[121], - permit_seal = c[120], - permit_store_local_cap = c[119], - permit_store_cap = c[118], - permit_load_cap = c[117], - permit_store = c[116], - permit_load = c[115], - permit_execute = c[114], - global = c[113], - reserved = c[112..111], - E = c[110..105], - sealed = s, - B = Bc, - T = Tc, - otype = otype, - address = c[63..0] - } - -function getCapHardPerms(cap) : CapStruct -> bits(11) = - (cap.access_system_regs - @ cap.permit_unseal - @ cap.permit_ccall - @ cap.permit_seal - @ cap.permit_store_local_cap - @ cap.permit_store_cap - @ cap.permit_load_cap - @ cap.permit_store - @ cap.permit_load - @ cap.permit_execute - @ cap.global) - -function capStructToMemBits128(cap) : CapStruct -> bits(128) = - let b : bits(20) = if cap.sealed then (cap.B)[19..12] @ (cap.otype)[23..12] else cap.B in - let t : bits(20) = if cap.sealed then (cap.T)[19..12] @ (cap.otype)[11..0] else cap.T in - ( cap.uperms - @ getCapHardPerms(cap) - @ cap.reserved - @ cap.E - @ cap.sealed - @ b - @ t - @ cap.address - ) - -function capStructToCapReg(cap) : CapStruct -> CapReg = - (cap.tag @ capStructToMemBits128(cap)) - -/* Reverse of above used when reading from memory */ -function memBitsToCapBits128(tag, b) : (bool, bits(128)) -> CapReg= - (tag @ b) - -/* When saving/restoring capabilities xor them with bits of null_cap -- - this ensures that canonical null_cap is always all-zeros in memory - even though it may have bits set logically (e.g. length or exponent */ - -let null_cap_bits : bits(128) = capStructToMemBits128(null_cap) - -function capStructToMemBits(cap) : CapStruct -> bits(128) = - capStructToMemBits128(cap) ^ null_cap_bits - -function memBitsToCapBits(tag, b) : (bool, bits(128)) -> bits(129) = - memBitsToCapBits128(tag, b ^ null_cap_bits) - -function getCapPerms(cap) : CapStruct -> bits(31) = - let perms : bits(15) = zero_extend(getCapHardPerms(cap)) in - (0x000 /* uperms 30-19 */ - @ cap.uperms - @ perms) - -function setCapPerms(cap, perms) : (CapStruct, bits(31)) -> CapStruct = - { cap with - uperms = perms[18..15], - /* 14..11 reserved -- ignore */ - access_system_regs = perms[10], - permit_unseal = perms[9], - permit_ccall = perms[8], - permit_seal = perms[7], - permit_store_local_cap = perms[6], - permit_store_cap = perms[5], - permit_load_cap = perms[4], - permit_store = perms[3], - permit_load = perms[2], - permit_execute = perms[1], - global = perms[0] - } - -function sealCap(cap, otype) : (CapStruct, bits(24)) -> (bool, CapStruct) = - if (((cap.T)[11..0] == zeros()) & ((cap.B)[11..0] == zeros())) then - (true, {cap with sealed=true, otype=otype}) - else - (false, cap /* XXX should be undefined? */ ) - -function a_top_correction(a_mid, R, bound) : (bits(20), bits(20), bits(20)) -> bits(65) = - match (a_mid <_u R, bound <_u R) { - (false, false) => zeros(), - (false, true) => zero_extend(0b1), - (true, false) => ones(), - (true, true) => zeros() - } - -function getCapBase(c) : CapStruct -> uint64 = - let E = min(unsigned(c.E), 48) in - let Bc : bits(20) = c.B in - let a : bits(65) = zero_extend(c.address) in - let R : bits(20) = Bc - 0x01000 in /* wraps */ - let a_mid : bits(20) = mask(a >> E) in - let correction = a_top_correction(a_mid, R, Bc) in - let a_top = a >> E+20 in - let base : bits(64) = mask(((a_top + correction) @ Bc) << E) in - unsigned(base) - -function getCapTop (c) : CapStruct -> CapLen = - let E = min(unsigned(c.E), 48) in - let Bc : bits(20) = c.B in - let T : bits(20) = c.T in - let a : bits(65) = zero_extend(c.address) in - let R : bits(20) = Bc - 0x01000 in /* wraps */ - let a_mid : bits(20) = mask(a >> E) in - let correction = a_top_correction(a_mid, R, T) in - let a_top = a >> E+20 in - let top1 : bits(65) = mask((a_top + correction) @ T) in - unsigned(top1 << E) - -function getCapOffset(c) : CapStruct -> uint64 = - let base = getCapBase(c) in - (unsigned(c.address) - base) % pow2(64) - -function getCapLength(c) : CapStruct -> CapLen = - let 'top = getCapTop(c) in - let 'base = getCapBase(c) in { - assert (top >= base); - top - base - } - -function getCapCursor(cap) : CapStruct -> uint64 = unsigned(cap.address) - -function fastRepCheck(c, i) : (CapStruct, bits(64)) -> bool= - let 'E = unsigned(c.E) in - if (E >= 44) then - true /* in this case representable region is whole address space */ - else - let E' = min(E, 43) in - let i_top = signed(i[63..E+20]) in - let i_mid : bits(20) = i[E+19..E] in - let a_mid : bits(20) = (c.address)[E+19..E] in - let R : bits(20) = (c.B) - 0x01000 in - let diff : bits(20) = R - a_mid in - let diff1 : bits(20) = diff - 1 in - /* i_top determines 1. whether the increment is inRange - i.e. less than the size of the representable region - (2**(E+20)) and 2. whether it is positive or negative. To - satisfy 1. all top bits must be the same so we are - interested in the cases i_top is 0 or -1 */ - if (i_top == 0) then - i_mid <_u diff1 - else if (i_top == -1) then - (i_mid >=_u diff) & (R != a_mid) - else - false - -function setCapOffset(c, offset) : (CapStruct, bits(64)) -> (bool, CapStruct) = - let base : bits(64) = to_bits(64, getCapBase(c)) in - let newAddress : bits(64) = base + offset in - let newCap = { c with address = newAddress } in - let representable = fastRepCheck(c, (newAddress - c.address)) in - (representable, newCap) - -function incCapOffset(c, delta) : (CapStruct, bits(64)) -> (bool, CapStruct) = - let newAddress : bits(64) = c.address + delta in - let newCap = { c with address = newAddress } in - let representable = fastRepCheck(c, delta) in - (representable, newCap) - -/** FUNCTION:integer HighestSetBit(bits(N) x) */ - -val HighestSetBit : forall 'N , 'N >= 2. bits('N) -> {'n, 0 <= 'n < 'N . (bool, atom('n))} -function HighestSetBit x = { - foreach (i from ('N - 1) to 0 by 1 in dec) - if [x[i]] == 0b1 then return (true, i); - return (false, 0) -} - -/* hw rounds up E to multiple of 4 */ -function roundUp(e) : range(0, 45) -> range(0, 48) = - let 'r = e % 4 in - if (r == 0) - then e - else (e - r + 4) - -function computeE (rlength) : bits(65) -> range(0, 48) = - let (nonzero, 'msb) = HighestSetBit((rlength + (rlength >> 6)) >> 19) in - if nonzero then - /* above will always return <= 45 because 19 bits of zero are shifted in from right */ - {assert(0 <= msb & msb <= 45); roundUp (min(msb,45)) } - else - 0 - -function setCapBounds(cap, base, top) : (CapStruct, bits(64), bits(65)) -> (bool, CapStruct) = - /* {cap with base=base; length=(bits(64)) length; offset=0} */ - let 'e = computeE(top - (0b0 @ base)) in - let Bc : bits(20) = mask(base >> e) in - let T : bits(20) = mask(top >> e) in - let e_mask : bits(65) = zero_extend(replicate_bits(0b1, e)) in - let e_bits = top & e_mask in - let T2 : bits(20) = T + (if unsigned(e_bits) == 0 then 0x00000 else 0x00001) in - let newCap = {cap with address=base, E=to_bits(6, e), B=Bc, T=T2} in - let newBase = getCapBase(newCap) in - let newTop = getCapTop(newCap) in - let exact = (unsigned(base) == newBase) & (unsigned(top) == newTop) in - (exact, newCap) - -function int_to_cap (offset) : bits(64) -> CapStruct = - {null_cap with address = offset} diff --git a/cheri/cheri_prelude_256.sail b/cheri/cheri_prelude_256.sail deleted file mode 100644 index 08e285e7..00000000 --- a/cheri/cheri_prelude_256.sail +++ /dev/null @@ -1,229 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* 256 bit cap + tag */ -type CapReg = bits(257) - -struct CapStruct = { - tag : bool , - padding : bits(8) , - otype : bits(24), - uperms : bits(16), - perm_reserved11_14 : bits(4) , - access_system_regs : bool , - permit_unseal : bool , - permit_ccall : bool , - permit_seal : bool , - permit_store_local_cap : bool , - permit_store_cap : bool , - permit_load_cap : bool , - permit_store : bool , - permit_load : bool , - permit_execute : bool , - global : bool , - sealed : bool , - address : bits(64), - base : bits(64), - length : bits(64), -} - -let null_cap : CapStruct = struct { - tag = false, - padding = zeros(), - otype = zeros(), - uperms = zeros(), - perm_reserved11_14 = zeros(), - access_system_regs = false, - permit_unseal = false, - permit_ccall = false, - permit_seal = false, - permit_store_local_cap = false, - permit_store_cap = false, - permit_load_cap = false, - permit_store = false, - permit_load = false, - permit_execute = false, - global = false, - sealed = false, - address = zeros(), - base = zeros(), - length = 0xffffffffffffffff -} - -let default_cap : CapStruct = struct { - tag = true, - padding = zeros(), - otype = zeros(), - uperms = ones(), - perm_reserved11_14 = zeros(), - access_system_regs = true, - permit_unseal = true, - permit_ccall = true, - permit_seal = true, - permit_store_local_cap = true, - permit_store_cap = true, - permit_load_cap = true, - permit_store = true, - permit_load = true, - permit_execute = true, - global = true, - sealed = false, - address = zeros(), - base = zeros(), - length = 0xffffffffffffffff -} - -let 'cap_size = 32 - -function capRegToCapStruct(capReg) : CapReg -> CapStruct = - struct { - tag = capReg[256], - padding = capReg[255..248], - otype = capReg[247..224], - uperms = capReg[223..208], - perm_reserved11_14 = capReg[207..204], - access_system_regs = capReg[203], - permit_unseal = capReg[202], - permit_ccall = capReg[201], - permit_seal = capReg[200], - permit_store_local_cap = capReg[199], - permit_store_cap = capReg[198], - permit_load_cap = capReg[197], - permit_store = capReg[196], - permit_load = capReg[195], - permit_execute = capReg[194], - global = capReg[193], - sealed = capReg[192], - address = capReg[191..128], - base = capReg[127..64], - length = capReg[63..0] - } - -function getCapPerms(cap) : CapStruct -> bits(31) = - ( - cap.uperms - @ cap.perm_reserved11_14 - @ cap.access_system_regs - @ cap.permit_unseal - @ cap.permit_ccall - @ cap.permit_seal - @ cap.permit_store_local_cap - @ cap.permit_store_cap - @ cap.permit_load_cap - @ cap.permit_store - @ cap.permit_load - @ cap.permit_execute - @ cap.global - ) - - -/* Function to convert capabilities to in-memory format. */ -function capStructToMemBits256(cap) : CapStruct -> bits(256) = - ( - cap.padding - @ cap.otype - @ getCapPerms(cap) - @ cap.sealed - @ cap.address - @ cap.base - @ cap.length - ) - - -/* When saving/restoring capabilities xor them with bits of null_cap -- - this ensures that canonical null_cap is always all-zeros in memory - even though it may have bits set logically (e.g. length or exponent) */ - -let null_cap_bits : bits(256) = capStructToMemBits256(null_cap) - -function capStructToMemBits(cap) : CapStruct -> bits(256)= - capStructToMemBits256(cap) ^ null_cap_bits - -function memBitsToCapBits(tag, b) : (bool, bits(256)) -> bits(257) = - tag @ (b ^ null_cap_bits) - -function capStructToCapReg(cap) : CapStruct -> CapReg = cap.tag @ capStructToMemBits256(cap) - -function setCapPerms(cap, perms) : (CapStruct, bits(31)) -> CapStruct = - { cap with - uperms = perms[30..15], - /* perm_reserved11_14 = perms[14..11], XXX should allow to set? only affects cbuildcap. */ - access_system_regs = perms[10], - permit_unseal = perms[9], - permit_ccall = perms[8], - permit_seal = perms[7], - permit_store_local_cap = perms[6], - permit_store_cap = perms[5], - permit_load_cap = perms[4], - permit_store = perms[3], - permit_load = perms[2], - permit_execute = perms[1], - global = perms[0] - } - -function sealCap(cap, otype) : (CapStruct, bits(24)) -> (bool, CapStruct) = - (true, {cap with sealed=true, otype=otype}) - -function getCapBase(c) : CapStruct -> uint64 = unsigned(c.base) -function getCapTop(c) : CapStruct -> CapLen = unsigned(c.base) + unsigned(c.length) /* XXX bug here? -- should be mod 2^64 */ -function getCapOffset(c) : CapStruct -> uint64 = (unsigned(c.address) - unsigned(c.base)) % (pow2(64)) -function getCapLength(c) : CapStruct -> CapLen = unsigned(c.length) - -function getCapCursor(c) : CapStruct -> uint64 = unsigned(c.address) - -/*! -Set the offset capability of the a capability to given value and return the result, along with a boolean indicating true if the operation preserved the existing bounds of the capability. When using compressed capabilities, setting the offset far outside the capability bounds can cause the result to become unrepresentable (XXX mention guarantees). Additionally in some implementations a fast representablity check may be used that could cause the operation to return failure even though the capability would be representable (XXX provide details). - */ -val setCapOffset : (CapStruct, bits(64)) -> (bool, CapStruct) -function setCapOffset(c, offset) = - (true, {c with address=c.base + offset}) - -/*! -\function{incCapOffset} is the same as \function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic). - */ -val incCapOffset : (CapStruct, bits(64)) -> (bool, CapStruct) -function incCapOffset(c, delta) = - let newAddr : bits(64) = c.address + delta in - (true, {c with address = newAddr}) - -/*! -Returns a capability derived from the given capability by setting the base and top to values provided. The offset of the resulting capability is zero. In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values. - */ -val setCapBounds : (CapStruct, bits(64), bits(65)) -> (bool, CapStruct) -function setCapBounds(cap, base, top) = - let length : bits(65) = top - (0b0 @ base) in - (true, {cap with base = base, length = length[63..0], address = base}) - -function int_to_cap (address) : bits(64) -> CapStruct = - {null_cap with address = address} diff --git a/cheri/cheri_prelude_common.sail b/cheri/cheri_prelude_common.sail deleted file mode 100644 index 764a4ff1..00000000 --- a/cheri/cheri_prelude_common.sail +++ /dev/null @@ -1,534 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - - -scattered union ast - -val execute : ast -> unit effect {barr, eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -scattered function execute - -val decode : bits(32) -> option(ast) effect pure -scattered function decode - -register PCC : CapReg -register nextPCC : CapReg -register delayedPCC : CapReg -register inCCallDelay : bits(1) -register DDC : CapReg -register C01 : CapReg -register C02 : CapReg -register C03 : CapReg -register C04 : CapReg -register C05 : CapReg -register C06 : CapReg -register C07 : CapReg -register C08 : CapReg -register C09 : CapReg -register C10 : CapReg -register C11 : CapReg -register C12 : CapReg -register C13 : CapReg -register C14 : CapReg -register C15 : CapReg -register C16 : CapReg -register C17 : CapReg -register C18 : CapReg -register C19 : CapReg -register C20 : CapReg -register C21 : CapReg -register C22 : CapReg -register C23 : CapReg -register C24 : CapReg /* aka return code capability, RCC */ -register C25 : CapReg -register C26 : CapReg /* aka invoked data capability, IDC */ -register C27 : CapReg -register C28 : CapReg -register C29 : CapReg -register C30 : CapReg -register C31 : CapReg - -register CTLSU : CapReg /* User thread local storage capabiltiy */ -register CTLSP : CapReg /* Privileged thread local storage capabiltiy */ -register KR1C : CapReg /* kernel reserved capability 1 */ -register KR2C : CapReg /* kernel reserved capability 2 */ -register KCC : CapReg /* kernel code capability */ -register KDC : CapReg /* kernel data capability */ -register EPCC : CapReg /* exception program counter capability */ - -let IDCNO : regno = 0b11010 /* C26, invoked data capability used be CCall */ - -/* Special register used to have these numbers -- here for transition purposes */ -let KR1CNO : regno = 0b11011 /* C27 */ -let KR2CNO : regno = 0b11100 /* C28 */ -let KCCNO : regno = 0b11101 /* C29 */ -let KDCNO : regno = 0b11110 /* C30 */ -let EPCCNO : regno = 0b11111 /* C31 */ - -let CapRegs : vector(32, dec, register(CapReg)) = - [ - ref C31, - ref C30, - ref C29, - ref C28, - ref C27, - ref C26, - ref C25, - ref C24, - ref C23, - ref C22, - ref C21, - ref C20, - ref C19, - ref C18, - ref C17, - ref C16, - ref C15, - ref C14, - ref C13, - ref C12, - ref C11, - ref C10, - ref C09, - ref C08, - ref C07, - ref C06, - ref C05, - ref C04, - ref C03, - ref C02, - ref C01, - ref DDC - ] - -let max_otype = MAX(24) /*0xffffff*/ -let have_cp2 = true - -/*! -This function reads a given capability register and returns its contents converted to a CapStruct. -If the argument is zero then the null capability is returned. -*/ -val readCapReg : regno -> CapStruct effect {rreg} -function readCapReg(n) = - if (n == 0b00000) then - null_cap - else - let i = unsigned(n) in - capRegToCapStruct(reg_deref(CapRegs[i])) - -/*! -This is the same as readCapReg except that when the argument is zero the value of DDC is returned -instead of the null capability. This is used for instructions that expect an address, where using -null would always generate an exception. -*/ -val readCapRegDDC : regno -> CapStruct effect {rreg} -function readCapRegDDC(n) = - let i = unsigned(n) in - capRegToCapStruct(reg_deref(CapRegs[i])) /* NB CapRegs[0] is points to DDC */ - -function writeCapReg(n, cap) : (regno, CapStruct) -> unit = - if (n == 0b00000) then - () - else - let i = unsigned(n) in - (*CapRegs[i]) = capStructToCapReg(cap) - -enum CapEx = { - CapEx_None, - CapEx_LengthViolation, - CapEx_TagViolation, - CapEx_SealViolation, - CapEx_TypeViolation, - CapEx_CallTrap, - CapEx_ReturnTrap, - CapEx_TSSUnderFlow, - CapEx_UserDefViolation, - CapEx_TLBNoStoreCap, - CapEx_InexactBounds, - CapEx_GlobalViolation, - CapEx_PermitExecuteViolation, - CapEx_PermitLoadViolation, - CapEx_PermitStoreViolation, - CapEx_PermitLoadCapViolation, - CapEx_PermitStoreCapViolation, - CapEx_PermitStoreLocalCapViolation, - CapEx_PermitSealViolation, - CapEx_AccessSystemRegsViolation, - CapEx_PermitCCallViolation, - CapEx_AccessCCallIDCViolation, - CapEx_PermitUnsealViolation -} - -function CapExCode(ex) : CapEx -> bits(8)= - match ex { - CapEx_None => 0x00, - CapEx_LengthViolation => 0x01, - CapEx_TagViolation => 0x02, - CapEx_SealViolation => 0x03, - CapEx_TypeViolation => 0x04, - CapEx_CallTrap => 0x05, - CapEx_ReturnTrap => 0x06, - CapEx_TSSUnderFlow => 0x07, - CapEx_UserDefViolation => 0x08, - CapEx_TLBNoStoreCap => 0x09, - CapEx_InexactBounds => 0x0a, - CapEx_GlobalViolation => 0x10, - CapEx_PermitExecuteViolation => 0x11, - CapEx_PermitLoadViolation => 0x12, - CapEx_PermitStoreViolation => 0x13, - CapEx_PermitLoadCapViolation => 0x14, - CapEx_PermitStoreCapViolation => 0x15, - CapEx_PermitStoreLocalCapViolation => 0x16, - CapEx_PermitSealViolation => 0x17, - CapEx_AccessSystemRegsViolation => 0x18, - CapEx_PermitCCallViolation => 0x19, - CapEx_AccessCCallIDCViolation => 0x1a, - CapEx_PermitUnsealViolation => 0x1b - } - -bitfield CapCauseReg : bits(16) = { - ExcCode : 15..8, - RegNum : 7..0, -} - -register CapCause : CapCauseReg - -val execute_branch_pcc : CapStruct -> unit effect {wreg} -function execute_branch_pcc(newPCC) = { - delayedPC = to_bits(64, getCapOffset(newPCC)); - delayedPCC = capStructToCapReg(newPCC); - branchPending = 0b1; -} - -function SignalException (ex) = - { - if (not (CP0Status.EXL())) then { - let pc = PC in - let pcc = capRegToCapStruct(PCC) in - let (success, epcc) = setCapOffset(pcc, pc) in - if (success) then - EPCC = capStructToCapReg(epcc) - else - EPCC = capStructToCapReg(int_to_cap(to_bits(64, getCapBase(pcc)) + unsigned(pc))); - }; - - nextPCC = KCC; - delayedPCC = KCC; /* always write delayedPCC together with nextPCC so - that non-capability branches don't override PCC */ - let base = getCapBase(capRegToCapStruct(KCC)) in - SignalExceptionMIPS(ex, to_bits(64, base)); - } - -function ERETHook() : unit -> unit = - { - nextPCC = EPCC; - delayedPCC = EPCC; /* always write delayedPCC together with nextPCC so - that non-capability branches don't override PCC */ - } - -val raise_c2_exception8 : forall ('o : Type) . (CapEx, bits(8)) -> 'o effect {escape, rreg, wreg} -function raise_c2_exception8(capEx, regnum) = - { - CapCause->ExcCode() = CapExCode(capEx); - CapCause->RegNum() = regnum; - let mipsEx = - if ((capEx == CapEx_CallTrap) | (capEx == CapEx_ReturnTrap)) - then C2Trap else C2E in - SignalException(mipsEx); - } - -val raise_c2_exception : forall ('o : Type) . (CapEx, regno) -> 'o effect {escape, rreg, wreg} -function raise_c2_exception(capEx, regnum) = - let reg8 = 0b000 @ regnum in - if ((capEx == CapEx_AccessSystemRegsViolation) & (regnum == IDCNO)) then - raise_c2_exception8(CapEx_AccessCCallIDCViolation, reg8) - else - raise_c2_exception8(capEx, reg8) - -val raise_c2_exception_noreg : forall ('o : Type) . (CapEx) -> 'o effect {escape, rreg, wreg} -function raise_c2_exception_noreg(capEx) = - raise_c2_exception8(capEx, 0xff) - -val pcc_access_system_regs : unit -> bool effect {rreg} -function pcc_access_system_regs () = - let pcc = capRegToCapStruct(PCC) in - (pcc.access_system_regs) - -/*! -The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. - */ -val register_inaccessible : regno -> bool effect {rreg} -function register_inaccessible(r) = - ((r == IDCNO) & inCCallDelay) | - ((r == KR1CNO | - r == KR2CNO | - r == KDCNO | - r == KCCNO | - r == EPCCNO) & not (pcc_access_system_regs ())) - -val MEMr_tag = "read_tag_bool" : bits(64) -> bool effect { rmemt } -val MEMw_tag = "write_tag_bool" : (bits(64) , bool) -> unit effect { wmvt } - -val MEMr_tagged : bits(64) -> (bool, bits('cap_size * 8)) effect { escape, rmem, rmemt } -function MEMr_tagged (addr) = -{ - /* assumes addr is cap. aligned */ - assert(unsigned(addr) % cap_size == 0); - let tag = MEMr_tag(addr) in - let data = MEMr(addr, cap_size) in - (tag, reverse_endianness(data)) -} - -val MEMr_tagged_reserve : bits(64) -> (bool, bits('cap_size * 8)) effect { escape, rmem, rmemt } -function MEMr_tagged_reserve (addr) = -{ - /* assumes addr is cap. aligned */ - assert(unsigned(addr) % cap_size == 0); - let tag = MEMr_tag(addr) in - let data = MEMr_reserve(addr, cap_size) in - (tag, reverse_endianness(data)) -} - -val MEMw_tagged : (bits(64), bool, bits('cap_size * 8)) -> unit effect { escape, eamem, wmv, wmvt } -function MEMw_tagged(addr, tag, data) = -{ - /* assumes addr is cap. aligned */ - assert(unsigned(addr) % cap_size == 0); - MEMea(addr, cap_size); - MEMval(addr, cap_size, reverse_endianness(data)); - MEMw_tag(addr, tag); -} - -val MEMw_tagged_conditional : (bits(64), bool, bits('cap_size * 8)) -> bool effect { escape, eamem, wmv, wmvt } -function MEMw_tagged_conditional(addr, tag, data) = -{ - /* assumes addr is cap. aligned */ - assert(unsigned(addr) % cap_size == 0); - MEMea_conditional(addr, cap_size); - success = MEMval_conditional(addr, cap_size, reverse_endianness(data)); - if success then - MEMw_tag(addr, tag); - success; -} - -let cap_addr_mask = to_bits(64, pow2(64) - cap_size) - -val MEMw_wrapper : forall 'n, 'n >= 1. (bits(64), atom('n), bits(8 * 'n)) -> unit effect {escape, wmv, wmvt, wreg, eamem} -function MEMw_wrapper(addr, size, data) = - let ledata = reverse_endianness(data) in - if (addr == 0x000000007f000000) then - { - UART_WDATA = ledata[7..0]; - UART_WRITTEN = 0b1; - } - else - { - /* require that writes don't cross capability boundaries (should be true due to mips alignment requirements) */ - assert((addr & cap_addr_mask) == ((addr + to_bits(64, size - 1)) & cap_addr_mask)); - MEMea(addr, size); - MEMval(addr, size, ledata); - /* On cheri non-capability writes must clear the corresponding tag*/ - MEMw_tag(addr & cap_addr_mask, false); - } - -val MEMw_conditional_wrapper : forall 'n, 'n >= 1. (bits(64), atom('n), bits(8 * 'n)) -> bool effect {escape, wmv, wmvt, eamem} -function MEMw_conditional_wrapper(addr, size, data) = - { - /* require that writes don't cross capability boundaries (should be true due to mips alignment requirements) */ - assert((addr & cap_addr_mask) == ((addr + to_bits(64, size - 1)) & cap_addr_mask)); - MEMea_conditional(addr, size); - success = MEMval_conditional(addr,size,reverse_endianness(data)); - if success then - /* On cheri non-capability writes must clear the corresponding tag */ - MEMw_tag(addr & cap_addr_mask, false); - success; - } - -val checkDDCPerms : (CapStruct, MemAccessType) -> unit effect {escape, rreg, wreg} -function checkDDCPerms(ddc : CapStruct, accessType: MemAccessType) = - { - if (not (ddc.tag)) then - raise_c2_exception(CapEx_TagViolation, 0b00000) - else if (ddc.sealed) then - raise_c2_exception(CapEx_SealViolation, 0b00000); - match accessType { - Instruction => assert(false), /* Only data accesses use DDC */ - LoadData => if (~(ddc.permit_load)) then (raise_c2_exception(CapEx_PermitLoadViolation, 0b00000)), - StoreData => if (~(ddc.permit_store)) then (raise_c2_exception(CapEx_PermitStoreViolation, 0b00000)) - }; - } - -val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) effect {rreg, wreg, escape} -function addrWrapper(addr, accessType, width) = - { - ddc = capRegToCapStruct(DDC); - checkDDCPerms(ddc, accessType); - cursor = getCapCursor(ddc); - vAddr = (cursor + unsigned(addr)) % pow2(64); - size = wordWidthBytes(width); - base = getCapBase(ddc); - top = getCapTop(ddc); - if ((vAddr + size) > top) then - (raise_c2_exception(CapEx_LengthViolation, 0b00000)) - else if (vAddr < base) then - (raise_c2_exception(CapEx_LengthViolation, 0b00000)) - else - to_bits(64, vAddr); - } - -val addrWrapperUnaligned : (bits(64), MemAccessType, WordTypeUnaligned) -> bits(64) effect {rreg, wreg, escape} -function addrWrapperUnaligned(addr, accessType, width) = - { - ddc = capRegToCapStruct(DDC); - checkDDCPerms(ddc, accessType); - cursor = getCapCursor(ddc); - vAddr = (cursor + unsigned(addr)) % pow2(64); - woffset = vAddr % 4; - doffset = vAddr % 8; - /* Compute the address and size of the bytes touched -- this depends on alignment. */ - let (waddr, size) : (int, int) = match width { - WL => (vAddr, 4 - woffset), - WR => (vAddr - woffset, woffset + 1), - DL => (vAddr, 8 - doffset), - DR => (vAddr - doffset, doffset + 1) - }; - base = getCapBase(ddc); - top = getCapTop(ddc); - if ((waddr + size) > top) then - (raise_c2_exception(CapEx_LengthViolation, 0b00000)) - else if (waddr < base) then - (raise_c2_exception(CapEx_LengthViolation, 0b00000)) - else - to_bits(64, vAddr); - } - -$ifdef _MIPS_TLB_STUB -val TranslatePC : bits(64) -> bits(64) effect {rreg, wreg, escape} -$else -val TranslatePC : bits(64) -> bits(64) effect {rreg, wreg, escape, undef} -$endif - -function TranslatePC (vAddr) = { - incrementCP0Count(); - let pcc = capRegToCapStruct(PCC); - let base = getCapBase(pcc); - let top = getCapTop(pcc); - let absPC = base + unsigned(vAddr); - if ((absPC % 4) != 0) then /* bad PC alignment */ - (SignalExceptionBadAddr(AdEL, to_bits(64, absPC))) /* XXX absPC may be truncated */ - else if not (pcc.tag) then - (raise_c2_exception_noreg(CapEx_TagViolation)) - else if ((absPC + 4) > top) then - (raise_c2_exception_noreg(CapEx_LengthViolation)) - else - TLBTranslate(to_bits(64, absPC), Instruction) /* XXX assert absPC never gets truncated due to above check and top <= 2^64 for valid caps */ -} - -/*! -All capability instrucitons must first check that the capability -co-processor is enabled using the following function that raises a -co-processor unusable exception if a CP0Status.CU2 is not set. This -allows the operating system to only save and restore the full -capability context for processes that use capabilities. -*/ -val checkCP2usable : unit -> unit effect {rreg, wreg, escape} -function checkCP2usable () = - if not (CP0Status.CU()[2]) then { - CP0Cause->CE() = 0b10; - SignalException(CpU); - } - -function init_cp2_state () = { - let defaultBits = capStructToCapReg(default_cap); - let nullBits = capStructToCapReg(null_cap); - PCC = defaultBits; - nextPCC = defaultBits; - delayedPCC = defaultBits; - DDC = defaultBits; - KCC = defaultBits; - EPCC = defaultBits; - KDC = nullBits; - KR1C = nullBits; - KR2C = nullBits; - CTLSP = nullBits; - CTLSU = nullBits; - foreach(i from 1 to 31) { - let idx = to_bits(5, i) in - writeCapReg(idx, null_cap) - } -} - -function cp2_next_pc () = { - PCC = nextPCC; - if inBranchDelay then { - nextPCC = delayedPCC; - } else { - inCCallDelay = 0b0; - }; -} - -val capToString : CapStruct -> string effect {escape} -function capToString cap = { - skip_escape(); /* because cheri128 getCapX functions contain asserts but cheri256 ones do not */ - concat_str(" t:", - concat_str(if cap.tag then "1" else "0", - concat_str(" s:", - concat_str(if cap.sealed then "1" else "0", - concat_str(" perms:", - concat_str(BitStr(0b0 @ getCapPerms(cap)), - concat_str(" type:", - concat_str(BitStr(cap.otype), - concat_str(" offset:", - concat_str(BitStr(to_bits(64, getCapOffset(cap))), - concat_str(" base:", - concat_str(BitStr(to_bits(64, getCapBase(cap))), - concat_str(" length:", BitStr(to_bits(64, min(getCapLength(cap), MAX(64))))))))))))))))) - } - -function dump_cp2_state () = { - print(concat_str("DEBUG CAP PCC", capToString(capRegToCapStruct(PCC)))); - foreach(i from 0 to 31) { - print(concat_str("DEBUG CAP REG ", concat_str(string_of_int(i), capToString(readCapReg(to_bits(5, i)))))) - }; - print(concat_str("DEBUG CAP HWREG 00", capToString(capRegToCapStruct(DDC)))); - print(concat_str("DEBUG CAP HWREG 01", capToString(capRegToCapStruct(CTLSU)))); - print(concat_str("DEBUG CAP HWREG 08", capToString(capRegToCapStruct(CTLSP)))); - /* TODO: these two should not be mirrored to match the FPGA */ - print(concat_str("DEBUG CAP HWREG 22", capToString(capRegToCapStruct(KR1C)))); - print(concat_str("DEBUG CAP HWREG 23", capToString(capRegToCapStruct(KR2C)))); - /* KCC, KDC, EPCC */ - print(concat_str("DEBUG CAP HWREG 29", capToString(capRegToCapStruct(KCC)))); - print(concat_str("DEBUG CAP HWREG 30", capToString(capRegToCapStruct(KDC)))); - print(concat_str("DEBUG CAP HWREG 31", capToString(capRegToCapStruct(EPCC)))); - -} diff --git a/cheri/cheri_types.sail b/cheri/cheri_types.sail deleted file mode 100644 index af23bcb4..00000000 --- a/cheri/cheri_types.sail +++ /dev/null @@ -1,55 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -type CapLen = range(0, 2 ^ 65) -type uint64 = range(0, (2 ^ 64) - 1) - -enum CPtrCmpOp = { - CEQ, - CNE, - CLT, - CLE, - CLTU, - CLEU, - CEXEQ, - CNEXEQ -} - -enum ClearRegSet = { -GPLo, -GPHi, -CLo, -CHi -} - diff --git a/cheri/sail_latex/commands.tex b/cheri/sail_latex/commands.tex deleted file mode 100644 index 76072eaf..00000000 --- a/cheri/sail_latex/commands.tex +++ /dev/null @@ -1,2667 +0,0 @@ -\newcommand{\sailsailregderefv}{\label{zregzyderef} \lstinputlisting[language=sail]{sail_latex/sailsailregderefv.tex}} - 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-\newcommand{\sailvectoraccess}{\label{zvectorzyaccess} \lstinputlisting[language=sail]{sail_latex/sailvectoraccess.tex}} - -\newcommand{\sailbitvectorupdate}{\label{zbitvectorzyupdate} \lstinputlisting[language=sail]{sail_latex/sailbitvectorupdate.tex}} - -\newcommand{\sailplainvectorupdate}{\label{zplainzyvectorzyupdate} \lstinputlisting[language=sail]{sail_latex/sailplainvectorupdate.tex}} - -\newcommand{\sailvectorupdate}{\label{zvectorzyupdate} \lstinputlisting[language=sail]{sail_latex/sailvectorupdate.tex}} - -\newcommand{\sailaddbits}{\label{zaddzybits} \lstinputlisting[language=sail]{sail_latex/sailaddbits.tex}} - -\newcommand{\sailaddbitsint}{\label{zaddzybitszyint} \lstinputlisting[language=sail]{sail_latex/sailaddbitsint.tex}} - -\newcommand{\sailsailzeightoperatorzzerozBzninev}{\label{zzeightoperatorzzerozBznine} \lstinputlisting[language=sail]{sail_latex/sailsailzeightoperatorzzerozBzninev.tex}} - -\newcommand{\sailvectorsubrange}{\label{zvectorzysubrange} \lstinputlisting[language=sail]{sail_latex/sailvectorsubrange.tex}} - -\newcommand{\sailvectorupdatesubrange}{\label{zvectorzyupdatezysubrange} \lstinputlisting[language=sail]{sail_latex/sailvectorupdatesubrange.tex}} - -\newcommand{\sailgetsliceint}{\label{zgetzyslicezyint} \lstinputlisting[language=sail]{sail_latex/sailgetsliceint.tex}} - -\newcommand{\sailsetsliceint}{\label{zsetzyslicezyint} \lstinputlisting[language=sail]{sail_latex/sailsetsliceint.tex}} - -\newcommand{\sailsetslicebits}{\label{zsetzyslicezybits} \lstinputlisting[language=sail]{sail_latex/sailsetslicebits.tex}} - -\newcommand{\sailslice}{\label{zslice} \lstinputlisting[language=sail]{sail_latex/sailslice.tex}} - -\newcommand{\sailreplicatebits}{\label{zreplicatezybits} \lstinputlisting[language=sail]{sail_latex/sailreplicatebits.tex}} - -\newcommand{\sailunsigned}{\label{zunsigned} \lstinputlisting[language=sail]{sail_latex/sailunsigned.tex}} - -\newcommand{\sailsigned}{\label{zsigned} \lstinputlisting[language=sail]{sail_latex/sailsigned.tex}} - -\newcommand{\saileqanything}{\label{zeqzyanything} \lstinputlisting[language=sail]{sail_latex/saileqanything.tex}} - -\newcommand{\sailzeightoperatorzzerozJzJznine}{\label{zzeightoperatorzzerozJzJznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozJzJznine.tex}} - -\newcommand{\sailnotvec}{\label{znotzyvec} \lstinputlisting[language=sail]{sail_latex/sailnotvec.tex}} - -\newcommand{\sailzW}{\label{zzW} \lstinputlisting[language=sail]{sail_latex/sailzW.tex}} - -\newcommand{\sailnot}{\label{znot} \lstinputlisting[language=sail]{sail_latex/sailnot.tex}} - -\newcommand{\sailneqvec}{\label{zneqzyvec} \lstinputlisting[language=sail]{sail_latex/sailneqvec.tex}} - -\newcommand{\sailfnneqvec}{\label{zneqzyvec} \lstinputlisting[language=sail]{sail_latex/sailfnneqvec.tex}} - -\newcommand{\sailneqanything}{\label{zneqzyanything} \lstinputlisting[language=sail]{sail_latex/sailneqanything.tex}} - -\newcommand{\sailfnneqanything}{\label{zneqzyanything} \lstinputlisting[language=sail]{sail_latex/sailfnneqanything.tex}} - -\newcommand{\sailzeightoperatorzzerozonezJznine}{\label{zzeightoperatorzzerozonezJznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozonezJznine.tex}} - -\newcommand{\sailandbits}{\label{zandzybits} \lstinputlisting[language=sail]{sail_latex/sailandbits.tex}} - -\newcommand{\sailzeightoperatorzzerozsixznine}{\label{zzeightoperatorzzerozsixznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozsixznine.tex}} - -\newcommand{\sailorbits}{\label{zorzybits} \lstinputlisting[language=sail]{sail_latex/sailorbits.tex}} - -\newcommand{\sailzeightoperatorzzerozUznine}{\label{zzeightoperatorzzerozUznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozUznine.tex}} - -\newcommand{\sailcastunitvec}{\label{zcastzyunitzyvec} \lstinputlisting[language=sail]{sail_latex/sailcastunitvec.tex}} - -\newcommand{\sailfncastunitvec}{\label{zcastzyunitzyvec} \lstinputlisting[language=sail]{sail_latex/sailfncastunitvec.tex}} - -\newcommand{\sailprint}{\label{zprint} \lstinputlisting[language=sail]{sail_latex/sailprint.tex}} - -\newcommand{\sailprerrendline}{\label{zprerrzyendline} \lstinputlisting[language=sail]{sail_latex/sailprerrendline.tex}} - -\newcommand{\sailprerrstring}{\label{zprerrzystring} \lstinputlisting[language=sail]{sail_latex/sailprerrstring.tex}} - -\newcommand{\sailputchar}{\label{zputchar} \lstinputlisting[language=sail]{sail_latex/sailputchar.tex}} - -\newcommand{\sailconcatstr}{\label{zconcatzystr} \lstinputlisting[language=sail]{sail_latex/sailconcatstr.tex}} - -\newcommand{\sailstringofint}{\label{zstringzyofzyint} \lstinputlisting[language=sail]{sail_latex/sailstringofint.tex}} - -\newcommand{\sailBitStr}{\label{zBitStr} \lstinputlisting[language=sail]{sail_latex/sailBitStr.tex}} - -\newcommand{\sailxorvec}{\label{zxorzyvec} \lstinputlisting[language=sail]{sail_latex/sailxorvec.tex}} - -\newcommand{\sailintpower}{\label{zintzypower} \lstinputlisting[language=sail]{sail_latex/sailintpower.tex}} - -\newcommand{\sailzeightoperatorzzerozQznine}{\label{zzeightoperatorzzerozQznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozQznine.tex}} - -\newcommand{\sailaddrange}{\label{zaddzyrange} \lstinputlisting[language=sail]{sail_latex/sailaddrange.tex}} - -\newcommand{\sailaddvec}{\label{zaddzyvec} \lstinputlisting[language=sail]{sail_latex/sailaddvec.tex}} - -\newcommand{\sailaddvecint}{\label{zaddzyveczyint} \lstinputlisting[language=sail]{sail_latex/sailaddvecint.tex}} - -\newcommand{\sailzeightoperatorzzerozBznine}{\label{zzeightoperatorzzerozBznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozBznine.tex}} - -\newcommand{\sailsubrange}{\label{zsubzyrange} \lstinputlisting[language=sail]{sail_latex/sailsubrange.tex}} - -\newcommand{\sailsubvec}{\label{zsubzyvec} \lstinputlisting[language=sail]{sail_latex/sailsubvec.tex}} - -\newcommand{\sailsubvecint}{\label{zsubzyveczyint} \lstinputlisting[language=sail]{sail_latex/sailsubvecint.tex}} - -\newcommand{\sailnegaterange}{\label{znegatezyrange} \lstinputlisting[language=sail]{sail_latex/sailnegaterange.tex}} - -\newcommand{\sailzeightoperatorzzerozDznine}{\label{zzeightoperatorzzerozDznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozDznine.tex}} - -\newcommand{\sailnegate}{\label{znegate} \lstinputlisting[language=sail]{sail_latex/sailnegate.tex}} - -\newcommand{\sailzeightoperatorzzerozAznine}{\label{zzeightoperatorzzerozAznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozAznine.tex}} - -\newcommand{\sailquotientnat}{\label{zquotientzynat} \lstinputlisting[language=sail]{sail_latex/sailquotientnat.tex}} - -\newcommand{\sailquotient}{\label{zquotient} \lstinputlisting[language=sail]{sail_latex/sailquotient.tex}} - -\newcommand{\sailzeightoperatorzzerozFznine}{\label{zzeightoperatorzzerozFznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozFznine.tex}} - -\newcommand{\sailquotroundzzero}{\label{zquotzyroundzyzzero} \lstinputlisting[language=sail]{sail_latex/sailquotroundzzero.tex}} - -\newcommand{\sailremroundzzero}{\label{zremzyroundzyzzero} \lstinputlisting[language=sail]{sail_latex/sailremroundzzero.tex}} - -\newcommand{\sailmodulus}{\label{zmodulus} \lstinputlisting[language=sail]{sail_latex/sailmodulus.tex}} - -\newcommand{\sailzeightoperatorzzerozfiveznine}{\label{zzeightoperatorzzerozfiveznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozfiveznine.tex}} - -\newcommand{\sailminnat}{\label{zminzynat} \lstinputlisting[language=sail]{sail_latex/sailminnat.tex}} - -\newcommand{\sailminint}{\label{zminzyint} \lstinputlisting[language=sail]{sail_latex/sailminint.tex}} - -\newcommand{\sailmaxnat}{\label{zmaxzynat} \lstinputlisting[language=sail]{sail_latex/sailmaxnat.tex}} - -\newcommand{\sailmaxint}{\label{zmaxzyint} \lstinputlisting[language=sail]{sail_latex/sailmaxint.tex}} - -\newcommand{\sailminatom}{\label{zminzyatom} \lstinputlisting[language=sail]{sail_latex/sailminatom.tex}} - -\newcommand{\sailmaxatom}{\label{zmaxzyatom} \lstinputlisting[language=sail]{sail_latex/sailmaxatom.tex}} - -\newcommand{\sailmin}{\label{zmin} \lstinputlisting[language=sail]{sail_latex/sailmin.tex}} - -\newcommand{\sailsailmaxv}{\label{zmax} \lstinputlisting[language=sail]{sail_latex/sailsailmaxv.tex}} - -\newcommand{\sailWriteRAM}{\label{zzyzyWriteRAM} \lstinputlisting[language=sail]{sail_latex/sailWriteRAM.tex}} - -\newcommand{\sailMIPSwrite}{\label{zzyzyMIPSzywrite} \lstinputlisting[language=sail]{sail_latex/sailMIPSwrite.tex}} - -\newcommand{\sailfnMIPSwrite}{\label{zzyzyMIPSzywrite} \lstinputlisting[language=sail]{sail_latex/sailfnMIPSwrite.tex}} - -\newcommand{\sailReadRAM}{\label{zzyzyReadRAM} \lstinputlisting[language=sail]{sail_latex/sailReadRAM.tex}} - -\newcommand{\sailMIPSread}{\label{zzyzyMIPSzyread} \lstinputlisting[language=sail]{sail_latex/sailMIPSread.tex}} - -\newcommand{\sailfnMIPSread}{\label{zzyzyMIPSzyread} \lstinputlisting[language=sail]{sail_latex/sailfnMIPSread.tex}} - -\newcommand{\sailzeightoperatorzzerozQzQznine}{\label{zzeightoperatorzzerozQzQznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozQzQznine.tex}} - -\newcommand{\sailfnzeightoperatorzzerozQzQznine}{\label{zzeightoperatorzzerozQzQznine} \lstinputlisting[language=sail]{sail_latex/sailfnzeightoperatorzzerozQzQznine.tex}} - -\newcommand{\sailpowtwo}{\label{zpowtwo} \lstinputlisting[language=sail]{sail_latex/sailpowtwo.tex}} - -\newcommand{\sailmipssignextend}{\label{zmipszysignzyextend} \lstinputlisting[language=sail]{sail_latex/sailmipssignextend.tex}} - -\newcommand{\sailmipszzeroextend}{\label{zmipszyzzerozyextend} \lstinputlisting[language=sail]{sail_latex/sailmipszzeroextend.tex}} - -\newcommand{\sailfnmipssignextend}{\label{zmipszysignzyextend} \lstinputlisting[language=sail]{sail_latex/sailfnmipssignextend.tex}} - -\newcommand{\sailfnmipszzeroextend}{\label{zmipszyzzerozyextend} \lstinputlisting[language=sail]{sail_latex/sailfnmipszzeroextend.tex}} - -\newcommand{\sailsignextend}{\label{zsignzyextend} \lstinputlisting[language=sail]{sail_latex/sailsignextend.tex}} - -\newcommand{\sailzzeroextend}{\label{zzzerozyextend} \lstinputlisting[language=sail]{sail_latex/sailzzeroextend.tex}} - -\newcommand{\sailzzeros}{\label{zzzeros} \lstinputlisting[language=sail]{sail_latex/sailzzeros.tex}} - -\newcommand{\sailfnzzeros}{\label{zzzeros} \lstinputlisting[language=sail]{sail_latex/sailfnzzeros.tex}} - -\newcommand{\sailones}{\label{zones} \lstinputlisting[language=sail]{sail_latex/sailones.tex}} - -\newcommand{\sailfnones}{\label{zones} \lstinputlisting[language=sail]{sail_latex/sailfnones.tex}} - -\newcommand{\sailzeightoperatorzzerozIsznine}{\label{zzeightoperatorzzerozIzysznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozIsznine.tex}} - -\newcommand{\sailzeightoperatorzzerozKzJsznine}{\label{zzeightoperatorzzerozKzJzysznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozKzJsznine.tex}} - -\newcommand{\sailzeightoperatorzzerozIuznine}{\label{zzeightoperatorzzerozIzyuznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozIuznine.tex}} - -\newcommand{\sailzeightoperatorzzerozKzJuznine}{\label{zzeightoperatorzzerozKzJzyuznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozKzJuznine.tex}} - -\newcommand{\sailfnzeightoperatorzzerozIsznine}{\label{zzeightoperatorzzerozIzysznine} \lstinputlisting[language=sail]{sail_latex/sailfnzeightoperatorzzerozIsznine.tex}} - -\newcommand{\sailfnzeightoperatorzzerozKzJsznine}{\label{zzeightoperatorzzerozKzJzysznine} \lstinputlisting[language=sail]{sail_latex/sailfnzeightoperatorzzerozKzJsznine.tex}} - -\newcommand{\sailfnzeightoperatorzzerozIuznine}{\label{zzeightoperatorzzerozIzyuznine} \lstinputlisting[language=sail]{sail_latex/sailfnzeightoperatorzzerozIuznine.tex}} - -\newcommand{\sailfnzeightoperatorzzerozKzJuznine}{\label{zzeightoperatorzzerozKzJzyuznine} \lstinputlisting[language=sail]{sail_latex/sailfnzeightoperatorzzerozKzJuznine.tex}} - -\newcommand{\sailbooltobits}{\label{zboolzytozybits} \lstinputlisting[language=sail]{sail_latex/sailbooltobits.tex}} - -\newcommand{\sailfnbooltobits}{\label{zboolzytozybits} \lstinputlisting[language=sail]{sail_latex/sailfnbooltobits.tex}} - -\newcommand{\sailbittobool}{\label{zbitzytozybool} \lstinputlisting[language=sail]{sail_latex/sailbittobool.tex}} - -\newcommand{\sailfnbittobool}{\label{zbitzytozybool} \lstinputlisting[language=sail]{sail_latex/sailfnbittobool.tex}} - -\newcommand{\sailbitstobool}{\label{zbitszytozybool} \lstinputlisting[language=sail]{sail_latex/sailbitstobool.tex}} - -\newcommand{\sailfnbitstobool}{\label{zbitszytozybool} \lstinputlisting[language=sail]{sail_latex/sailfnbitstobool.tex}} - -\newcommand{\sailshiftbitsright}{\label{zshiftzybitszyright} \lstinputlisting[language=sail]{sail_latex/sailshiftbitsright.tex}} - -\newcommand{\sailshiftbitsleft}{\label{zshiftzybitszyleft} \lstinputlisting[language=sail]{sail_latex/sailshiftbitsleft.tex}} - -\newcommand{\sailshiftl}{\label{zshiftl} \lstinputlisting[language=sail]{sail_latex/sailshiftl.tex}} - -\newcommand{\sailshiftr}{\label{zshiftr} \lstinputlisting[language=sail]{sail_latex/sailshiftr.tex}} - -\newcommand{\sailzeightoperatorzzerozKzKznine}{\label{zzeightoperatorzzerozKzKznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozKzKznine.tex}} - -\newcommand{\sailzeightoperatorzzerozIzIznine}{\label{zzeightoperatorzzerozIzIznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozIzIznine.tex}} - -\newcommand{\sailzeightoperatorzzerozKzKsznine}{\label{zzeightoperatorzzerozKzKzysznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozKzKsznine.tex}} - -\newcommand{\sailzeightoperatorzzerozAsznine}{\label{zzeightoperatorzzerozAzysznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozAsznine.tex}} - -\newcommand{\sailzeightoperatorzzerozAuznine}{\label{zzeightoperatorzzerozAzyuznine} \lstinputlisting[language=sail]{sail_latex/sailzeightoperatorzzerozAuznine.tex}} - -\newcommand{\sailtobits}{\label{ztozybits} -\function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. -\lstinputlisting[language=sail]{sail_latex/sailtobits.tex}} - -\newcommand{\sailfntobits}{\label{ztozybits} \lstinputlisting[language=sail]{sail_latex/sailfntobits.tex}} - -\newcommand{\sailmask}{\label{zmask} \lstinputlisting[language=sail]{sail_latex/sailmask.tex}} - -\newcommand{\sailfnmask}{\label{zmask} \lstinputlisting[language=sail]{sail_latex/sailfnmask.tex}} - -\newcommand{\sailgettimens}{\label{zgetzytimezyns} \lstinputlisting[language=sail]{sail_latex/sailgettimens.tex}} - -\newcommand{\sailCauseReg}{\label{zCauseReg} \lstinputlisting[language=sail]{sail_latex/sailCauseReg.tex}} - -\newcommand{\sailMkCauseReg}{\label{zMkzyCauseReg} \lstinputlisting[language=sail]{sail_latex/sailMkCauseReg.tex}} - -\newcommand{\sailfnMkCauseReg}{\label{zMkzyCauseReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkCauseReg.tex}} - -\newcommand{\sailgetCauseRegbits}{\label{zzygetzyCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegbits.tex}} - -\newcommand{\sailfngetCauseRegbits}{\label{zzygetzyCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegbits.tex}} - -\newcommand{\sailsetCauseRegbits}{\label{zzysetzyCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegbits.tex}} - -\newcommand{\sailfnsetCauseRegbits}{\label{zzysetzyCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegbits.tex}} - -\newcommand{\sailupdateCauseRegbits}{\label{zzyupdatezyCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegbits.tex}} - -\newcommand{\sailfnupdateCauseRegbits}{\label{zzyupdatezyCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegbits.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailupdatebitsvvvvvvv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailupdatebitsvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailmodbitsvvvvvvv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailmodbitsvvvvvvv.tex}} - -\newcommand{\sailgetCauseRegBD}{\label{zzygetzyCauseRegzyBD} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegBD.tex}} - -\newcommand{\sailfngetCauseRegBD}{\label{zzygetzyCauseRegzyBD} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegBD.tex}} - -\newcommand{\sailsetCauseRegBD}{\label{zzysetzyCauseRegzyBD} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegBD.tex}} - -\newcommand{\sailfnsetCauseRegBD}{\label{zzysetzyCauseRegzyBD} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegBD.tex}} - -\newcommand{\sailupdateCauseRegBD}{\label{zzyupdatezyCauseRegzyBD} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegBD.tex}} - -\newcommand{\sailfnupdateCauseRegBD}{\label{zzyupdatezyCauseRegzyBD} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegBD.tex}} - -\newcommand{\sailupdateBD}{\label{zupdatezyBD} \lstinputlisting[language=sail]{sail_latex/sailupdateBD.tex}} - -\newcommand{\sailmodBD}{\label{zzymodzyBD} \lstinputlisting[language=sail]{sail_latex/sailmodBD.tex}} - -\newcommand{\sailgetCauseRegCE}{\label{zzygetzyCauseRegzyCE} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegCE.tex}} - -\newcommand{\sailfngetCauseRegCE}{\label{zzygetzyCauseRegzyCE} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegCE.tex}} - -\newcommand{\sailsetCauseRegCE}{\label{zzysetzyCauseRegzyCE} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegCE.tex}} - -\newcommand{\sailfnsetCauseRegCE}{\label{zzysetzyCauseRegzyCE} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegCE.tex}} - -\newcommand{\sailupdateCauseRegCE}{\label{zzyupdatezyCauseRegzyCE} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegCE.tex}} - -\newcommand{\sailfnupdateCauseRegCE}{\label{zzyupdatezyCauseRegzyCE} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegCE.tex}} - -\newcommand{\sailupdateCE}{\label{zupdatezyCE} \lstinputlisting[language=sail]{sail_latex/sailupdateCE.tex}} - -\newcommand{\sailmodCE}{\label{zzymodzyCE} \lstinputlisting[language=sail]{sail_latex/sailmodCE.tex}} - -\newcommand{\sailgetCauseRegIV}{\label{zzygetzyCauseRegzyIV} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegIV.tex}} - -\newcommand{\sailfngetCauseRegIV}{\label{zzygetzyCauseRegzyIV} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegIV.tex}} - -\newcommand{\sailsetCauseRegIV}{\label{zzysetzyCauseRegzyIV} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegIV.tex}} - -\newcommand{\sailfnsetCauseRegIV}{\label{zzysetzyCauseRegzyIV} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegIV.tex}} - -\newcommand{\sailupdateCauseRegIV}{\label{zzyupdatezyCauseRegzyIV} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegIV.tex}} - -\newcommand{\sailfnupdateCauseRegIV}{\label{zzyupdatezyCauseRegzyIV} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegIV.tex}} - -\newcommand{\sailupdateIV}{\label{zupdatezyIV} \lstinputlisting[language=sail]{sail_latex/sailupdateIV.tex}} - -\newcommand{\sailmodIV}{\label{zzymodzyIV} \lstinputlisting[language=sail]{sail_latex/sailmodIV.tex}} - -\newcommand{\sailgetCauseRegWP}{\label{zzygetzyCauseRegzyWP} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegWP.tex}} - -\newcommand{\sailfngetCauseRegWP}{\label{zzygetzyCauseRegzyWP} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegWP.tex}} - -\newcommand{\sailsetCauseRegWP}{\label{zzysetzyCauseRegzyWP} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegWP.tex}} - -\newcommand{\sailfnsetCauseRegWP}{\label{zzysetzyCauseRegzyWP} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegWP.tex}} - -\newcommand{\sailupdateCauseRegWP}{\label{zzyupdatezyCauseRegzyWP} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegWP.tex}} - -\newcommand{\sailfnupdateCauseRegWP}{\label{zzyupdatezyCauseRegzyWP} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegWP.tex}} - -\newcommand{\sailupdateWP}{\label{zupdatezyWP} \lstinputlisting[language=sail]{sail_latex/sailupdateWP.tex}} - -\newcommand{\sailmodWP}{\label{zzymodzyWP} \lstinputlisting[language=sail]{sail_latex/sailmodWP.tex}} - -\newcommand{\sailgetCauseRegIP}{\label{zzygetzyCauseRegzyIP} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegIP.tex}} - -\newcommand{\sailfngetCauseRegIP}{\label{zzygetzyCauseRegzyIP} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegIP.tex}} - -\newcommand{\sailsetCauseRegIP}{\label{zzysetzyCauseRegzyIP} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegIP.tex}} - -\newcommand{\sailfnsetCauseRegIP}{\label{zzysetzyCauseRegzyIP} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegIP.tex}} - -\newcommand{\sailupdateCauseRegIP}{\label{zzyupdatezyCauseRegzyIP} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegIP.tex}} - -\newcommand{\sailfnupdateCauseRegIP}{\label{zzyupdatezyCauseRegzyIP} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegIP.tex}} - -\newcommand{\sailupdateIP}{\label{zupdatezyIP} \lstinputlisting[language=sail]{sail_latex/sailupdateIP.tex}} - -\newcommand{\sailmodIP}{\label{zzymodzyIP} \lstinputlisting[language=sail]{sail_latex/sailmodIP.tex}} - -\newcommand{\sailgetCauseRegExcCode}{\label{zzygetzyCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailgetCauseRegExcCode.tex}} - -\newcommand{\sailfngetCauseRegExcCode}{\label{zzygetzyCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailfngetCauseRegExcCode.tex}} - -\newcommand{\sailsetCauseRegExcCode}{\label{zzysetzyCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailsetCauseRegExcCode.tex}} - -\newcommand{\sailfnsetCauseRegExcCode}{\label{zzysetzyCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailfnsetCauseRegExcCode.tex}} - -\newcommand{\sailupdateCauseRegExcCode}{\label{zzyupdatezyCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailupdateCauseRegExcCode.tex}} - -\newcommand{\sailfnupdateCauseRegExcCode}{\label{zzyupdatezyCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCauseRegExcCode.tex}} - -\newcommand{\sailsailupdateExcCodev}{\label{zupdatezyExcCode} \lstinputlisting[language=sail]{sail_latex/sailsailupdateExcCodev.tex}} - -\newcommand{\sailsailmodExcCodev}{\label{zzymodzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailsailmodExcCodev.tex}} - -\newcommand{\sailTLBEntryLoReg}{\label{zTLBEntryLoReg} \lstinputlisting[language=sail]{sail_latex/sailTLBEntryLoReg.tex}} - -\newcommand{\sailMkTLBEntryLoReg}{\label{zMkzyTLBEntryLoReg} \lstinputlisting[language=sail]{sail_latex/sailMkTLBEntryLoReg.tex}} - -\newcommand{\sailfnMkTLBEntryLoReg}{\label{zMkzyTLBEntryLoReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkTLBEntryLoReg.tex}} - -\newcommand{\sailgetTLBEntryLoRegbits}{\label{zzygetzyTLBEntryLoRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegbits.tex}} - -\newcommand{\sailfngetTLBEntryLoRegbits}{\label{zzygetzyTLBEntryLoRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegbits.tex}} - -\newcommand{\sailsetTLBEntryLoRegbits}{\label{zzysetzyTLBEntryLoRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegbits.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegbits}{\label{zzysetzyTLBEntryLoRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegbits.tex}} - -\newcommand{\sailupdateTLBEntryLoRegbits}{\label{zzyupdatezyTLBEntryLoRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegbits.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegbits}{\label{zzyupdatezyTLBEntryLoRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegbits.tex}} - -\newcommand{\sailsailsailsailsailsailsailupdatebitsvvvvvv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailupdatebitsvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailmodbitsvvvvvv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailmodbitsvvvvvv.tex}} - -\newcommand{\sailgetTLBEntryLoRegCapS}{\label{zzygetzyTLBEntryLoRegzyCapS} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegCapS.tex}} - -\newcommand{\sailfngetTLBEntryLoRegCapS}{\label{zzygetzyTLBEntryLoRegzyCapS} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegCapS.tex}} - -\newcommand{\sailsetTLBEntryLoRegCapS}{\label{zzysetzyTLBEntryLoRegzyCapS} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegCapS.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegCapS}{\label{zzysetzyTLBEntryLoRegzyCapS} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegCapS.tex}} - -\newcommand{\sailupdateTLBEntryLoRegCapS}{\label{zzyupdatezyTLBEntryLoRegzyCapS} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegCapS.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegCapS}{\label{zzyupdatezyTLBEntryLoRegzyCapS} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegCapS.tex}} - -\newcommand{\sailupdateCapS}{\label{zupdatezyCapS} \lstinputlisting[language=sail]{sail_latex/sailupdateCapS.tex}} - -\newcommand{\sailmodCapS}{\label{zzymodzyCapS} \lstinputlisting[language=sail]{sail_latex/sailmodCapS.tex}} - -\newcommand{\sailgetTLBEntryLoRegCapL}{\label{zzygetzyTLBEntryLoRegzyCapL} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegCapL.tex}} - -\newcommand{\sailfngetTLBEntryLoRegCapL}{\label{zzygetzyTLBEntryLoRegzyCapL} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegCapL.tex}} - -\newcommand{\sailsetTLBEntryLoRegCapL}{\label{zzysetzyTLBEntryLoRegzyCapL} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegCapL.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegCapL}{\label{zzysetzyTLBEntryLoRegzyCapL} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegCapL.tex}} - -\newcommand{\sailupdateTLBEntryLoRegCapL}{\label{zzyupdatezyTLBEntryLoRegzyCapL} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegCapL.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegCapL}{\label{zzyupdatezyTLBEntryLoRegzyCapL} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegCapL.tex}} - -\newcommand{\sailupdateCapL}{\label{zupdatezyCapL} \lstinputlisting[language=sail]{sail_latex/sailupdateCapL.tex}} - -\newcommand{\sailmodCapL}{\label{zzymodzyCapL} \lstinputlisting[language=sail]{sail_latex/sailmodCapL.tex}} - -\newcommand{\sailgetTLBEntryLoRegPFN}{\label{zzygetzyTLBEntryLoRegzyPFN} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegPFN.tex}} - -\newcommand{\sailfngetTLBEntryLoRegPFN}{\label{zzygetzyTLBEntryLoRegzyPFN} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegPFN.tex}} - -\newcommand{\sailsetTLBEntryLoRegPFN}{\label{zzysetzyTLBEntryLoRegzyPFN} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegPFN.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegPFN}{\label{zzysetzyTLBEntryLoRegzyPFN} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegPFN.tex}} - -\newcommand{\sailupdateTLBEntryLoRegPFN}{\label{zzyupdatezyTLBEntryLoRegzyPFN} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegPFN.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegPFN}{\label{zzyupdatezyTLBEntryLoRegzyPFN} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegPFN.tex}} - -\newcommand{\sailupdatePFN}{\label{zupdatezyPFN} \lstinputlisting[language=sail]{sail_latex/sailupdatePFN.tex}} - -\newcommand{\sailmodPFN}{\label{zzymodzyPFN} \lstinputlisting[language=sail]{sail_latex/sailmodPFN.tex}} - -\newcommand{\sailgetTLBEntryLoRegC}{\label{zzygetzyTLBEntryLoRegzyC} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegC.tex}} - -\newcommand{\sailfngetTLBEntryLoRegC}{\label{zzygetzyTLBEntryLoRegzyC} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegC.tex}} - -\newcommand{\sailsetTLBEntryLoRegC}{\label{zzysetzyTLBEntryLoRegzyC} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegC.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegC}{\label{zzysetzyTLBEntryLoRegzyC} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegC.tex}} - -\newcommand{\sailupdateTLBEntryLoRegC}{\label{zzyupdatezyTLBEntryLoRegzyC} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegC.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegC}{\label{zzyupdatezyTLBEntryLoRegzyC} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegC.tex}} - -\newcommand{\sailupdateC}{\label{zupdatezyC} \lstinputlisting[language=sail]{sail_latex/sailupdateC.tex}} - -\newcommand{\sailmodC}{\label{zzymodzyC} \lstinputlisting[language=sail]{sail_latex/sailmodC.tex}} - -\newcommand{\sailgetTLBEntryLoRegD}{\label{zzygetzyTLBEntryLoRegzyD} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegD.tex}} - -\newcommand{\sailfngetTLBEntryLoRegD}{\label{zzygetzyTLBEntryLoRegzyD} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegD.tex}} - -\newcommand{\sailsetTLBEntryLoRegD}{\label{zzysetzyTLBEntryLoRegzyD} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegD.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegD}{\label{zzysetzyTLBEntryLoRegzyD} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegD.tex}} - -\newcommand{\sailupdateTLBEntryLoRegD}{\label{zzyupdatezyTLBEntryLoRegzyD} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegD.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegD}{\label{zzyupdatezyTLBEntryLoRegzyD} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegD.tex}} - -\newcommand{\sailupdateD}{\label{zupdatezyD} \lstinputlisting[language=sail]{sail_latex/sailupdateD.tex}} - -\newcommand{\sailmodD}{\label{zzymodzyD} \lstinputlisting[language=sail]{sail_latex/sailmodD.tex}} - -\newcommand{\sailgetTLBEntryLoRegV}{\label{zzygetzyTLBEntryLoRegzyV} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegV.tex}} - -\newcommand{\sailfngetTLBEntryLoRegV}{\label{zzygetzyTLBEntryLoRegzyV} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegV.tex}} - -\newcommand{\sailsetTLBEntryLoRegV}{\label{zzysetzyTLBEntryLoRegzyV} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegV.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegV}{\label{zzysetzyTLBEntryLoRegzyV} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegV.tex}} - -\newcommand{\sailupdateTLBEntryLoRegV}{\label{zzyupdatezyTLBEntryLoRegzyV} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegV.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegV}{\label{zzyupdatezyTLBEntryLoRegzyV} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegV.tex}} - -\newcommand{\sailupdateV}{\label{zupdatezyV} \lstinputlisting[language=sail]{sail_latex/sailupdateV.tex}} - -\newcommand{\sailmodV}{\label{zzymodzyV} \lstinputlisting[language=sail]{sail_latex/sailmodV.tex}} - -\newcommand{\sailgetTLBEntryLoRegG}{\label{zzygetzyTLBEntryLoRegzyG} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryLoRegG.tex}} - -\newcommand{\sailfngetTLBEntryLoRegG}{\label{zzygetzyTLBEntryLoRegzyG} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryLoRegG.tex}} - -\newcommand{\sailsetTLBEntryLoRegG}{\label{zzysetzyTLBEntryLoRegzyG} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryLoRegG.tex}} - -\newcommand{\sailfnsetTLBEntryLoRegG}{\label{zzysetzyTLBEntryLoRegzyG} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryLoRegG.tex}} - -\newcommand{\sailupdateTLBEntryLoRegG}{\label{zzyupdatezyTLBEntryLoRegzyG} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryLoRegG.tex}} - -\newcommand{\sailfnupdateTLBEntryLoRegG}{\label{zzyupdatezyTLBEntryLoRegzyG} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryLoRegG.tex}} - -\newcommand{\sailsailupdateGv}{\label{zupdatezyG} \lstinputlisting[language=sail]{sail_latex/sailsailupdateGv.tex}} - -\newcommand{\sailsailmodGv}{\label{zzymodzyG} \lstinputlisting[language=sail]{sail_latex/sailsailmodGv.tex}} - -\newcommand{\sailTLBEntryHiReg}{\label{zTLBEntryHiReg} \lstinputlisting[language=sail]{sail_latex/sailTLBEntryHiReg.tex}} - -\newcommand{\sailMkTLBEntryHiReg}{\label{zMkzyTLBEntryHiReg} \lstinputlisting[language=sail]{sail_latex/sailMkTLBEntryHiReg.tex}} - -\newcommand{\sailfnMkTLBEntryHiReg}{\label{zMkzyTLBEntryHiReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkTLBEntryHiReg.tex}} - -\newcommand{\sailgetTLBEntryHiRegbits}{\label{zzygetzyTLBEntryHiRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryHiRegbits.tex}} - -\newcommand{\sailfngetTLBEntryHiRegbits}{\label{zzygetzyTLBEntryHiRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryHiRegbits.tex}} - -\newcommand{\sailsetTLBEntryHiRegbits}{\label{zzysetzyTLBEntryHiRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryHiRegbits.tex}} - -\newcommand{\sailfnsetTLBEntryHiRegbits}{\label{zzysetzyTLBEntryHiRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryHiRegbits.tex}} - -\newcommand{\sailupdateTLBEntryHiRegbits}{\label{zzyupdatezyTLBEntryHiRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryHiRegbits.tex}} - -\newcommand{\sailfnupdateTLBEntryHiRegbits}{\label{zzyupdatezyTLBEntryHiRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryHiRegbits.tex}} - -\newcommand{\sailsailsailsailsailsailupdatebitsvvvvv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailupdatebitsvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailmodbitsvvvvv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailmodbitsvvvvv.tex}} - -\newcommand{\sailgetTLBEntryHiRegR}{\label{zzygetzyTLBEntryHiRegzyR} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryHiRegR.tex}} - -\newcommand{\sailfngetTLBEntryHiRegR}{\label{zzygetzyTLBEntryHiRegzyR} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryHiRegR.tex}} - -\newcommand{\sailsetTLBEntryHiRegR}{\label{zzysetzyTLBEntryHiRegzyR} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryHiRegR.tex}} - -\newcommand{\sailfnsetTLBEntryHiRegR}{\label{zzysetzyTLBEntryHiRegzyR} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryHiRegR.tex}} - -\newcommand{\sailupdateTLBEntryHiRegR}{\label{zzyupdatezyTLBEntryHiRegzyR} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryHiRegR.tex}} - -\newcommand{\sailfnupdateTLBEntryHiRegR}{\label{zzyupdatezyTLBEntryHiRegzyR} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryHiRegR.tex}} - -\newcommand{\sailsailupdateRv}{\label{zupdatezyR} \lstinputlisting[language=sail]{sail_latex/sailsailupdateRv.tex}} - -\newcommand{\sailsailmodRv}{\label{zzymodzyR} \lstinputlisting[language=sail]{sail_latex/sailsailmodRv.tex}} - -\newcommand{\sailgetTLBEntryHiRegVPNtwo}{\label{zzygetzyTLBEntryHiRegzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryHiRegVPNtwo.tex}} - -\newcommand{\sailfngetTLBEntryHiRegVPNtwo}{\label{zzygetzyTLBEntryHiRegzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryHiRegVPNtwo.tex}} - -\newcommand{\sailsetTLBEntryHiRegVPNtwo}{\label{zzysetzyTLBEntryHiRegzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryHiRegVPNtwo.tex}} - -\newcommand{\sailfnsetTLBEntryHiRegVPNtwo}{\label{zzysetzyTLBEntryHiRegzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryHiRegVPNtwo.tex}} - -\newcommand{\sailupdateTLBEntryHiRegVPNtwo}{\label{zzyupdatezyTLBEntryHiRegzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryHiRegVPNtwo.tex}} - -\newcommand{\sailfnupdateTLBEntryHiRegVPNtwo}{\label{zzyupdatezyTLBEntryHiRegzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryHiRegVPNtwo.tex}} - -\newcommand{\sailsailupdateVPNtwov}{\label{zupdatezyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailsailupdateVPNtwov.tex}} - -\newcommand{\sailsailmodVPNtwov}{\label{zzymodzyVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailsailmodVPNtwov.tex}} - -\newcommand{\sailgetTLBEntryHiRegASID}{\label{zzygetzyTLBEntryHiRegzyASID} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryHiRegASID.tex}} - -\newcommand{\sailfngetTLBEntryHiRegASID}{\label{zzygetzyTLBEntryHiRegzyASID} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryHiRegASID.tex}} - -\newcommand{\sailsetTLBEntryHiRegASID}{\label{zzysetzyTLBEntryHiRegzyASID} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryHiRegASID.tex}} - -\newcommand{\sailfnsetTLBEntryHiRegASID}{\label{zzysetzyTLBEntryHiRegzyASID} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryHiRegASID.tex}} - -\newcommand{\sailupdateTLBEntryHiRegASID}{\label{zzyupdatezyTLBEntryHiRegzyASID} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryHiRegASID.tex}} - -\newcommand{\sailfnupdateTLBEntryHiRegASID}{\label{zzyupdatezyTLBEntryHiRegzyASID} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryHiRegASID.tex}} - -\newcommand{\sailsailupdateASIDv}{\label{zupdatezyASID} \lstinputlisting[language=sail]{sail_latex/sailsailupdateASIDv.tex}} - -\newcommand{\sailsailmodASIDv}{\label{zzymodzyASID} \lstinputlisting[language=sail]{sail_latex/sailsailmodASIDv.tex}} - -\newcommand{\sailContextReg}{\label{zContextReg} \lstinputlisting[language=sail]{sail_latex/sailContextReg.tex}} - -\newcommand{\sailMkContextReg}{\label{zMkzyContextReg} \lstinputlisting[language=sail]{sail_latex/sailMkContextReg.tex}} - -\newcommand{\sailfnMkContextReg}{\label{zMkzyContextReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkContextReg.tex}} - -\newcommand{\sailgetContextRegbits}{\label{zzygetzyContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetContextRegbits.tex}} - -\newcommand{\sailfngetContextRegbits}{\label{zzygetzyContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetContextRegbits.tex}} - -\newcommand{\sailsetContextRegbits}{\label{zzysetzyContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetContextRegbits.tex}} - -\newcommand{\sailfnsetContextRegbits}{\label{zzysetzyContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetContextRegbits.tex}} - -\newcommand{\sailupdateContextRegbits}{\label{zzyupdatezyContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateContextRegbits.tex}} - -\newcommand{\sailfnupdateContextRegbits}{\label{zzyupdatezyContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateContextRegbits.tex}} - -\newcommand{\sailsailsailsailsailupdatebitsvvvv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailupdatebitsvvvv.tex}} - -\newcommand{\sailsailsailsailsailmodbitsvvvv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailmodbitsvvvv.tex}} - -\newcommand{\sailgetContextRegPTEBase}{\label{zzygetzyContextRegzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailgetContextRegPTEBase.tex}} - -\newcommand{\sailfngetContextRegPTEBase}{\label{zzygetzyContextRegzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailfngetContextRegPTEBase.tex}} - -\newcommand{\sailsetContextRegPTEBase}{\label{zzysetzyContextRegzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailsetContextRegPTEBase.tex}} - -\newcommand{\sailfnsetContextRegPTEBase}{\label{zzysetzyContextRegzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailfnsetContextRegPTEBase.tex}} - -\newcommand{\sailupdateContextRegPTEBase}{\label{zzyupdatezyContextRegzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailupdateContextRegPTEBase.tex}} - -\newcommand{\sailfnupdateContextRegPTEBase}{\label{zzyupdatezyContextRegzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailfnupdateContextRegPTEBase.tex}} - -\newcommand{\sailupdatePTEBase}{\label{zupdatezyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailupdatePTEBase.tex}} - -\newcommand{\sailmodPTEBase}{\label{zzymodzyPTEBase} \lstinputlisting[language=sail]{sail_latex/sailmodPTEBase.tex}} - -\newcommand{\sailgetContextRegBadVPNtwo}{\label{zzygetzyContextRegzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailgetContextRegBadVPNtwo.tex}} - -\newcommand{\sailfngetContextRegBadVPNtwo}{\label{zzygetzyContextRegzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfngetContextRegBadVPNtwo.tex}} - -\newcommand{\sailsetContextRegBadVPNtwo}{\label{zzysetzyContextRegzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailsetContextRegBadVPNtwo.tex}} - -\newcommand{\sailfnsetContextRegBadVPNtwo}{\label{zzysetzyContextRegzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfnsetContextRegBadVPNtwo.tex}} - -\newcommand{\sailupdateContextRegBadVPNtwo}{\label{zzyupdatezyContextRegzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailupdateContextRegBadVPNtwo.tex}} - -\newcommand{\sailfnupdateContextRegBadVPNtwo}{\label{zzyupdatezyContextRegzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfnupdateContextRegBadVPNtwo.tex}} - -\newcommand{\sailupdateBadVPNtwo}{\label{zupdatezyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailupdateBadVPNtwo.tex}} - -\newcommand{\sailmodBadVPNtwo}{\label{zzymodzyBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailmodBadVPNtwo.tex}} - -\newcommand{\sailXContextReg}{\label{zXContextReg} \lstinputlisting[language=sail]{sail_latex/sailXContextReg.tex}} - -\newcommand{\sailMkXContextReg}{\label{zMkzyXContextReg} \lstinputlisting[language=sail]{sail_latex/sailMkXContextReg.tex}} - -\newcommand{\sailfnMkXContextReg}{\label{zMkzyXContextReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkXContextReg.tex}} - -\newcommand{\sailgetXContextRegbits}{\label{zzygetzyXContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetXContextRegbits.tex}} - -\newcommand{\sailfngetXContextRegbits}{\label{zzygetzyXContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetXContextRegbits.tex}} - -\newcommand{\sailsetXContextRegbits}{\label{zzysetzyXContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetXContextRegbits.tex}} - -\newcommand{\sailfnsetXContextRegbits}{\label{zzysetzyXContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetXContextRegbits.tex}} - -\newcommand{\sailupdateXContextRegbits}{\label{zzyupdatezyXContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateXContextRegbits.tex}} - -\newcommand{\sailfnupdateXContextRegbits}{\label{zzyupdatezyXContextRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateXContextRegbits.tex}} - -\newcommand{\sailsailsailsailupdatebitsvvv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailupdatebitsvvv.tex}} - -\newcommand{\sailsailsailsailmodbitsvvv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailsailmodbitsvvv.tex}} - -\newcommand{\sailgetXContextRegXPTEBase}{\label{zzygetzyXContextRegzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailgetXContextRegXPTEBase.tex}} - -\newcommand{\sailfngetXContextRegXPTEBase}{\label{zzygetzyXContextRegzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailfngetXContextRegXPTEBase.tex}} - -\newcommand{\sailsetXContextRegXPTEBase}{\label{zzysetzyXContextRegzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailsetXContextRegXPTEBase.tex}} - -\newcommand{\sailfnsetXContextRegXPTEBase}{\label{zzysetzyXContextRegzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailfnsetXContextRegXPTEBase.tex}} - -\newcommand{\sailupdateXContextRegXPTEBase}{\label{zzyupdatezyXContextRegzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailupdateXContextRegXPTEBase.tex}} - -\newcommand{\sailfnupdateXContextRegXPTEBase}{\label{zzyupdatezyXContextRegzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailfnupdateXContextRegXPTEBase.tex}} - -\newcommand{\sailupdateXPTEBase}{\label{zupdatezyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailupdateXPTEBase.tex}} - -\newcommand{\sailmodXPTEBase}{\label{zzymodzyXPTEBase} \lstinputlisting[language=sail]{sail_latex/sailmodXPTEBase.tex}} - -\newcommand{\sailgetXContextRegXR}{\label{zzygetzyXContextRegzyXR} \lstinputlisting[language=sail]{sail_latex/sailgetXContextRegXR.tex}} - -\newcommand{\sailfngetXContextRegXR}{\label{zzygetzyXContextRegzyXR} \lstinputlisting[language=sail]{sail_latex/sailfngetXContextRegXR.tex}} - -\newcommand{\sailsetXContextRegXR}{\label{zzysetzyXContextRegzyXR} \lstinputlisting[language=sail]{sail_latex/sailsetXContextRegXR.tex}} - -\newcommand{\sailfnsetXContextRegXR}{\label{zzysetzyXContextRegzyXR} \lstinputlisting[language=sail]{sail_latex/sailfnsetXContextRegXR.tex}} - -\newcommand{\sailupdateXContextRegXR}{\label{zzyupdatezyXContextRegzyXR} \lstinputlisting[language=sail]{sail_latex/sailupdateXContextRegXR.tex}} - -\newcommand{\sailfnupdateXContextRegXR}{\label{zzyupdatezyXContextRegzyXR} \lstinputlisting[language=sail]{sail_latex/sailfnupdateXContextRegXR.tex}} - -\newcommand{\sailupdateXR}{\label{zupdatezyXR} \lstinputlisting[language=sail]{sail_latex/sailupdateXR.tex}} - -\newcommand{\sailmodXR}{\label{zzymodzyXR} \lstinputlisting[language=sail]{sail_latex/sailmodXR.tex}} - -\newcommand{\sailgetXContextRegXBadVPNtwo}{\label{zzygetzyXContextRegzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailgetXContextRegXBadVPNtwo.tex}} - -\newcommand{\sailfngetXContextRegXBadVPNtwo}{\label{zzygetzyXContextRegzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfngetXContextRegXBadVPNtwo.tex}} - -\newcommand{\sailsetXContextRegXBadVPNtwo}{\label{zzysetzyXContextRegzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailsetXContextRegXBadVPNtwo.tex}} - -\newcommand{\sailfnsetXContextRegXBadVPNtwo}{\label{zzysetzyXContextRegzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfnsetXContextRegXBadVPNtwo.tex}} - -\newcommand{\sailupdateXContextRegXBadVPNtwo}{\label{zzyupdatezyXContextRegzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailupdateXContextRegXBadVPNtwo.tex}} - -\newcommand{\sailfnupdateXContextRegXBadVPNtwo}{\label{zzyupdatezyXContextRegzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailfnupdateXContextRegXBadVPNtwo.tex}} - -\newcommand{\sailupdateXBadVPNtwo}{\label{zupdatezyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailupdateXBadVPNtwo.tex}} - -\newcommand{\sailmodXBadVPNtwo}{\label{zzymodzyXBadVPNtwo} \lstinputlisting[language=sail]{sail_latex/sailmodXBadVPNtwo.tex}} - -\newcommand{\sailTLBIndexT}{\label{zTLBIndexT} \lstinputlisting[language=sail]{sail_latex/sailTLBIndexT.tex}} - -\newcommand{\sailMAX}{\label{zMAX} \lstinputlisting[language=sail]{sail_latex/sailMAX.tex}} - -\newcommand{\sailfnMAX}{\label{zMAX} \lstinputlisting[language=sail]{sail_latex/sailfnMAX.tex}} - -\newcommand{\sailTLBEntry}{\label{zTLBEntry} \lstinputlisting[language=sail]{sail_latex/sailTLBEntry.tex}} - -\newcommand{\sailMkTLBEntry}{\label{zMkzyTLBEntry} \lstinputlisting[language=sail]{sail_latex/sailMkTLBEntry.tex}} - -\newcommand{\sailfnMkTLBEntry}{\label{zMkzyTLBEntry} \lstinputlisting[language=sail]{sail_latex/sailfnMkTLBEntry.tex}} - -\newcommand{\sailgetTLBEntrybits}{\label{zzygetzyTLBEntryzybits} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrybits.tex}} - -\newcommand{\sailfngetTLBEntrybits}{\label{zzygetzyTLBEntryzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrybits.tex}} - -\newcommand{\sailsetTLBEntrybits}{\label{zzysetzyTLBEntryzybits} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrybits.tex}} - -\newcommand{\sailfnsetTLBEntrybits}{\label{zzysetzyTLBEntryzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrybits.tex}} - -\newcommand{\sailupdateTLBEntrybits}{\label{zzyupdatezyTLBEntryzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrybits.tex}} - -\newcommand{\sailfnupdateTLBEntrybits}{\label{zzyupdatezyTLBEntryzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrybits.tex}} - -\newcommand{\sailsailsailupdatebitsvv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailupdatebitsvv.tex}} - -\newcommand{\sailsailsailmodbitsvv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailsailmodbitsvv.tex}} - -\newcommand{\sailgetTLBEntrypagemask}{\label{zzygetzyTLBEntryzypagemask} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrypagemask.tex}} - -\newcommand{\sailfngetTLBEntrypagemask}{\label{zzygetzyTLBEntryzypagemask} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrypagemask.tex}} - -\newcommand{\sailsetTLBEntrypagemask}{\label{zzysetzyTLBEntryzypagemask} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrypagemask.tex}} - -\newcommand{\sailfnsetTLBEntrypagemask}{\label{zzysetzyTLBEntryzypagemask} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrypagemask.tex}} - -\newcommand{\sailupdateTLBEntrypagemask}{\label{zzyupdatezyTLBEntryzypagemask} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrypagemask.tex}} - -\newcommand{\sailfnupdateTLBEntrypagemask}{\label{zzyupdatezyTLBEntryzypagemask} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrypagemask.tex}} - -\newcommand{\sailupdatepagemask}{\label{zupdatezypagemask} \lstinputlisting[language=sail]{sail_latex/sailupdatepagemask.tex}} - -\newcommand{\sailmodpagemask}{\label{zzymodzypagemask} \lstinputlisting[language=sail]{sail_latex/sailmodpagemask.tex}} - -\newcommand{\sailgetTLBEntryr}{\label{zzygetzyTLBEntryzyr} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryr.tex}} - -\newcommand{\sailfngetTLBEntryr}{\label{zzygetzyTLBEntryzyr} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryr.tex}} - -\newcommand{\sailsetTLBEntryr}{\label{zzysetzyTLBEntryzyr} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryr.tex}} - -\newcommand{\sailfnsetTLBEntryr}{\label{zzysetzyTLBEntryzyr} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryr.tex}} - -\newcommand{\sailupdateTLBEntryr}{\label{zzyupdatezyTLBEntryzyr} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryr.tex}} - -\newcommand{\sailfnupdateTLBEntryr}{\label{zzyupdatezyTLBEntryzyr} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryr.tex}} - -\newcommand{\sailupdater}{\label{zupdatezyr} \lstinputlisting[language=sail]{sail_latex/sailupdater.tex}} - -\newcommand{\sailmodr}{\label{zzymodzyr} \lstinputlisting[language=sail]{sail_latex/sailmodr.tex}} - -\newcommand{\sailgetTLBEntryvpntwo}{\label{zzygetzyTLBEntryzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryvpntwo.tex}} - -\newcommand{\sailfngetTLBEntryvpntwo}{\label{zzygetzyTLBEntryzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryvpntwo.tex}} - -\newcommand{\sailsetTLBEntryvpntwo}{\label{zzysetzyTLBEntryzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryvpntwo.tex}} - -\newcommand{\sailfnsetTLBEntryvpntwo}{\label{zzysetzyTLBEntryzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryvpntwo.tex}} - -\newcommand{\sailupdateTLBEntryvpntwo}{\label{zzyupdatezyTLBEntryzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryvpntwo.tex}} - -\newcommand{\sailfnupdateTLBEntryvpntwo}{\label{zzyupdatezyTLBEntryzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryvpntwo.tex}} - -\newcommand{\sailupdatevpntwo}{\label{zupdatezyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailupdatevpntwo.tex}} - -\newcommand{\sailmodvpntwo}{\label{zzymodzyvpntwo} \lstinputlisting[language=sail]{sail_latex/sailmodvpntwo.tex}} - -\newcommand{\sailgetTLBEntryasid}{\label{zzygetzyTLBEntryzyasid} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryasid.tex}} - -\newcommand{\sailfngetTLBEntryasid}{\label{zzygetzyTLBEntryzyasid} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryasid.tex}} - -\newcommand{\sailsetTLBEntryasid}{\label{zzysetzyTLBEntryzyasid} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryasid.tex}} - -\newcommand{\sailfnsetTLBEntryasid}{\label{zzysetzyTLBEntryzyasid} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryasid.tex}} - -\newcommand{\sailupdateTLBEntryasid}{\label{zzyupdatezyTLBEntryzyasid} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryasid.tex}} - -\newcommand{\sailfnupdateTLBEntryasid}{\label{zzyupdatezyTLBEntryzyasid} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryasid.tex}} - -\newcommand{\sailupdateasid}{\label{zupdatezyasid} \lstinputlisting[language=sail]{sail_latex/sailupdateasid.tex}} - -\newcommand{\sailmodasid}{\label{zzymodzyasid} \lstinputlisting[language=sail]{sail_latex/sailmodasid.tex}} - -\newcommand{\sailgetTLBEntryg}{\label{zzygetzyTLBEntryzyg} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryg.tex}} - -\newcommand{\sailfngetTLBEntryg}{\label{zzygetzyTLBEntryzyg} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryg.tex}} - -\newcommand{\sailsetTLBEntryg}{\label{zzysetzyTLBEntryzyg} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryg.tex}} - -\newcommand{\sailfnsetTLBEntryg}{\label{zzysetzyTLBEntryzyg} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryg.tex}} - -\newcommand{\sailupdateTLBEntryg}{\label{zzyupdatezyTLBEntryzyg} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryg.tex}} - -\newcommand{\sailfnupdateTLBEntryg}{\label{zzyupdatezyTLBEntryzyg} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryg.tex}} - -\newcommand{\sailupdateg}{\label{zupdatezyg} \lstinputlisting[language=sail]{sail_latex/sailupdateg.tex}} - -\newcommand{\sailmodg}{\label{zzymodzyg} \lstinputlisting[language=sail]{sail_latex/sailmodg.tex}} - -\newcommand{\sailgetTLBEntryvalid}{\label{zzygetzyTLBEntryzyvalid} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryvalid.tex}} - -\newcommand{\sailfngetTLBEntryvalid}{\label{zzygetzyTLBEntryzyvalid} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryvalid.tex}} - -\newcommand{\sailsetTLBEntryvalid}{\label{zzysetzyTLBEntryzyvalid} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryvalid.tex}} - -\newcommand{\sailfnsetTLBEntryvalid}{\label{zzysetzyTLBEntryzyvalid} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryvalid.tex}} - -\newcommand{\sailupdateTLBEntryvalid}{\label{zzyupdatezyTLBEntryzyvalid} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryvalid.tex}} - -\newcommand{\sailfnupdateTLBEntryvalid}{\label{zzyupdatezyTLBEntryzyvalid} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryvalid.tex}} - -\newcommand{\sailupdatevalid}{\label{zupdatezyvalid} \lstinputlisting[language=sail]{sail_latex/sailupdatevalid.tex}} - -\newcommand{\sailmodvalid}{\label{zzymodzyvalid} \lstinputlisting[language=sail]{sail_latex/sailmodvalid.tex}} - -\newcommand{\sailgetTLBEntrycapsone}{\label{zzygetzyTLBEntryzycapsone} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrycapsone.tex}} - -\newcommand{\sailfngetTLBEntrycapsone}{\label{zzygetzyTLBEntryzycapsone} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrycapsone.tex}} - -\newcommand{\sailsetTLBEntrycapsone}{\label{zzysetzyTLBEntryzycapsone} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrycapsone.tex}} - -\newcommand{\sailfnsetTLBEntrycapsone}{\label{zzysetzyTLBEntryzycapsone} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrycapsone.tex}} - -\newcommand{\sailupdateTLBEntrycapsone}{\label{zzyupdatezyTLBEntryzycapsone} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrycapsone.tex}} - -\newcommand{\sailfnupdateTLBEntrycapsone}{\label{zzyupdatezyTLBEntryzycapsone} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrycapsone.tex}} - -\newcommand{\sailupdatecapsone}{\label{zupdatezycapsone} \lstinputlisting[language=sail]{sail_latex/sailupdatecapsone.tex}} - -\newcommand{\sailmodcapsone}{\label{zzymodzycapsone} \lstinputlisting[language=sail]{sail_latex/sailmodcapsone.tex}} - -\newcommand{\sailgetTLBEntrycaplone}{\label{zzygetzyTLBEntryzycaplone} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrycaplone.tex}} - -\newcommand{\sailfngetTLBEntrycaplone}{\label{zzygetzyTLBEntryzycaplone} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrycaplone.tex}} - -\newcommand{\sailsetTLBEntrycaplone}{\label{zzysetzyTLBEntryzycaplone} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrycaplone.tex}} - -\newcommand{\sailfnsetTLBEntrycaplone}{\label{zzysetzyTLBEntryzycaplone} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrycaplone.tex}} - -\newcommand{\sailupdateTLBEntrycaplone}{\label{zzyupdatezyTLBEntryzycaplone} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrycaplone.tex}} - -\newcommand{\sailfnupdateTLBEntrycaplone}{\label{zzyupdatezyTLBEntryzycaplone} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrycaplone.tex}} - -\newcommand{\sailupdatecaplone}{\label{zupdatezycaplone} \lstinputlisting[language=sail]{sail_latex/sailupdatecaplone.tex}} - -\newcommand{\sailmodcaplone}{\label{zzymodzycaplone} \lstinputlisting[language=sail]{sail_latex/sailmodcaplone.tex}} - -\newcommand{\sailgetTLBEntrypfnone}{\label{zzygetzyTLBEntryzypfnone} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrypfnone.tex}} - -\newcommand{\sailfngetTLBEntrypfnone}{\label{zzygetzyTLBEntryzypfnone} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrypfnone.tex}} - -\newcommand{\sailsetTLBEntrypfnone}{\label{zzysetzyTLBEntryzypfnone} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrypfnone.tex}} - -\newcommand{\sailfnsetTLBEntrypfnone}{\label{zzysetzyTLBEntryzypfnone} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrypfnone.tex}} - -\newcommand{\sailupdateTLBEntrypfnone}{\label{zzyupdatezyTLBEntryzypfnone} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrypfnone.tex}} - -\newcommand{\sailfnupdateTLBEntrypfnone}{\label{zzyupdatezyTLBEntryzypfnone} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrypfnone.tex}} - -\newcommand{\sailupdatepfnone}{\label{zupdatezypfnone} \lstinputlisting[language=sail]{sail_latex/sailupdatepfnone.tex}} - -\newcommand{\sailmodpfnone}{\label{zzymodzypfnone} \lstinputlisting[language=sail]{sail_latex/sailmodpfnone.tex}} - -\newcommand{\sailgetTLBEntrycone}{\label{zzygetzyTLBEntryzycone} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrycone.tex}} - -\newcommand{\sailfngetTLBEntrycone}{\label{zzygetzyTLBEntryzycone} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrycone.tex}} - -\newcommand{\sailsetTLBEntrycone}{\label{zzysetzyTLBEntryzycone} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrycone.tex}} - -\newcommand{\sailfnsetTLBEntrycone}{\label{zzysetzyTLBEntryzycone} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrycone.tex}} - -\newcommand{\sailupdateTLBEntrycone}{\label{zzyupdatezyTLBEntryzycone} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrycone.tex}} - -\newcommand{\sailfnupdateTLBEntrycone}{\label{zzyupdatezyTLBEntryzycone} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrycone.tex}} - -\newcommand{\sailupdatecone}{\label{zupdatezycone} \lstinputlisting[language=sail]{sail_latex/sailupdatecone.tex}} - -\newcommand{\sailmodcone}{\label{zzymodzycone} \lstinputlisting[language=sail]{sail_latex/sailmodcone.tex}} - -\newcommand{\sailgetTLBEntrydone}{\label{zzygetzyTLBEntryzydone} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrydone.tex}} - -\newcommand{\sailfngetTLBEntrydone}{\label{zzygetzyTLBEntryzydone} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrydone.tex}} - -\newcommand{\sailsetTLBEntrydone}{\label{zzysetzyTLBEntryzydone} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrydone.tex}} - -\newcommand{\sailfnsetTLBEntrydone}{\label{zzysetzyTLBEntryzydone} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrydone.tex}} - -\newcommand{\sailupdateTLBEntrydone}{\label{zzyupdatezyTLBEntryzydone} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrydone.tex}} - -\newcommand{\sailfnupdateTLBEntrydone}{\label{zzyupdatezyTLBEntryzydone} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrydone.tex}} - -\newcommand{\sailupdatedone}{\label{zupdatezydone} \lstinputlisting[language=sail]{sail_latex/sailupdatedone.tex}} - -\newcommand{\sailmoddone}{\label{zzymodzydone} \lstinputlisting[language=sail]{sail_latex/sailmoddone.tex}} - -\newcommand{\sailgetTLBEntryvone}{\label{zzygetzyTLBEntryzyvone} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryvone.tex}} - -\newcommand{\sailfngetTLBEntryvone}{\label{zzygetzyTLBEntryzyvone} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryvone.tex}} - -\newcommand{\sailsetTLBEntryvone}{\label{zzysetzyTLBEntryzyvone} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryvone.tex}} - -\newcommand{\sailfnsetTLBEntryvone}{\label{zzysetzyTLBEntryzyvone} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryvone.tex}} - -\newcommand{\sailupdateTLBEntryvone}{\label{zzyupdatezyTLBEntryzyvone} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryvone.tex}} - -\newcommand{\sailfnupdateTLBEntryvone}{\label{zzyupdatezyTLBEntryzyvone} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryvone.tex}} - -\newcommand{\sailupdatevone}{\label{zupdatezyvone} \lstinputlisting[language=sail]{sail_latex/sailupdatevone.tex}} - -\newcommand{\sailmodvone}{\label{zzymodzyvone} \lstinputlisting[language=sail]{sail_latex/sailmodvone.tex}} - -\newcommand{\sailgetTLBEntrycapszero}{\label{zzygetzyTLBEntryzycapszero} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrycapszero.tex}} - -\newcommand{\sailfngetTLBEntrycapszero}{\label{zzygetzyTLBEntryzycapszero} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrycapszero.tex}} - -\newcommand{\sailsetTLBEntrycapszero}{\label{zzysetzyTLBEntryzycapszero} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrycapszero.tex}} - -\newcommand{\sailfnsetTLBEntrycapszero}{\label{zzysetzyTLBEntryzycapszero} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrycapszero.tex}} - -\newcommand{\sailupdateTLBEntrycapszero}{\label{zzyupdatezyTLBEntryzycapszero} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrycapszero.tex}} - -\newcommand{\sailfnupdateTLBEntrycapszero}{\label{zzyupdatezyTLBEntryzycapszero} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrycapszero.tex}} - -\newcommand{\sailupdatecapszero}{\label{zupdatezycapszero} \lstinputlisting[language=sail]{sail_latex/sailupdatecapszero.tex}} - -\newcommand{\sailmodcapszero}{\label{zzymodzycapszero} \lstinputlisting[language=sail]{sail_latex/sailmodcapszero.tex}} - -\newcommand{\sailgetTLBEntrycaplzero}{\label{zzygetzyTLBEntryzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrycaplzero.tex}} - -\newcommand{\sailfngetTLBEntrycaplzero}{\label{zzygetzyTLBEntryzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrycaplzero.tex}} - -\newcommand{\sailsetTLBEntrycaplzero}{\label{zzysetzyTLBEntryzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrycaplzero.tex}} - -\newcommand{\sailfnsetTLBEntrycaplzero}{\label{zzysetzyTLBEntryzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrycaplzero.tex}} - -\newcommand{\sailupdateTLBEntrycaplzero}{\label{zzyupdatezyTLBEntryzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrycaplzero.tex}} - -\newcommand{\sailfnupdateTLBEntrycaplzero}{\label{zzyupdatezyTLBEntryzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrycaplzero.tex}} - -\newcommand{\sailupdatecaplzero}{\label{zupdatezycaplzero} \lstinputlisting[language=sail]{sail_latex/sailupdatecaplzero.tex}} - -\newcommand{\sailmodcaplzero}{\label{zzymodzycaplzero} \lstinputlisting[language=sail]{sail_latex/sailmodcaplzero.tex}} - -\newcommand{\sailgetTLBEntrypfnzero}{\label{zzygetzyTLBEntryzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrypfnzero.tex}} - -\newcommand{\sailfngetTLBEntrypfnzero}{\label{zzygetzyTLBEntryzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrypfnzero.tex}} - -\newcommand{\sailsetTLBEntrypfnzero}{\label{zzysetzyTLBEntryzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrypfnzero.tex}} - -\newcommand{\sailfnsetTLBEntrypfnzero}{\label{zzysetzyTLBEntryzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrypfnzero.tex}} - -\newcommand{\sailupdateTLBEntrypfnzero}{\label{zzyupdatezyTLBEntryzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrypfnzero.tex}} - -\newcommand{\sailfnupdateTLBEntrypfnzero}{\label{zzyupdatezyTLBEntryzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrypfnzero.tex}} - -\newcommand{\sailupdatepfnzero}{\label{zupdatezypfnzero} \lstinputlisting[language=sail]{sail_latex/sailupdatepfnzero.tex}} - -\newcommand{\sailmodpfnzero}{\label{zzymodzypfnzero} \lstinputlisting[language=sail]{sail_latex/sailmodpfnzero.tex}} - -\newcommand{\sailgetTLBEntryczero}{\label{zzygetzyTLBEntryzyczero} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryczero.tex}} - -\newcommand{\sailfngetTLBEntryczero}{\label{zzygetzyTLBEntryzyczero} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryczero.tex}} - -\newcommand{\sailsetTLBEntryczero}{\label{zzysetzyTLBEntryzyczero} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryczero.tex}} - -\newcommand{\sailfnsetTLBEntryczero}{\label{zzysetzyTLBEntryzyczero} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryczero.tex}} - -\newcommand{\sailupdateTLBEntryczero}{\label{zzyupdatezyTLBEntryzyczero} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryczero.tex}} - -\newcommand{\sailfnupdateTLBEntryczero}{\label{zzyupdatezyTLBEntryzyczero} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryczero.tex}} - -\newcommand{\sailupdateczero}{\label{zupdatezyczero} \lstinputlisting[language=sail]{sail_latex/sailupdateczero.tex}} - -\newcommand{\sailmodczero}{\label{zzymodzyczero} \lstinputlisting[language=sail]{sail_latex/sailmodczero.tex}} - -\newcommand{\sailgetTLBEntrydzero}{\label{zzygetzyTLBEntryzydzero} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntrydzero.tex}} - -\newcommand{\sailfngetTLBEntrydzero}{\label{zzygetzyTLBEntryzydzero} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntrydzero.tex}} - -\newcommand{\sailsetTLBEntrydzero}{\label{zzysetzyTLBEntryzydzero} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntrydzero.tex}} - -\newcommand{\sailfnsetTLBEntrydzero}{\label{zzysetzyTLBEntryzydzero} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntrydzero.tex}} - -\newcommand{\sailupdateTLBEntrydzero}{\label{zzyupdatezyTLBEntryzydzero} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntrydzero.tex}} - -\newcommand{\sailfnupdateTLBEntrydzero}{\label{zzyupdatezyTLBEntryzydzero} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntrydzero.tex}} - -\newcommand{\sailupdatedzero}{\label{zupdatezydzero} \lstinputlisting[language=sail]{sail_latex/sailupdatedzero.tex}} - -\newcommand{\sailmoddzero}{\label{zzymodzydzero} \lstinputlisting[language=sail]{sail_latex/sailmoddzero.tex}} - -\newcommand{\sailgetTLBEntryvzero}{\label{zzygetzyTLBEntryzyvzero} \lstinputlisting[language=sail]{sail_latex/sailgetTLBEntryvzero.tex}} - -\newcommand{\sailfngetTLBEntryvzero}{\label{zzygetzyTLBEntryzyvzero} \lstinputlisting[language=sail]{sail_latex/sailfngetTLBEntryvzero.tex}} - -\newcommand{\sailsetTLBEntryvzero}{\label{zzysetzyTLBEntryzyvzero} \lstinputlisting[language=sail]{sail_latex/sailsetTLBEntryvzero.tex}} - -\newcommand{\sailfnsetTLBEntryvzero}{\label{zzysetzyTLBEntryzyvzero} \lstinputlisting[language=sail]{sail_latex/sailfnsetTLBEntryvzero.tex}} - -\newcommand{\sailupdateTLBEntryvzero}{\label{zzyupdatezyTLBEntryzyvzero} \lstinputlisting[language=sail]{sail_latex/sailupdateTLBEntryvzero.tex}} - -\newcommand{\sailfnupdateTLBEntryvzero}{\label{zzyupdatezyTLBEntryzyvzero} \lstinputlisting[language=sail]{sail_latex/sailfnupdateTLBEntryvzero.tex}} - -\newcommand{\sailupdatevzero}{\label{zupdatezyvzero} \lstinputlisting[language=sail]{sail_latex/sailupdatevzero.tex}} - -\newcommand{\sailmodvzero}{\label{zzymodzyvzero} \lstinputlisting[language=sail]{sail_latex/sailmodvzero.tex}} - -\newcommand{\sailStatusReg}{\label{zStatusReg} \lstinputlisting[language=sail]{sail_latex/sailStatusReg.tex}} - -\newcommand{\sailMkStatusReg}{\label{zMkzyStatusReg} \lstinputlisting[language=sail]{sail_latex/sailMkStatusReg.tex}} - -\newcommand{\sailfnMkStatusReg}{\label{zMkzyStatusReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkStatusReg.tex}} - -\newcommand{\sailgetStatusRegbits}{\label{zzygetzyStatusRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegbits.tex}} - -\newcommand{\sailfngetStatusRegbits}{\label{zzygetzyStatusRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegbits.tex}} - -\newcommand{\sailsetStatusRegbits}{\label{zzysetzyStatusRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegbits.tex}} - -\newcommand{\sailfnsetStatusRegbits}{\label{zzysetzyStatusRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegbits.tex}} - -\newcommand{\sailupdateStatusRegbits}{\label{zzyupdatezyStatusRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegbits.tex}} - -\newcommand{\sailfnupdateStatusRegbits}{\label{zzyupdatezyStatusRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegbits.tex}} - -\newcommand{\sailsailupdatebitsv}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailsailupdatebitsv.tex}} - -\newcommand{\sailsailmodbitsv}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailsailmodbitsv.tex}} - -\newcommand{\sailgetStatusRegCU}{\label{zzygetzyStatusRegzyCU} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegCU.tex}} - -\newcommand{\sailfngetStatusRegCU}{\label{zzygetzyStatusRegzyCU} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegCU.tex}} - -\newcommand{\sailsetStatusRegCU}{\label{zzysetzyStatusRegzyCU} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegCU.tex}} - -\newcommand{\sailfnsetStatusRegCU}{\label{zzysetzyStatusRegzyCU} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegCU.tex}} - -\newcommand{\sailupdateStatusRegCU}{\label{zzyupdatezyStatusRegzyCU} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegCU.tex}} - -\newcommand{\sailfnupdateStatusRegCU}{\label{zzyupdatezyStatusRegzyCU} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegCU.tex}} - -\newcommand{\sailupdateCU}{\label{zupdatezyCU} \lstinputlisting[language=sail]{sail_latex/sailupdateCU.tex}} - -\newcommand{\sailmodCU}{\label{zzymodzyCU} \lstinputlisting[language=sail]{sail_latex/sailmodCU.tex}} - -\newcommand{\sailgetStatusRegBEV}{\label{zzygetzyStatusRegzyBEV} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegBEV.tex}} - -\newcommand{\sailfngetStatusRegBEV}{\label{zzygetzyStatusRegzyBEV} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegBEV.tex}} - -\newcommand{\sailsetStatusRegBEV}{\label{zzysetzyStatusRegzyBEV} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegBEV.tex}} - -\newcommand{\sailfnsetStatusRegBEV}{\label{zzysetzyStatusRegzyBEV} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegBEV.tex}} - -\newcommand{\sailupdateStatusRegBEV}{\label{zzyupdatezyStatusRegzyBEV} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegBEV.tex}} - -\newcommand{\sailfnupdateStatusRegBEV}{\label{zzyupdatezyStatusRegzyBEV} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegBEV.tex}} - -\newcommand{\sailupdateBEV}{\label{zupdatezyBEV} \lstinputlisting[language=sail]{sail_latex/sailupdateBEV.tex}} - -\newcommand{\sailmodBEV}{\label{zzymodzyBEV} \lstinputlisting[language=sail]{sail_latex/sailmodBEV.tex}} - -\newcommand{\sailgetStatusRegIM}{\label{zzygetzyStatusRegzyIM} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegIM.tex}} - -\newcommand{\sailfngetStatusRegIM}{\label{zzygetzyStatusRegzyIM} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegIM.tex}} - -\newcommand{\sailsetStatusRegIM}{\label{zzysetzyStatusRegzyIM} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegIM.tex}} - -\newcommand{\sailfnsetStatusRegIM}{\label{zzysetzyStatusRegzyIM} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegIM.tex}} - -\newcommand{\sailupdateStatusRegIM}{\label{zzyupdatezyStatusRegzyIM} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegIM.tex}} - -\newcommand{\sailfnupdateStatusRegIM}{\label{zzyupdatezyStatusRegzyIM} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegIM.tex}} - -\newcommand{\sailupdateIM}{\label{zupdatezyIM} \lstinputlisting[language=sail]{sail_latex/sailupdateIM.tex}} - -\newcommand{\sailmodIM}{\label{zzymodzyIM} \lstinputlisting[language=sail]{sail_latex/sailmodIM.tex}} - -\newcommand{\sailgetStatusRegKX}{\label{zzygetzyStatusRegzyKX} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegKX.tex}} - -\newcommand{\sailfngetStatusRegKX}{\label{zzygetzyStatusRegzyKX} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegKX.tex}} - -\newcommand{\sailsetStatusRegKX}{\label{zzysetzyStatusRegzyKX} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegKX.tex}} - -\newcommand{\sailfnsetStatusRegKX}{\label{zzysetzyStatusRegzyKX} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegKX.tex}} - -\newcommand{\sailupdateStatusRegKX}{\label{zzyupdatezyStatusRegzyKX} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegKX.tex}} - -\newcommand{\sailfnupdateStatusRegKX}{\label{zzyupdatezyStatusRegzyKX} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegKX.tex}} - -\newcommand{\sailupdateKX}{\label{zupdatezyKX} \lstinputlisting[language=sail]{sail_latex/sailupdateKX.tex}} - -\newcommand{\sailmodKX}{\label{zzymodzyKX} \lstinputlisting[language=sail]{sail_latex/sailmodKX.tex}} - -\newcommand{\sailgetStatusRegSX}{\label{zzygetzyStatusRegzySX} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegSX.tex}} - -\newcommand{\sailfngetStatusRegSX}{\label{zzygetzyStatusRegzySX} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegSX.tex}} - -\newcommand{\sailsetStatusRegSX}{\label{zzysetzyStatusRegzySX} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegSX.tex}} - -\newcommand{\sailfnsetStatusRegSX}{\label{zzysetzyStatusRegzySX} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegSX.tex}} - -\newcommand{\sailupdateStatusRegSX}{\label{zzyupdatezyStatusRegzySX} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegSX.tex}} - -\newcommand{\sailfnupdateStatusRegSX}{\label{zzyupdatezyStatusRegzySX} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegSX.tex}} - -\newcommand{\sailupdateSX}{\label{zupdatezySX} \lstinputlisting[language=sail]{sail_latex/sailupdateSX.tex}} - -\newcommand{\sailmodSX}{\label{zzymodzySX} \lstinputlisting[language=sail]{sail_latex/sailmodSX.tex}} - -\newcommand{\sailgetStatusRegUX}{\label{zzygetzyStatusRegzyUX} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegUX.tex}} - -\newcommand{\sailfngetStatusRegUX}{\label{zzygetzyStatusRegzyUX} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegUX.tex}} - -\newcommand{\sailsetStatusRegUX}{\label{zzysetzyStatusRegzyUX} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegUX.tex}} - -\newcommand{\sailfnsetStatusRegUX}{\label{zzysetzyStatusRegzyUX} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegUX.tex}} - -\newcommand{\sailupdateStatusRegUX}{\label{zzyupdatezyStatusRegzyUX} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegUX.tex}} - -\newcommand{\sailfnupdateStatusRegUX}{\label{zzyupdatezyStatusRegzyUX} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegUX.tex}} - -\newcommand{\sailupdateUX}{\label{zupdatezyUX} \lstinputlisting[language=sail]{sail_latex/sailupdateUX.tex}} - -\newcommand{\sailmodUX}{\label{zzymodzyUX} \lstinputlisting[language=sail]{sail_latex/sailmodUX.tex}} - -\newcommand{\sailgetStatusRegKSU}{\label{zzygetzyStatusRegzyKSU} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegKSU.tex}} - -\newcommand{\sailfngetStatusRegKSU}{\label{zzygetzyStatusRegzyKSU} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegKSU.tex}} - -\newcommand{\sailsetStatusRegKSU}{\label{zzysetzyStatusRegzyKSU} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegKSU.tex}} - -\newcommand{\sailfnsetStatusRegKSU}{\label{zzysetzyStatusRegzyKSU} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegKSU.tex}} - -\newcommand{\sailupdateStatusRegKSU}{\label{zzyupdatezyStatusRegzyKSU} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegKSU.tex}} - -\newcommand{\sailfnupdateStatusRegKSU}{\label{zzyupdatezyStatusRegzyKSU} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegKSU.tex}} - -\newcommand{\sailupdateKSU}{\label{zupdatezyKSU} \lstinputlisting[language=sail]{sail_latex/sailupdateKSU.tex}} - -\newcommand{\sailmodKSU}{\label{zzymodzyKSU} \lstinputlisting[language=sail]{sail_latex/sailmodKSU.tex}} - -\newcommand{\sailgetStatusRegERL}{\label{zzygetzyStatusRegzyERL} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegERL.tex}} - -\newcommand{\sailfngetStatusRegERL}{\label{zzygetzyStatusRegzyERL} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegERL.tex}} - -\newcommand{\sailsetStatusRegERL}{\label{zzysetzyStatusRegzyERL} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegERL.tex}} - -\newcommand{\sailfnsetStatusRegERL}{\label{zzysetzyStatusRegzyERL} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegERL.tex}} - -\newcommand{\sailupdateStatusRegERL}{\label{zzyupdatezyStatusRegzyERL} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegERL.tex}} - -\newcommand{\sailfnupdateStatusRegERL}{\label{zzyupdatezyStatusRegzyERL} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegERL.tex}} - -\newcommand{\sailupdateERL}{\label{zupdatezyERL} \lstinputlisting[language=sail]{sail_latex/sailupdateERL.tex}} - -\newcommand{\sailmodERL}{\label{zzymodzyERL} \lstinputlisting[language=sail]{sail_latex/sailmodERL.tex}} - -\newcommand{\sailgetStatusRegEXL}{\label{zzygetzyStatusRegzyEXL} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegEXL.tex}} - -\newcommand{\sailfngetStatusRegEXL}{\label{zzygetzyStatusRegzyEXL} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegEXL.tex}} - -\newcommand{\sailsetStatusRegEXL}{\label{zzysetzyStatusRegzyEXL} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegEXL.tex}} - -\newcommand{\sailfnsetStatusRegEXL}{\label{zzysetzyStatusRegzyEXL} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegEXL.tex}} - -\newcommand{\sailupdateStatusRegEXL}{\label{zzyupdatezyStatusRegzyEXL} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegEXL.tex}} - -\newcommand{\sailfnupdateStatusRegEXL}{\label{zzyupdatezyStatusRegzyEXL} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegEXL.tex}} - -\newcommand{\sailupdateEXL}{\label{zupdatezyEXL} \lstinputlisting[language=sail]{sail_latex/sailupdateEXL.tex}} - -\newcommand{\sailmodEXL}{\label{zzymodzyEXL} \lstinputlisting[language=sail]{sail_latex/sailmodEXL.tex}} - -\newcommand{\sailgetStatusRegIE}{\label{zzygetzyStatusRegzyIE} \lstinputlisting[language=sail]{sail_latex/sailgetStatusRegIE.tex}} - -\newcommand{\sailfngetStatusRegIE}{\label{zzygetzyStatusRegzyIE} \lstinputlisting[language=sail]{sail_latex/sailfngetStatusRegIE.tex}} - -\newcommand{\sailsetStatusRegIE}{\label{zzysetzyStatusRegzyIE} \lstinputlisting[language=sail]{sail_latex/sailsetStatusRegIE.tex}} - -\newcommand{\sailfnsetStatusRegIE}{\label{zzysetzyStatusRegzyIE} \lstinputlisting[language=sail]{sail_latex/sailfnsetStatusRegIE.tex}} - -\newcommand{\sailupdateStatusRegIE}{\label{zzyupdatezyStatusRegzyIE} \lstinputlisting[language=sail]{sail_latex/sailupdateStatusRegIE.tex}} - -\newcommand{\sailfnupdateStatusRegIE}{\label{zzyupdatezyStatusRegzyIE} \lstinputlisting[language=sail]{sail_latex/sailfnupdateStatusRegIE.tex}} - -\newcommand{\sailupdateIE}{\label{zupdatezyIE} \lstinputlisting[language=sail]{sail_latex/sailupdateIE.tex}} - -\newcommand{\sailmodIE}{\label{zzymodzyIE} \lstinputlisting[language=sail]{sail_latex/sailmodIE.tex}} - -\newcommand{\sailexecutebranch}{\label{zexecutezybranch} \lstinputlisting[language=sail]{sail_latex/sailexecutebranch.tex}} - -\newcommand{\sailfnexecutebranch}{\label{zexecutezybranch} \lstinputlisting[language=sail]{sail_latex/sailfnexecutebranch.tex}} - -\newcommand{\sailNotWordVal}{\label{zNotWordVal} \lstinputlisting[language=sail]{sail_latex/sailNotWordVal.tex}} - -\newcommand{\sailfnNotWordVal}{\label{zNotWordVal} \lstinputlisting[language=sail]{sail_latex/sailfnNotWordVal.tex}} - -\newcommand{\sailrGPR}{\label{zrGPR} \lstinputlisting[language=sail]{sail_latex/sailrGPR.tex}} - -\newcommand{\sailfnrGPR}{\label{zrGPR} \lstinputlisting[language=sail]{sail_latex/sailfnrGPR.tex}} - -\newcommand{\sailwGPR}{\label{zwGPR} \lstinputlisting[language=sail]{sail_latex/sailwGPR.tex}} - -\newcommand{\sailfnwGPR}{\label{zwGPR} \lstinputlisting[language=sail]{sail_latex/sailfnwGPR.tex}} - -\newcommand{\sailMEMr}{\label{zMEMr} \lstinputlisting[language=sail]{sail_latex/sailMEMr.tex}} - -\newcommand{\sailMEMrreserve}{\label{zMEMrzyreserve} \lstinputlisting[language=sail]{sail_latex/sailMEMrreserve.tex}} - -\newcommand{\sailMEMsync}{\label{zMEMzysync} \lstinputlisting[language=sail]{sail_latex/sailMEMsync.tex}} - -\newcommand{\sailMEMea}{\label{zMEMea} \lstinputlisting[language=sail]{sail_latex/sailMEMea.tex}} - -\newcommand{\sailMEMeaconditional}{\label{zMEMeazyconditional} \lstinputlisting[language=sail]{sail_latex/sailMEMeaconditional.tex}} - -\newcommand{\sailMEMval}{\label{zMEMval} \lstinputlisting[language=sail]{sail_latex/sailMEMval.tex}} - -\newcommand{\sailMEMvalconditional}{\label{zMEMvalzyconditional} \lstinputlisting[language=sail]{sail_latex/sailMEMvalconditional.tex}} - -\newcommand{\sailskipeamem}{\label{zskipzyeamem} \lstinputlisting[language=sail]{sail_latex/sailskipeamem.tex}} - -\newcommand{\sailskipbarr}{\label{zskipzybarr} \lstinputlisting[language=sail]{sail_latex/sailskipbarr.tex}} - -\newcommand{\sailskipwreg}{\label{zskipzywreg} \lstinputlisting[language=sail]{sail_latex/sailskipwreg.tex}} - -\newcommand{\sailskiprreg}{\label{zskipzyrreg} \lstinputlisting[language=sail]{sail_latex/sailskiprreg.tex}} - -\newcommand{\sailskipwmvt}{\label{zskipzywmvt} \lstinputlisting[language=sail]{sail_latex/sailskipwmvt.tex}} - -\newcommand{\sailskiprmemt}{\label{zskipzyrmemt} \lstinputlisting[language=sail]{sail_latex/sailskiprmemt.tex}} - -\newcommand{\sailskipescape}{\label{zskipzyescape} \lstinputlisting[language=sail]{sail_latex/sailskipescape.tex}} - -\newcommand{\sailfnMEMr}{\label{zMEMr} \lstinputlisting[language=sail]{sail_latex/sailfnMEMr.tex}} - -\newcommand{\sailfnMEMrreserve}{\label{zMEMrzyreserve} \lstinputlisting[language=sail]{sail_latex/sailfnMEMrreserve.tex}} - -\newcommand{\sailfnMEMsync}{\label{zMEMzysync} \lstinputlisting[language=sail]{sail_latex/sailfnMEMsync.tex}} - -\newcommand{\sailfnMEMea}{\label{zMEMea} \lstinputlisting[language=sail]{sail_latex/sailfnMEMea.tex}} - -\newcommand{\sailfnMEMeaconditional}{\label{zMEMeazyconditional} \lstinputlisting[language=sail]{sail_latex/sailfnMEMeaconditional.tex}} - -\newcommand{\sailfnMEMval}{\label{zMEMval} \lstinputlisting[language=sail]{sail_latex/sailfnMEMval.tex}} - -\newcommand{\sailfnMEMvalconditional}{\label{zMEMvalzyconditional} \lstinputlisting[language=sail]{sail_latex/sailfnMEMvalconditional.tex}} - -\newcommand{\sailException}{\label{zException} \lstinputlisting[language=sail]{sail_latex/sailException.tex}} - -\newcommand{\sailExceptionofnum}{\label{zExceptionzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailExceptionofnum.tex}} - -\newcommand{\sailfnExceptionofnum}{\label{zExceptionzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnExceptionofnum.tex}} - -\newcommand{\sailnumofException}{\label{znumzyofzyException} \lstinputlisting[language=sail]{sail_latex/sailnumofException.tex}} - -\newcommand{\sailfnnumofException}{\label{znumzyofzyException} \lstinputlisting[language=sail]{sail_latex/sailfnnumofException.tex}} - -\newcommand{\sailExceptionCode}{\label{zExceptionCode} \lstinputlisting[language=sail]{sail_latex/sailExceptionCode.tex}} - -\newcommand{\sailfnExceptionCode}{\label{zExceptionCode} \lstinputlisting[language=sail]{sail_latex/sailfnExceptionCode.tex}} - -\newcommand{\sailSignalExceptionMIPS}{\label{zSignalExceptionMIPS} \lstinputlisting[language=sail]{sail_latex/sailSignalExceptionMIPS.tex}} - -\newcommand{\sailfnSignalExceptionMIPS}{\label{zSignalExceptionMIPS} \lstinputlisting[language=sail]{sail_latex/sailfnSignalExceptionMIPS.tex}} - -\newcommand{\sailSignalException}{\label{zSignalException} \lstinputlisting[language=sail]{sail_latex/sailSignalException.tex}} - -\newcommand{\sailSignalExceptionBadAddr}{\label{zSignalExceptionBadAddr} \lstinputlisting[language=sail]{sail_latex/sailSignalExceptionBadAddr.tex}} - -\newcommand{\sailfnSignalExceptionBadAddr}{\label{zSignalExceptionBadAddr} \lstinputlisting[language=sail]{sail_latex/sailfnSignalExceptionBadAddr.tex}} - -\newcommand{\sailSignalExceptionTLB}{\label{zSignalExceptionTLB} \lstinputlisting[language=sail]{sail_latex/sailSignalExceptionTLB.tex}} - -\newcommand{\sailfnSignalExceptionTLB}{\label{zSignalExceptionTLB} \lstinputlisting[language=sail]{sail_latex/sailfnSignalExceptionTLB.tex}} - -\newcommand{\sailMemAccessType}{\label{zMemAccessType} \lstinputlisting[language=sail]{sail_latex/sailMemAccessType.tex}} - -\newcommand{\sailMemAccessTypeofnum}{\label{zMemAccessTypezyofzynum} \lstinputlisting[language=sail]{sail_latex/sailMemAccessTypeofnum.tex}} - -\newcommand{\sailfnMemAccessTypeofnum}{\label{zMemAccessTypezyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnMemAccessTypeofnum.tex}} - -\newcommand{\sailnumofMemAccessType}{\label{znumzyofzyMemAccessType} \lstinputlisting[language=sail]{sail_latex/sailnumofMemAccessType.tex}} - -\newcommand{\sailfnnumofMemAccessType}{\label{znumzyofzyMemAccessType} \lstinputlisting[language=sail]{sail_latex/sailfnnumofMemAccessType.tex}} - -\newcommand{\sailAccessLevel}{\label{zAccessLevel} \lstinputlisting[language=sail]{sail_latex/sailAccessLevel.tex}} - -\newcommand{\sailAccessLevelofnum}{\label{zAccessLevelzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailAccessLevelofnum.tex}} - -\newcommand{\sailfnAccessLevelofnum}{\label{zAccessLevelzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnAccessLevelofnum.tex}} - -\newcommand{\sailnumofAccessLevel}{\label{znumzyofzyAccessLevel} \lstinputlisting[language=sail]{sail_latex/sailnumofAccessLevel.tex}} - -\newcommand{\sailfnnumofAccessLevel}{\label{znumzyofzyAccessLevel} \lstinputlisting[language=sail]{sail_latex/sailfnnumofAccessLevel.tex}} - -\newcommand{\sailintofAccessLevel}{\label{zintzyofzyAccessLevel} \lstinputlisting[language=sail]{sail_latex/sailintofAccessLevel.tex}} - -\newcommand{\sailfnintofAccessLevel}{\label{zintzyofzyAccessLevel} \lstinputlisting[language=sail]{sail_latex/sailfnintofAccessLevel.tex}} - -\newcommand{\sailgrantsAccess}{\label{zgrantsAccess} -Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. - \lstinputlisting[language=sail]{sail_latex/sailgrantsAccess.tex}} - -\newcommand{\sailfngrantsAccess}{\label{zgrantsAccess} \lstinputlisting[language=sail]{sail_latex/sailfngrantsAccess.tex}} - -\newcommand{\sailgetAccessLevel}{\label{zgetAccessLevel} -Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. - \lstinputlisting[language=sail]{sail_latex/sailgetAccessLevel.tex}} - -\newcommand{\sailfngetAccessLevel}{\label{zgetAccessLevel} \lstinputlisting[language=sail]{sail_latex/sailfngetAccessLevel.tex}} - -\newcommand{\sailcheckCPzeroAccess}{\label{zcheckCPzeroAccess} \lstinputlisting[language=sail]{sail_latex/sailcheckCPzeroAccess.tex}} - -\newcommand{\sailfncheckCPzeroAccess}{\label{zcheckCPzeroAccess} \lstinputlisting[language=sail]{sail_latex/sailfncheckCPzeroAccess.tex}} - -\newcommand{\sailincrementCPzeroCount}{\label{zincrementCPzeroCount} \lstinputlisting[language=sail]{sail_latex/sailincrementCPzeroCount.tex}} - -\newcommand{\sailfnincrementCPzeroCount}{\label{zincrementCPzeroCount} \lstinputlisting[language=sail]{sail_latex/sailfnincrementCPzeroCount.tex}} - -\newcommand{\sailregno}{\label{zregno} \lstinputlisting[language=sail]{sail_latex/sailregno.tex}} - -\newcommand{\sailimmonesix}{\label{zimmonesix} \lstinputlisting[language=sail]{sail_latex/sailimmonesix.tex}} - -\newcommand{\sailregregreg}{\label{zregregreg} \lstinputlisting[language=sail]{sail_latex/sailregregreg.tex}} - -\newcommand{\sailregregimmonesix}{\label{zregregimmonesix} \lstinputlisting[language=sail]{sail_latex/sailregregimmonesix.tex}} - -\newcommand{\saildecodefailure}{\label{zdecodezyfailure} \lstinputlisting[language=sail]{sail_latex/saildecodefailure.tex}} - -\newcommand{\saildecodefailureofnum}{\label{zdecodezyfailurezyofzynum} \lstinputlisting[language=sail]{sail_latex/saildecodefailureofnum.tex}} - -\newcommand{\sailfndecodefailureofnum}{\label{zdecodezyfailurezyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfndecodefailureofnum.tex}} - -\newcommand{\sailnumofdecodefailure}{\label{znumzyofzydecodezyfailure} \lstinputlisting[language=sail]{sail_latex/sailnumofdecodefailure.tex}} - -\newcommand{\sailfnnumofdecodefailure}{\label{znumzyofzydecodezyfailure} \lstinputlisting[language=sail]{sail_latex/sailfnnumofdecodefailure.tex}} - -\newcommand{\sailComparison}{\label{zComparison} \lstinputlisting[language=sail]{sail_latex/sailComparison.tex}} - -\newcommand{\sailComparisonofnum}{\label{zComparisonzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailComparisonofnum.tex}} - -\newcommand{\sailfnComparisonofnum}{\label{zComparisonzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnComparisonofnum.tex}} - -\newcommand{\sailnumofComparison}{\label{znumzyofzyComparison} \lstinputlisting[language=sail]{sail_latex/sailnumofComparison.tex}} - -\newcommand{\sailfnnumofComparison}{\label{znumzyofzyComparison} \lstinputlisting[language=sail]{sail_latex/sailfnnumofComparison.tex}} - -\newcommand{\sailcompare}{\label{zcompare} \lstinputlisting[language=sail]{sail_latex/sailcompare.tex}} - -\newcommand{\sailfncompare}{\label{zcompare} \lstinputlisting[language=sail]{sail_latex/sailfncompare.tex}} - -\newcommand{\sailWordType}{\label{zWordType} \lstinputlisting[language=sail]{sail_latex/sailWordType.tex}} - -\newcommand{\sailWordTypeofnum}{\label{zWordTypezyofzynum} \lstinputlisting[language=sail]{sail_latex/sailWordTypeofnum.tex}} - -\newcommand{\sailfnWordTypeofnum}{\label{zWordTypezyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnWordTypeofnum.tex}} - -\newcommand{\sailnumofWordType}{\label{znumzyofzyWordType} \lstinputlisting[language=sail]{sail_latex/sailnumofWordType.tex}} - -\newcommand{\sailfnnumofWordType}{\label{znumzyofzyWordType} \lstinputlisting[language=sail]{sail_latex/sailfnnumofWordType.tex}} - -\newcommand{\sailWordTypeUnaligned}{\label{zWordTypeUnaligned} \lstinputlisting[language=sail]{sail_latex/sailWordTypeUnaligned.tex}} - -\newcommand{\sailWordTypeUnalignedofnum}{\label{zWordTypeUnalignedzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailWordTypeUnalignedofnum.tex}} - -\newcommand{\sailfnWordTypeUnalignedofnum}{\label{zWordTypeUnalignedzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnWordTypeUnalignedofnum.tex}} - -\newcommand{\sailnumofWordTypeUnaligned}{\label{znumzyofzyWordTypeUnaligned} \lstinputlisting[language=sail]{sail_latex/sailnumofWordTypeUnaligned.tex}} - -\newcommand{\sailfnnumofWordTypeUnaligned}{\label{znumzyofzyWordTypeUnaligned} \lstinputlisting[language=sail]{sail_latex/sailfnnumofWordTypeUnaligned.tex}} - -\newcommand{\sailwordWidthBytes}{\label{zwordWidthBytes} \lstinputlisting[language=sail]{sail_latex/sailwordWidthBytes.tex}} - -\newcommand{\sailfnwordWidthBytes}{\label{zwordWidthBytes} \lstinputlisting[language=sail]{sail_latex/sailfnwordWidthBytes.tex}} - -\newcommand{\sailisAddressAligned}{\label{zisAddressAligned} \lstinputlisting[language=sail]{sail_latex/sailisAddressAligned.tex}} - -\newcommand{\sailfnisAddressAligned}{\label{zisAddressAligned} \lstinputlisting[language=sail]{sail_latex/sailfnisAddressAligned.tex}} - -\newcommand{\sailreverseendianness}{\label{zreversezyendianness} \lstinputlisting[language=sail]{sail_latex/sailreverseendianness.tex}} - -\newcommand{\sailMEMrwrapper}{\label{zMEMrzywrapper} \lstinputlisting[language=sail]{sail_latex/sailMEMrwrapper.tex}} - -\newcommand{\sailfnMEMrwrapper}{\label{zMEMrzywrapper} \lstinputlisting[language=sail]{sail_latex/sailfnMEMrwrapper.tex}} - -\newcommand{\sailMEMrreservewrapper}{\label{zMEMrzyreservezywrapper} \lstinputlisting[language=sail]{sail_latex/sailMEMrreservewrapper.tex}} - -\newcommand{\sailfnMEMrreservewrapper}{\label{zMEMrzyreservezywrapper} \lstinputlisting[language=sail]{sail_latex/sailfnMEMrreservewrapper.tex}} - -\newcommand{\sailinitcpzerostate}{\label{zinitzycpzerozystate} \lstinputlisting[language=sail]{sail_latex/sailinitcpzerostate.tex}} - -\newcommand{\sailfninitcpzerostate}{\label{zinitzycpzerozystate} \lstinputlisting[language=sail]{sail_latex/sailfninitcpzerostate.tex}} - -\newcommand{\sailinitcptwostate}{\label{zinitzycptwozystate} \lstinputlisting[language=sail]{sail_latex/sailinitcptwostate.tex}} - -\newcommand{\sailcptwonextpc}{\label{zcptwozynextzypc} \lstinputlisting[language=sail]{sail_latex/sailcptwonextpc.tex}} - -\newcommand{\saildumpcptwostate}{\label{zdumpzycptwozystate} \lstinputlisting[language=sail]{sail_latex/saildumpcptwostate.tex}} - -\newcommand{\sailtlbEntryMatch}{\label{ztlbEntryMatch} \lstinputlisting[language=sail]{sail_latex/sailtlbEntryMatch.tex}} - -\newcommand{\sailfntlbEntryMatch}{\label{ztlbEntryMatch} \lstinputlisting[language=sail]{sail_latex/sailfntlbEntryMatch.tex}} - -\newcommand{\sailtlbSearch}{\label{ztlbSearch} \lstinputlisting[language=sail]{sail_latex/sailtlbSearch.tex}} - -\newcommand{\sailfntlbSearch}{\label{ztlbSearch} \lstinputlisting[language=sail]{sail_latex/sailfntlbSearch.tex}} - -\newcommand{\sailTLBTranslatetwo}{\label{zTLBTranslatetwo} \lstinputlisting[language=sail]{sail_latex/sailTLBTranslatetwo.tex}} - -\newcommand{\sailfnTLBTranslatetwo}{\label{zTLBTranslatetwo} \lstinputlisting[language=sail]{sail_latex/sailfnTLBTranslatetwo.tex}} - -\newcommand{\sailTLBTranslateC}{\label{zTLBTranslateC} \lstinputlisting[language=sail]{sail_latex/sailTLBTranslateC.tex}} - -\newcommand{\sailfnTLBTranslateC}{\label{zTLBTranslateC} \lstinputlisting[language=sail]{sail_latex/sailfnTLBTranslateC.tex}} - -\newcommand{\sailTLBTranslate}{\label{zTLBTranslate} \lstinputlisting[language=sail]{sail_latex/sailTLBTranslate.tex}} - -\newcommand{\sailfnTLBTranslate}{\label{zTLBTranslate} \lstinputlisting[language=sail]{sail_latex/sailfnTLBTranslate.tex}} - -\newcommand{\sailCapLen}{\label{zCapLen} \lstinputlisting[language=sail]{sail_latex/sailCapLen.tex}} - -\newcommand{\sailuintsixfour}{\label{zuintsixfour} \lstinputlisting[language=sail]{sail_latex/sailuintsixfour.tex}} - -\newcommand{\sailCPtrCmpOp}{\label{zCPtrCmpOp} \lstinputlisting[language=sail]{sail_latex/sailCPtrCmpOp.tex}} - -\newcommand{\sailCPtrCmpOpofnum}{\label{zCPtrCmpOpzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailCPtrCmpOpofnum.tex}} - -\newcommand{\sailfnCPtrCmpOpofnum}{\label{zCPtrCmpOpzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnCPtrCmpOpofnum.tex}} - -\newcommand{\sailnumofCPtrCmpOp}{\label{znumzyofzyCPtrCmpOp} \lstinputlisting[language=sail]{sail_latex/sailnumofCPtrCmpOp.tex}} - -\newcommand{\sailfnnumofCPtrCmpOp}{\label{znumzyofzyCPtrCmpOp} \lstinputlisting[language=sail]{sail_latex/sailfnnumofCPtrCmpOp.tex}} - -\newcommand{\sailClearRegSet}{\label{zClearRegSet} \lstinputlisting[language=sail]{sail_latex/sailClearRegSet.tex}} - -\newcommand{\sailClearRegSetofnum}{\label{zClearRegSetzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailClearRegSetofnum.tex}} - -\newcommand{\sailfnClearRegSetofnum}{\label{zClearRegSetzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnClearRegSetofnum.tex}} - -\newcommand{\sailnumofClearRegSet}{\label{znumzyofzyClearRegSet} \lstinputlisting[language=sail]{sail_latex/sailnumofClearRegSet.tex}} - -\newcommand{\sailfnnumofClearRegSet}{\label{znumzyofzyClearRegSet} \lstinputlisting[language=sail]{sail_latex/sailfnnumofClearRegSet.tex}} - -\newcommand{\sailCapReg}{\label{zCapReg} \lstinputlisting[language=sail]{sail_latex/sailCapReg.tex}} - -\newcommand{\sailCapStruct}{\label{zCapStruct} \lstinputlisting[language=sail]{sail_latex/sailCapStruct.tex}} - -\newcommand{\sailcapRegToCapStruct}{\label{zcapRegToCapStruct} \lstinputlisting[language=sail]{sail_latex/sailcapRegToCapStruct.tex}} - -\newcommand{\sailfncapRegToCapStruct}{\label{zcapRegToCapStruct} \lstinputlisting[language=sail]{sail_latex/sailfncapRegToCapStruct.tex}} - -\newcommand{\sailgetCapPerms}{\label{zgetCapPerms} \lstinputlisting[language=sail]{sail_latex/sailgetCapPerms.tex}} - -\newcommand{\sailfngetCapPerms}{\label{zgetCapPerms} \lstinputlisting[language=sail]{sail_latex/sailfngetCapPerms.tex}} - -\newcommand{\sailcapStructToMemBitstwofivesix}{\label{zcapStructToMemBitstwofivesix} \lstinputlisting[language=sail]{sail_latex/sailcapStructToMemBitstwofivesix.tex}} - -\newcommand{\sailfncapStructToMemBitstwofivesix}{\label{zcapStructToMemBitstwofivesix} \lstinputlisting[language=sail]{sail_latex/sailfncapStructToMemBitstwofivesix.tex}} - -\newcommand{\sailcapStructToMemBits}{\label{zcapStructToMemBits} \lstinputlisting[language=sail]{sail_latex/sailcapStructToMemBits.tex}} - -\newcommand{\sailfncapStructToMemBits}{\label{zcapStructToMemBits} \lstinputlisting[language=sail]{sail_latex/sailfncapStructToMemBits.tex}} - -\newcommand{\sailmemBitsToCapBits}{\label{zmemBitsToCapBits} \lstinputlisting[language=sail]{sail_latex/sailmemBitsToCapBits.tex}} - -\newcommand{\sailfnmemBitsToCapBits}{\label{zmemBitsToCapBits} \lstinputlisting[language=sail]{sail_latex/sailfnmemBitsToCapBits.tex}} - -\newcommand{\sailcapStructToCapReg}{\label{zcapStructToCapReg} \lstinputlisting[language=sail]{sail_latex/sailcapStructToCapReg.tex}} - -\newcommand{\sailfncapStructToCapReg}{\label{zcapStructToCapReg} \lstinputlisting[language=sail]{sail_latex/sailfncapStructToCapReg.tex}} - -\newcommand{\sailsetCapPerms}{\label{zsetCapPerms} \lstinputlisting[language=sail]{sail_latex/sailsetCapPerms.tex}} - -\newcommand{\sailfnsetCapPerms}{\label{zsetCapPerms} \lstinputlisting[language=sail]{sail_latex/sailfnsetCapPerms.tex}} - -\newcommand{\sailsealCap}{\label{zsealCap} \lstinputlisting[language=sail]{sail_latex/sailsealCap.tex}} - -\newcommand{\sailfnsealCap}{\label{zsealCap} \lstinputlisting[language=sail]{sail_latex/sailfnsealCap.tex}} - -\newcommand{\sailgetCapBase}{\label{zgetCapBase} \lstinputlisting[language=sail]{sail_latex/sailgetCapBase.tex}} - -\newcommand{\sailfngetCapBase}{\label{zgetCapBase} \lstinputlisting[language=sail]{sail_latex/sailfngetCapBase.tex}} - -\newcommand{\sailgetCapTop}{\label{zgetCapTop} \lstinputlisting[language=sail]{sail_latex/sailgetCapTop.tex}} - -\newcommand{\sailfngetCapTop}{\label{zgetCapTop} \lstinputlisting[language=sail]{sail_latex/sailfngetCapTop.tex}} - -\newcommand{\sailgetCapOffset}{\label{zgetCapOffset} \lstinputlisting[language=sail]{sail_latex/sailgetCapOffset.tex}} - -\newcommand{\sailfngetCapOffset}{\label{zgetCapOffset} \lstinputlisting[language=sail]{sail_latex/sailfngetCapOffset.tex}} - -\newcommand{\sailgetCapLength}{\label{zgetCapLength} \lstinputlisting[language=sail]{sail_latex/sailgetCapLength.tex}} - -\newcommand{\sailfngetCapLength}{\label{zgetCapLength} \lstinputlisting[language=sail]{sail_latex/sailfngetCapLength.tex}} - -\newcommand{\sailgetCapCursor}{\label{zgetCapCursor} \lstinputlisting[language=sail]{sail_latex/sailgetCapCursor.tex}} - -\newcommand{\sailfngetCapCursor}{\label{zgetCapCursor} \lstinputlisting[language=sail]{sail_latex/sailfngetCapCursor.tex}} - -\newcommand{\sailsetCapOffset}{\label{zsetCapOffset} -Set the offset capability of the a capability to given value and return the result, along with a boolean indicating true if the operation preserved the existing bounds of the capability. When using compressed capabilities, setting the offset far outside the capability bounds can cause the result to become unrepresentable (XXX mention guarantees). Additionally in some implementations a fast representablity check may be used that could cause the operation to return failure even though the capability would be representable (XXX provide details). - \lstinputlisting[language=sail]{sail_latex/sailsetCapOffset.tex}} - -\newcommand{\sailfnsetCapOffset}{\label{zsetCapOffset} \lstinputlisting[language=sail]{sail_latex/sailfnsetCapOffset.tex}} - -\newcommand{\sailincCapOffset}{\label{zincCapOffset} -\function{incCapOffset} is the same as \function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic). - \lstinputlisting[language=sail]{sail_latex/sailincCapOffset.tex}} - -\newcommand{\sailfnincCapOffset}{\label{zincCapOffset} \lstinputlisting[language=sail]{sail_latex/sailfnincCapOffset.tex}} - -\newcommand{\sailsetCapBounds}{\label{zsetCapBounds} -Returns a capability derived from the given capability by setting the base and top to values provided. The offset of the resulting capability is zero. In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values. - \lstinputlisting[language=sail]{sail_latex/sailsetCapBounds.tex}} - -\newcommand{\sailfnsetCapBounds}{\label{zsetCapBounds} \lstinputlisting[language=sail]{sail_latex/sailfnsetCapBounds.tex}} - -\newcommand{\sailinttocap}{\label{zintzytozycap} \lstinputlisting[language=sail]{sail_latex/sailinttocap.tex}} - -\newcommand{\sailfninttocap}{\label{zintzytozycap} \lstinputlisting[language=sail]{sail_latex/sailfninttocap.tex}} - -\newcommand{\sailexecute}{\label{zexecute} \lstinputlisting[language=sail]{sail_latex/sailexecute.tex}} - -\newcommand{\saildecode}{\label{zdecode} \lstinputlisting[language=sail]{sail_latex/saildecode.tex}} - -\newcommand{\sailreadCapReg}{\label{zreadCapReg} -This function reads a given capability register and returns its contents converted to a CapStruct. -If the argument is zero then the null capability is returned. -\lstinputlisting[language=sail]{sail_latex/sailreadCapReg.tex}} - -\newcommand{\sailfnreadCapReg}{\label{zreadCapReg} \lstinputlisting[language=sail]{sail_latex/sailfnreadCapReg.tex}} - -\newcommand{\sailreadCapRegDDC}{\label{zreadCapRegDDC} -This is the same as readCapReg except that when the argument is zero the value of DDC is returned -instead of the null capability. This is used for instructions that expect an address, where using -null would always generate an exception. -\lstinputlisting[language=sail]{sail_latex/sailreadCapRegDDC.tex}} - -\newcommand{\sailfnreadCapRegDDC}{\label{zreadCapRegDDC} \lstinputlisting[language=sail]{sail_latex/sailfnreadCapRegDDC.tex}} - -\newcommand{\sailwriteCapReg}{\label{zwriteCapReg} \lstinputlisting[language=sail]{sail_latex/sailwriteCapReg.tex}} - -\newcommand{\sailfnwriteCapReg}{\label{zwriteCapReg} \lstinputlisting[language=sail]{sail_latex/sailfnwriteCapReg.tex}} - -\newcommand{\sailCapEx}{\label{zCapEx} \lstinputlisting[language=sail]{sail_latex/sailCapEx.tex}} - -\newcommand{\sailCapExofnum}{\label{zCapExzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailCapExofnum.tex}} - -\newcommand{\sailfnCapExofnum}{\label{zCapExzyofzynum} \lstinputlisting[language=sail]{sail_latex/sailfnCapExofnum.tex}} - -\newcommand{\sailnumofCapEx}{\label{znumzyofzyCapEx} \lstinputlisting[language=sail]{sail_latex/sailnumofCapEx.tex}} - -\newcommand{\sailfnnumofCapEx}{\label{znumzyofzyCapEx} \lstinputlisting[language=sail]{sail_latex/sailfnnumofCapEx.tex}} - -\newcommand{\sailCapExCode}{\label{zCapExCode} \lstinputlisting[language=sail]{sail_latex/sailCapExCode.tex}} - -\newcommand{\sailfnCapExCode}{\label{zCapExCode} \lstinputlisting[language=sail]{sail_latex/sailfnCapExCode.tex}} - -\newcommand{\sailCapCauseReg}{\label{zCapCauseReg} \lstinputlisting[language=sail]{sail_latex/sailCapCauseReg.tex}} - -\newcommand{\sailMkCapCauseReg}{\label{zMkzyCapCauseReg} \lstinputlisting[language=sail]{sail_latex/sailMkCapCauseReg.tex}} - -\newcommand{\sailfnMkCapCauseReg}{\label{zMkzyCapCauseReg} \lstinputlisting[language=sail]{sail_latex/sailfnMkCapCauseReg.tex}} - -\newcommand{\sailgetCapCauseRegbits}{\label{zzygetzyCapCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailgetCapCauseRegbits.tex}} - -\newcommand{\sailfngetCapCauseRegbits}{\label{zzygetzyCapCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfngetCapCauseRegbits.tex}} - -\newcommand{\sailsetCapCauseRegbits}{\label{zzysetzyCapCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailsetCapCauseRegbits.tex}} - -\newcommand{\sailfnsetCapCauseRegbits}{\label{zzysetzyCapCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnsetCapCauseRegbits.tex}} - -\newcommand{\sailupdateCapCauseRegbits}{\label{zzyupdatezyCapCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailupdateCapCauseRegbits.tex}} - -\newcommand{\sailfnupdateCapCauseRegbits}{\label{zzyupdatezyCapCauseRegzybits} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCapCauseRegbits.tex}} - -\newcommand{\sailupdatebits}{\label{zupdatezybits} \lstinputlisting[language=sail]{sail_latex/sailupdatebits.tex}} - -\newcommand{\sailmodbits}{\label{zzymodzybits} \lstinputlisting[language=sail]{sail_latex/sailmodbits.tex}} - -\newcommand{\sailgetCapCauseRegExcCode}{\label{zzygetzyCapCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailgetCapCauseRegExcCode.tex}} - -\newcommand{\sailfngetCapCauseRegExcCode}{\label{zzygetzyCapCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailfngetCapCauseRegExcCode.tex}} - -\newcommand{\sailsetCapCauseRegExcCode}{\label{zzysetzyCapCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailsetCapCauseRegExcCode.tex}} - -\newcommand{\sailfnsetCapCauseRegExcCode}{\label{zzysetzyCapCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailfnsetCapCauseRegExcCode.tex}} - -\newcommand{\sailupdateCapCauseRegExcCode}{\label{zzyupdatezyCapCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailupdateCapCauseRegExcCode.tex}} - -\newcommand{\sailfnupdateCapCauseRegExcCode}{\label{zzyupdatezyCapCauseRegzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCapCauseRegExcCode.tex}} - -\newcommand{\sailupdateExcCode}{\label{zupdatezyExcCode} \lstinputlisting[language=sail]{sail_latex/sailupdateExcCode.tex}} - -\newcommand{\sailmodExcCode}{\label{zzymodzyExcCode} \lstinputlisting[language=sail]{sail_latex/sailmodExcCode.tex}} - -\newcommand{\sailgetCapCauseRegRegNum}{\label{zzygetzyCapCauseRegzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailgetCapCauseRegRegNum.tex}} - -\newcommand{\sailfngetCapCauseRegRegNum}{\label{zzygetzyCapCauseRegzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailfngetCapCauseRegRegNum.tex}} - -\newcommand{\sailsetCapCauseRegRegNum}{\label{zzysetzyCapCauseRegzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailsetCapCauseRegRegNum.tex}} - -\newcommand{\sailfnsetCapCauseRegRegNum}{\label{zzysetzyCapCauseRegzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailfnsetCapCauseRegRegNum.tex}} - -\newcommand{\sailupdateCapCauseRegRegNum}{\label{zzyupdatezyCapCauseRegzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailupdateCapCauseRegRegNum.tex}} - -\newcommand{\sailfnupdateCapCauseRegRegNum}{\label{zzyupdatezyCapCauseRegzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailfnupdateCapCauseRegRegNum.tex}} - -\newcommand{\sailupdateRegNum}{\label{zupdatezyRegNum} \lstinputlisting[language=sail]{sail_latex/sailupdateRegNum.tex}} - -\newcommand{\sailmodRegNum}{\label{zzymodzyRegNum} \lstinputlisting[language=sail]{sail_latex/sailmodRegNum.tex}} - -\newcommand{\sailexecutebranchpcc}{\label{zexecutezybranchzypcc} \lstinputlisting[language=sail]{sail_latex/sailexecutebranchpcc.tex}} - -\newcommand{\sailfnexecutebranchpcc}{\label{zexecutezybranchzypcc} \lstinputlisting[language=sail]{sail_latex/sailfnexecutebranchpcc.tex}} - -\newcommand{\sailfnSignalException}{\label{zSignalException} \lstinputlisting[language=sail]{sail_latex/sailfnSignalException.tex}} - -\newcommand{\sailERETHook}{\label{zERETHook} \lstinputlisting[language=sail]{sail_latex/sailERETHook.tex}} - -\newcommand{\sailfnERETHook}{\label{zERETHook} \lstinputlisting[language=sail]{sail_latex/sailfnERETHook.tex}} - -\newcommand{\sailraisectwoexceptioneight}{\label{zraisezyctwozyexceptioneight} \lstinputlisting[language=sail]{sail_latex/sailraisectwoexceptioneight.tex}} - -\newcommand{\sailfnraisectwoexceptioneight}{\label{zraisezyctwozyexceptioneight} \lstinputlisting[language=sail]{sail_latex/sailfnraisectwoexceptioneight.tex}} - -\newcommand{\sailraisectwoexception}{\label{zraisezyctwozyexception} \lstinputlisting[language=sail]{sail_latex/sailraisectwoexception.tex}} - -\newcommand{\sailfnraisectwoexception}{\label{zraisezyctwozyexception} \lstinputlisting[language=sail]{sail_latex/sailfnraisectwoexception.tex}} - -\newcommand{\sailraisectwoexceptionnoreg}{\label{zraisezyctwozyexceptionzynoreg} \lstinputlisting[language=sail]{sail_latex/sailraisectwoexceptionnoreg.tex}} - -\newcommand{\sailfnraisectwoexceptionnoreg}{\label{zraisezyctwozyexceptionzynoreg} \lstinputlisting[language=sail]{sail_latex/sailfnraisectwoexceptionnoreg.tex}} - -\newcommand{\sailpccaccesssystemregs}{\label{zpcczyaccesszysystemzyregs} \lstinputlisting[language=sail]{sail_latex/sailpccaccesssystemregs.tex}} - -\newcommand{\sailfnpccaccesssystemregs}{\label{zpcczyaccesszysystemzyregs} \lstinputlisting[language=sail]{sail_latex/sailfnpccaccesssystemregs.tex}} - -\newcommand{\sailregisterinaccessible}{\label{zregisterzyinaccessible} -The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. - \lstinputlisting[language=sail]{sail_latex/sailregisterinaccessible.tex}} - -\newcommand{\sailfnregisterinaccessible}{\label{zregisterzyinaccessible} \lstinputlisting[language=sail]{sail_latex/sailfnregisterinaccessible.tex}} - -\newcommand{\sailMEMrtag}{\label{zMEMrzytag} \lstinputlisting[language=sail]{sail_latex/sailMEMrtag.tex}} - -\newcommand{\sailMEMwtag}{\label{zMEMwzytag} \lstinputlisting[language=sail]{sail_latex/sailMEMwtag.tex}} - -\newcommand{\sailMEMrtagged}{\label{zMEMrzytagged} \lstinputlisting[language=sail]{sail_latex/sailMEMrtagged.tex}} - -\newcommand{\sailfnMEMrtagged}{\label{zMEMrzytagged} \lstinputlisting[language=sail]{sail_latex/sailfnMEMrtagged.tex}} - -\newcommand{\sailMEMrtaggedreserve}{\label{zMEMrzytaggedzyreserve} \lstinputlisting[language=sail]{sail_latex/sailMEMrtaggedreserve.tex}} - -\newcommand{\sailfnMEMrtaggedreserve}{\label{zMEMrzytaggedzyreserve} \lstinputlisting[language=sail]{sail_latex/sailfnMEMrtaggedreserve.tex}} - -\newcommand{\sailMEMwtagged}{\label{zMEMwzytagged} \lstinputlisting[language=sail]{sail_latex/sailMEMwtagged.tex}} - -\newcommand{\sailfnMEMwtagged}{\label{zMEMwzytagged} \lstinputlisting[language=sail]{sail_latex/sailfnMEMwtagged.tex}} - -\newcommand{\sailMEMwtaggedconditional}{\label{zMEMwzytaggedzyconditional} \lstinputlisting[language=sail]{sail_latex/sailMEMwtaggedconditional.tex}} - -\newcommand{\sailfnMEMwtaggedconditional}{\label{zMEMwzytaggedzyconditional} \lstinputlisting[language=sail]{sail_latex/sailfnMEMwtaggedconditional.tex}} - -\newcommand{\sailMEMwwrapper}{\label{zMEMwzywrapper} \lstinputlisting[language=sail]{sail_latex/sailMEMwwrapper.tex}} - -\newcommand{\sailfnMEMwwrapper}{\label{zMEMwzywrapper} \lstinputlisting[language=sail]{sail_latex/sailfnMEMwwrapper.tex}} - -\newcommand{\sailMEMwconditionalwrapper}{\label{zMEMwzyconditionalzywrapper} \lstinputlisting[language=sail]{sail_latex/sailMEMwconditionalwrapper.tex}} - -\newcommand{\sailfnMEMwconditionalwrapper}{\label{zMEMwzyconditionalzywrapper} \lstinputlisting[language=sail]{sail_latex/sailfnMEMwconditionalwrapper.tex}} - -\newcommand{\sailcheckDDCPerms}{\label{zcheckDDCPerms} \lstinputlisting[language=sail]{sail_latex/sailcheckDDCPerms.tex}} - -\newcommand{\sailfncheckDDCPerms}{\label{zcheckDDCPerms} \lstinputlisting[language=sail]{sail_latex/sailfncheckDDCPerms.tex}} - -\newcommand{\sailaddrWrapper}{\label{zaddrWrapper} \lstinputlisting[language=sail]{sail_latex/sailaddrWrapper.tex}} - -\newcommand{\sailfnaddrWrapper}{\label{zaddrWrapper} \lstinputlisting[language=sail]{sail_latex/sailfnaddrWrapper.tex}} - -\newcommand{\sailaddrWrapperUnaligned}{\label{zaddrWrapperUnaligned} \lstinputlisting[language=sail]{sail_latex/sailaddrWrapperUnaligned.tex}} - -\newcommand{\sailfnaddrWrapperUnaligned}{\label{zaddrWrapperUnaligned} \lstinputlisting[language=sail]{sail_latex/sailfnaddrWrapperUnaligned.tex}} - -\newcommand{\sailTranslatePC}{\label{zTranslatePC} \lstinputlisting[language=sail]{sail_latex/sailTranslatePC.tex}} - -\newcommand{\sailfnTranslatePC}{\label{zTranslatePC} \lstinputlisting[language=sail]{sail_latex/sailfnTranslatePC.tex}} - -\newcommand{\sailcheckCPtwousable}{\label{zcheckCPtwousable} -All capability instrucitons must first check that the capability -co-processor is enabled using the following function that raises a -co-processor unusable exception if a CP0Status.CU2 is not set. This -allows the operating system to only save and restore the full -capability context for processes that use capabilities. -\lstinputlisting[language=sail]{sail_latex/sailcheckCPtwousable.tex}} - -\newcommand{\sailfncheckCPtwousable}{\label{zcheckCPtwousable} \lstinputlisting[language=sail]{sail_latex/sailfncheckCPtwousable.tex}} - -\newcommand{\sailfninitcptwostate}{\label{zinitzycptwozystate} \lstinputlisting[language=sail]{sail_latex/sailfninitcptwostate.tex}} - -\newcommand{\sailfncptwonextpc}{\label{zcptwozynextzypc} \lstinputlisting[language=sail]{sail_latex/sailfncptwonextpc.tex}} - -\newcommand{\sailcapToString}{\label{zcapToString} \lstinputlisting[language=sail]{sail_latex/sailcapToString.tex}} - -\newcommand{\sailfncapToString}{\label{zcapToString} \lstinputlisting[language=sail]{sail_latex/sailfncapToString.tex}} - -\newcommand{\sailfndumpcptwostate}{\label{zdumpzycptwozystate} \lstinputlisting[language=sail]{sail_latex/sailfndumpcptwostate.tex}} - -\newcommand{\sailextendLoad}{\label{zextendLoad} \lstinputlisting[language=sail]{sail_latex/sailextendLoad.tex}} - -\newcommand{\sailfnextendLoad}{\label{zextendLoad} \lstinputlisting[language=sail]{sail_latex/sailfnextendLoad.tex}} - -\newcommand{\sailTLBWriteEntry}{\label{zTLBWriteEntry} \lstinputlisting[language=sail]{sail_latex/sailTLBWriteEntry.tex}} - -\newcommand{\sailfnTLBWriteEntry}{\label{zTLBWriteEntry} \lstinputlisting[language=sail]{sail_latex/sailfnTLBWriteEntry.tex}} - -\newcommand{\sailfndecodeSomeDADDIU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDADDIU.tex}} - -\newcommand{\sailfndecodeSomeDADDU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDADDU.tex}} - -\newcommand{\sailfndecodeSomeDADDI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDADDI.tex}} - -\newcommand{\sailfndecodeSomeDADD}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDADD.tex}} - -\newcommand{\sailfndecodeSomeADD}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeADD.tex}} - -\newcommand{\sailfndecodeSomeADDI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeADDI.tex}} - -\newcommand{\sailfndecodeSomeADDU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeADDU.tex}} - -\newcommand{\sailfndecodeSomeADDIU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeADDIU.tex}} - -\newcommand{\sailfndecodeSomeDSUBU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSUBU.tex}} - -\newcommand{\sailfndecodeSomeDSUB}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSUB.tex}} - -\newcommand{\sailfndecodeSomeSUB}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSUB.tex}} - -\newcommand{\sailfndecodeSomeSUBU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSUBU.tex}} - -\newcommand{\sailfndecodeSomeAND}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeAND.tex}} - -\newcommand{\sailfndecodeSomeANDI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeANDI.tex}} - -\newcommand{\sailfndecodeSomeOR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeOR.tex}} - -\newcommand{\sailfndecodeSomeORI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeORI.tex}} - -\newcommand{\sailfndecodeSomeNOR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeNOR.tex}} - -\newcommand{\sailfndecodeSomeXOR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeXOR.tex}} - -\newcommand{\sailfndecodeSomeXORI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeXORI.tex}} - -\newcommand{\sailfndecodeSomeLUI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeLUI.tex}} - -\newcommand{\sailfndecodeSomeDSLL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSLL.tex}} - -\newcommand{\sailfndecodeSomeDSLLthreetwo}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSLLthreetwo.tex}} - -\newcommand{\sailfndecodeSomeDSLLV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSLLV.tex}} - -\newcommand{\sailfndecodeSomeDSRA}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSRA.tex}} - -\newcommand{\sailfndecodeSomeDSRAthreetwo}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSRAthreetwo.tex}} - -\newcommand{\sailfndecodeSomeDSRAV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSRAV.tex}} - -\newcommand{\sailfndecodeSomeDSRL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSRL.tex}} - -\newcommand{\sailfndecodeSomeDSRLthreetwo}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSRLthreetwo.tex}} - -\newcommand{\sailfndecodeSomeDSRLV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDSRLV.tex}} - -\newcommand{\sailfndecodeSomeSLL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSLL.tex}} - -\newcommand{\sailfndecodeSomeSLLV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSLLV.tex}} - -\newcommand{\sailfndecodeSomeSRA}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSRA.tex}} - -\newcommand{\sailfndecodeSomeSRAV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSRAV.tex}} - -\newcommand{\sailfndecodeSomeSRL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSRL.tex}} - -\newcommand{\sailfndecodeSomeSRLV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSRLV.tex}} - -\newcommand{\sailfndecodeSomeSLT}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSLT.tex}} - -\newcommand{\sailfndecodeSomeSLTI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSLTI.tex}} - -\newcommand{\sailfndecodeSomeSLTU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSLTU.tex}} - -\newcommand{\sailfndecodeSomeSLTIU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSLTIU.tex}} - -\newcommand{\sailfndecodeSomeMOVN}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMOVN.tex}} - -\newcommand{\sailfndecodeSomeMOVZ}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMOVZ.tex}} - -\newcommand{\sailfndecodeSomeMFHIrd}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMFHIrd.tex}} - -\newcommand{\sailfndecodeSomeMFLOrd}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMFLOrd.tex}} - -\newcommand{\sailfndecodeSomeMTHIrs}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMTHIrs.tex}} - -\newcommand{\sailfndecodeSomeMTLOrs}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMTLOrs.tex}} - -\newcommand{\sailfndecodeSomeMUL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMUL.tex}} - -\newcommand{\sailfndecodeSomeMULT}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMULT.tex}} - -\newcommand{\sailfndecodeSomeMULTU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMULTU.tex}} - -\newcommand{\sailfndecodeSomeDMULT}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDMULT.tex}} - -\newcommand{\sailfndecodeSomeDMULTU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDMULTU.tex}} - -\newcommand{\sailfndecodeSomeMADD}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMADD.tex}} - -\newcommand{\sailfndecodeSomeMADDU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMADDU.tex}} - -\newcommand{\sailfndecodeSomeMSUB}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMSUB.tex}} - -\newcommand{\sailfndecodeSomeMSUBU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMSUBU.tex}} - -\newcommand{\sailfndecodeSomeDIV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDIV.tex}} - -\newcommand{\sailfndecodeSomeDIVU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDIVU.tex}} - -\newcommand{\sailfndecodeSomeDDIV}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDDIV.tex}} - -\newcommand{\sailfndecodeSomeDDIVU}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeDDIVU.tex}} - -\newcommand{\sailfndecodeSomeJoffset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeJoffset.tex}} - -\newcommand{\sailfndecodeSomeJALoffset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeJALoffset.tex}} - -\newcommand{\sailfndecodeSomeJRrs}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeJRrs.tex}} - -\newcommand{\sailfndecodeSomeJALR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeJALR.tex}} - -\newcommand{\sailfndecodeSomeBEQ}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeBEQ.tex}} - -\newcommand{\sailsailfndecodeSomeBEQv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeBEQv.tex}} - -\newcommand{\sailsailsailfndecodeSomeBEQvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeBEQvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeBEQvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeBEQvvv.tex}} - -\newcommand{\sailfndecodeSomeBCMPZ}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeBCMPZ.tex}} - -\newcommand{\sailsailfndecodeSomeBCMPZv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeBCMPZv.tex}} - -\newcommand{\sailsailsailfndecodeSomeBCMPZvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeBCMPZvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeBCMPZvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeBCMPZvvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeBCMPZvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeBCMPZvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeBCMPZvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeBCMPZvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvvv.tex}} - -\newcommand{\sailfndecodeSomeSYSCALL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSYSCALL.tex}} - -\newcommand{\sailfndecodeSomeBREAK}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeBREAK.tex}} - -\newcommand{\sailfndecodeSomeWAIT}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeWAIT.tex}} - -\newcommand{\sailfndecodeSomeTRAPREG}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeTRAPREG.tex}} - -\newcommand{\sailsailfndecodeSomeTRAPREGv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeTRAPREGv.tex}} - -\newcommand{\sailsailsailfndecodeSomeTRAPREGvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeTRAPREGvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeTRAPREGvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeTRAPREGvvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeTRAPREGvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeTRAPREGvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeTRAPREGvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPREGvvvvv.tex}} - -\newcommand{\sailfndecodeSomeTRAPIMM}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeTRAPIMM.tex}} - -\newcommand{\sailsailfndecodeSomeTRAPIMMv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeTRAPIMMv.tex}} - -\newcommand{\sailsailsailfndecodeSomeTRAPIMMvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeTRAPIMMvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeTRAPIMMvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeTRAPIMMvvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeTRAPIMMvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeTRAPIMMvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeTRAPIMMvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPIMMvvvvv.tex}} - -\newcommand{\sailfndecodeSomeLoad}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeLoad.tex}} - -\newcommand{\sailsailfndecodeSomeLoadv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeLoadv.tex}} - -\newcommand{\sailsailsailfndecodeSomeLoadvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeLoadvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeLoadvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeLoadvvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeLoadvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeLoadvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeLoadvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeLoadvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailfndecodeSomeLoadvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailfndecodeSomeLoadvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvvv.tex}} - -\newcommand{\sailfndecodeSomeStore}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeStore.tex}} - -\newcommand{\sailsailfndecodeSomeStorev}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeStorev.tex}} - -\newcommand{\sailsailsailfndecodeSomeStorevv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeStorevv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeStorevvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeStorevvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeStorevvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeStorevvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeStorevvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeStorevvvvv.tex}} - -\newcommand{\sailfndecodeSomeLWL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeLWL.tex}} - -\newcommand{\sailfndecodeSomeLWR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeLWR.tex}} - -\newcommand{\sailfndecodeSomeSWL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSWL.tex}} - -\newcommand{\sailfndecodeSomeSWR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSWR.tex}} - -\newcommand{\sailfndecodeSomeLDL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeLDL.tex}} - -\newcommand{\sailfndecodeSomeLDR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeLDR.tex}} - -\newcommand{\sailfndecodeSomeSDL}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSDL.tex}} - -\newcommand{\sailfndecodeSomeSDR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSDR.tex}} - -\newcommand{\sailfndecodeSomeCACHE}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCACHE.tex}} - -\newcommand{\sailfndecodeSomeSYNC}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeSYNC.tex}} - -\newcommand{\sailfndecodeSomeMFCzero}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMFCzero.tex}} - -\newcommand{\sailsailfndecodeSomeMFCzerov}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeMFCzerov.tex}} - -\newcommand{\sailfndecodeSomeHCF}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeHCF.tex}} - -\newcommand{\sailsailfndecodeSomeHCFv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeHCFv.tex}} - -\newcommand{\sailfndecodeSomeMTCzero}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeMTCzero.tex}} - -\newcommand{\sailsailfndecodeSomeMTCzerov}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeMTCzerov.tex}} - -\newcommand{\sailfndecodeSome}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSome.tex}} - -\newcommand{\sailsailfndecodeSomev}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomev.tex}} - -\newcommand{\sailsailsailfndecodeSomevv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomevv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomevvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomevvv.tex}} - -\newcommand{\sailfndecodeSomeRDHWR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeRDHWR.tex}} - -\newcommand{\sailfndecodeSomeERET}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeERET.tex}} - -\newcommand{\sailfndecodeSomeCGetPerm}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetPerm.tex}} - -\newcommand{\sailfndecodeSomeCGetType}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetType.tex}} - -\newcommand{\sailfndecodeSomeCGetBase}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetBase.tex}} - -\newcommand{\sailfndecodeSomeCGetLen}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetLen.tex}} - -\newcommand{\sailfndecodeSomeCGetTag}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetTag.tex}} - -\newcommand{\sailfndecodeSomeCGetSealed}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetSealed.tex}} - -\newcommand{\sailfndecodeSomeCGetCauserd}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetCauserd.tex}} - -\newcommand{\sailfndecodeSomeCReturn}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCReturn.tex}} - -\newcommand{\sailfndecodeSomeCGetOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetOffset.tex}} - -\newcommand{\sailfndecodeSomeCSetCausert}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSetCausert.tex}} - -\newcommand{\sailfndecodeSomeCAndPerm}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCAndPerm.tex}} - -\newcommand{\sailfndecodeSomeCToPtr}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCToPtr.tex}} - -\newcommand{\sailfndecodeSomeCPtrCmp}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCPtrCmp.tex}} - -\newcommand{\sailsailfndecodeSomeCPtrCmpv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCPtrCmpv.tex}} - -\newcommand{\sailsailsailfndecodeSomeCPtrCmpvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeCPtrCmpvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeCPtrCmpvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeCPtrCmpvvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeCPtrCmpvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeCPtrCmpvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvv.tex}} - -\newcommand{\sailfndecodeSomeCIncOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCIncOffset.tex}} - -\newcommand{\sailfndecodeSomeCSetOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSetOffset.tex}} - -\newcommand{\sailfndecodeSomeCSetBounds}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSetBounds.tex}} - -\newcommand{\sailfndecodeSomeCClearTag}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCClearTag.tex}} - -\newcommand{\sailfndecodeSomeCFromPtr}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCFromPtr.tex}} - -\newcommand{\sailfndecodeSomeCCheckPerm}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCCheckPerm.tex}} - -\newcommand{\sailfndecodeSomeCCheckType}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCCheckType.tex}} - -\newcommand{\sailfndecodeSomeCSeal}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSeal.tex}} - -\newcommand{\sailfndecodeSomeCUnseal}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCUnseal.tex}} - -\newcommand{\sailfndecodeSomeCJALR}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCJALR.tex}} - -\newcommand{\sailsailfndecodeSomeCJALRv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCJALRv.tex}} - -\newcommand{\sailsailfndecodeSomeCGetCauserdv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetCauserdv.tex}} - -\newcommand{\sailfndecodeSomeCSetCausers}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSetCausers.tex}} - -\newcommand{\sailfndecodeSomeCGetPCCcd}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetPCCcd.tex}} - -\newcommand{\sailsailsailfndecodeSomeCJALRvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeCJALRvv.tex}} - -\newcommand{\sailsailfndecodeSomeCCheckPermv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCCheckPermv.tex}} - -\newcommand{\sailsailfndecodeSomeCCheckTypev}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCCheckTypev.tex}} - -\newcommand{\sailsailfndecodeSomeCClearTagv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCClearTagv.tex}} - -\newcommand{\sailfndecodeSomeCMOVX}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCMOVX.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeCJALRvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeCJALRvvv.tex}} - -\newcommand{\sailsailfndecodeSomeCGetPermv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetPermv.tex}} - -\newcommand{\sailsailfndecodeSomeCGetTypev}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetTypev.tex}} - -\newcommand{\sailsailfndecodeSomeCGetBasev}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetBasev.tex}} - -\newcommand{\sailsailfndecodeSomeCGetLenv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetLenv.tex}} - -\newcommand{\sailsailfndecodeSomeCGetTagv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetTagv.tex}} - -\newcommand{\sailsailfndecodeSomeCGetSealedv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetSealedv.tex}} - -\newcommand{\sailsailfndecodeSomeCGetOffsetv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCGetOffsetv.tex}} - -\newcommand{\sailfndecodeSomeCGetPCCSetOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetPCCSetOffset.tex}} - -\newcommand{\sailfndecodeSomeCReadHwr}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCReadHwr.tex}} - -\newcommand{\sailfndecodeSomeCWriteHwr}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCWriteHwr.tex}} - -\newcommand{\sailfndecodeSomeCGetAddr}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCGetAddr.tex}} - -\newcommand{\sailsailfndecodeSomeCSealv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCSealv.tex}} - -\newcommand{\sailsailfndecodeSomeCUnsealv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCUnsealv.tex}} - -\newcommand{\sailsailfndecodeSomeCAndPermv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCAndPermv.tex}} - -\newcommand{\sailsailfndecodeSomeCSetOffsetv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCSetOffsetv.tex}} - -\newcommand{\sailsailfndecodeSomeCSetBoundsv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCSetBoundsv.tex}} - -\newcommand{\sailfndecodeSomeCSetBoundsExact}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSetBoundsExact.tex}} - -\newcommand{\sailsailfndecodeSomeCIncOffsetv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCIncOffsetv.tex}} - -\newcommand{\sailfndecodeSomeCBuildCap}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCBuildCap.tex}} - -\newcommand{\sailfndecodeSomeCCopyType}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCCopyType.tex}} - -\newcommand{\sailfndecodeSomeCCSeal}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCCSeal.tex}} - -\newcommand{\sailsailfndecodeSomeCToPtrv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCToPtrv.tex}} - -\newcommand{\sailsailfndecodeSomeCFromPtrv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCFromPtrv.tex}} - -\newcommand{\sailfndecodeSomeCSub}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSub.tex}} - -\newcommand{\sailsailfndecodeSomeCMOVXv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCMOVXv.tex}} - -\newcommand{\sailsailsailfndecodeSomeCMOVXvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeCMOVXvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvvv.tex}} - -\newcommand{\sailfndecodeSomeCTestSubset}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCTestSubset.tex}} - -\newcommand{\sailfndecodeSomeCBX}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCBX.tex}} - -\newcommand{\sailsailfndecodeSomeCBXv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCBXv.tex}} - -\newcommand{\sailfndecodeSomeCBZ}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCBZ.tex}} - -\newcommand{\sailsailfndecodeSomeCBZv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCBZv.tex}} - -\newcommand{\sailsailfndecodeSomeCReturnv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCReturnv.tex}} - -\newcommand{\sailfndecodeSomeCCall}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCCall.tex}} - -\newcommand{\sailfndecodeSomeClearRegs}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeClearRegs.tex}} - -\newcommand{\sailsailfndecodeSomeClearRegsv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeClearRegsv.tex}} - -\newcommand{\sailsailsailfndecodeSomeClearRegsvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeClearRegsvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeClearRegsvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeClearRegsvvv.tex}} - -\newcommand{\sailfndecodeSomeCIncOffsetImmediate}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCIncOffsetImmediate.tex}} - -\newcommand{\sailfndecodeSomeCSetBoundsImmediate}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSetBoundsImmediate.tex}} - -\newcommand{\sailfndecodeSomeCLoad}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCLoad.tex}} - -\newcommand{\sailsailfndecodeSomeCLoadv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCLoadv.tex}} - -\newcommand{\sailsailsailfndecodeSomeCLoadvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeCLoadvv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeCLoadvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeCLoadvvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeCLoadvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeCLoadvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeCLoadvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeCLoadvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvvv.tex}} - -\newcommand{\sailfndecodeSomeCStore}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCStore.tex}} - -\newcommand{\sailsailfndecodeSomeCStorev}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCStorev.tex}} - -\newcommand{\sailsailsailfndecodeSomeCStorevv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeCStorevv.tex}} - -\newcommand{\sailsailsailsailfndecodeSomeCStorevvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailfndecodeSomeCStorevvv.tex}} - -\newcommand{\sailsailsailsailsailfndecodeSomeCStorevvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailfndecodeSomeCStorevvvv.tex}} - -\newcommand{\sailsailsailsailsailsailfndecodeSomeCStorevvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailfndecodeSomeCStorevvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailfndecodeSomeCStorevvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailfndecodeSomeCStorevvvvvv.tex}} - -\newcommand{\sailsailsailsailsailsailsailsailfndecodeSomeCStorevvvvvvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCStorevvvvvvv.tex}} - -\newcommand{\sailfndecodeSomeCSC}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCSC.tex}} - -\newcommand{\sailsailfndecodeSomeCSCv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCSCv.tex}} - -\newcommand{\sailfndecodeSomeCLC}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCLC.tex}} - -\newcommand{\sailsailfndecodeSomeCLCv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfndecodeSomeCLCv.tex}} - -\newcommand{\sailsailsailfndecodeSomeCLCvv}{ \lstinputlisting[language=sail]{sail_latex/sailsailsailfndecodeSomeCLCvv.tex}} - -\newcommand{\sailfndecodeSomeCtwoDumprt}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeCtwoDumprt.tex}} - -\newcommand{\sailfndecodeSomeRI}{ \lstinputlisting[language=sail]{sail_latex/sailfndecodeSomeRI.tex}} - - - -\newcommand{\sailfnexecuteDADDIU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDADDIU.tex}} - -\newcommand{\sailfnexecuteDADDU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDADDU.tex}} - -\newcommand{\sailfnexecuteDADDI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDADDI.tex}} - -\newcommand{\sailfnexecuteDADD}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDADD.tex}} - -\newcommand{\sailfnexecuteADD}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteADD.tex}} - -\newcommand{\sailfnexecuteADDI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteADDI.tex}} - -\newcommand{\sailfnexecuteADDU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteADDU.tex}} - -\newcommand{\sailfnexecuteADDIU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteADDIU.tex}} - -\newcommand{\sailfnexecuteDSUBU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSUBU.tex}} - -\newcommand{\sailfnexecuteDSUB}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSUB.tex}} - -\newcommand{\sailfnexecuteSUB}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSUB.tex}} - -\newcommand{\sailfnexecuteSUBU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSUBU.tex}} - -\newcommand{\sailfnexecuteAND}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteAND.tex}} - -\newcommand{\sailfnexecuteANDI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteANDI.tex}} - -\newcommand{\sailfnexecuteOR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteOR.tex}} - -\newcommand{\sailfnexecuteORI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteORI.tex}} - -\newcommand{\sailfnexecuteNOR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteNOR.tex}} - -\newcommand{\sailfnexecuteXOR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteXOR.tex}} - -\newcommand{\sailfnexecuteXORI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteXORI.tex}} - -\newcommand{\sailfnexecuteLUI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteLUI.tex}} - -\newcommand{\sailfnexecuteDSLL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSLL.tex}} - -\newcommand{\sailfnexecuteDSLLthreetwo}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSLLthreetwo.tex}} - -\newcommand{\sailfnexecuteDSLLV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSLLV.tex}} - -\newcommand{\sailfnexecuteDSRA}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSRA.tex}} - -\newcommand{\sailfnexecuteDSRAthreetwo}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSRAthreetwo.tex}} - -\newcommand{\sailfnexecuteDSRAV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSRAV.tex}} - -\newcommand{\sailfnexecuteDSRL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSRL.tex}} - -\newcommand{\sailfnexecuteDSRLthreetwo}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSRLthreetwo.tex}} - -\newcommand{\sailfnexecuteDSRLV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDSRLV.tex}} - -\newcommand{\sailfnexecuteSLL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSLL.tex}} - -\newcommand{\sailfnexecuteSLLV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSLLV.tex}} - -\newcommand{\sailfnexecuteSRA}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSRA.tex}} - -\newcommand{\sailfnexecuteSRAV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSRAV.tex}} - -\newcommand{\sailfnexecuteSRL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSRL.tex}} - -\newcommand{\sailfnexecuteSRLV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSRLV.tex}} - -\newcommand{\sailfnexecuteSLT}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSLT.tex}} - -\newcommand{\sailfnexecuteSLTI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSLTI.tex}} - -\newcommand{\sailfnexecuteSLTU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSLTU.tex}} - -\newcommand{\sailfnexecuteSLTIU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSLTIU.tex}} - -\newcommand{\sailfnexecuteMOVN}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMOVN.tex}} - -\newcommand{\sailfnexecuteMOVZ}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMOVZ.tex}} - -\newcommand{\sailfnexecuteMFHI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMFHI.tex}} - -\newcommand{\sailfnexecuteMFLO}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMFLO.tex}} - -\newcommand{\sailfnexecuteMTHI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMTHI.tex}} - -\newcommand{\sailfnexecuteMTLO}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMTLO.tex}} - -\newcommand{\sailfnexecuteMUL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMUL.tex}} - -\newcommand{\sailfnexecuteMULT}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMULT.tex}} - -\newcommand{\sailfnexecuteMULTU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMULTU.tex}} - -\newcommand{\sailfnexecuteDMULT}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDMULT.tex}} - -\newcommand{\sailfnexecuteDMULTU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDMULTU.tex}} - -\newcommand{\sailfnexecuteMADD}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMADD.tex}} - -\newcommand{\sailfnexecuteMADDU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMADDU.tex}} - -\newcommand{\sailfnexecuteMSUB}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMSUB.tex}} - -\newcommand{\sailfnexecuteMSUBU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMSUBU.tex}} - -\newcommand{\sailfnexecuteDIV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDIV.tex}} - -\newcommand{\sailfnexecuteDIVU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDIVU.tex}} - -\newcommand{\sailfnexecuteDDIV}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDDIV.tex}} - -\newcommand{\sailfnexecuteDDIVU}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteDDIVU.tex}} - -\newcommand{\sailfnexecuteJ}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteJ.tex}} - -\newcommand{\sailfnexecuteJAL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteJAL.tex}} - -\newcommand{\sailfnexecuteJR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteJR.tex}} - -\newcommand{\sailfnexecuteJALR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteJALR.tex}} - -\newcommand{\sailfnexecuteBEQ}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteBEQ.tex}} - -\newcommand{\sailfnexecuteBCMPZ}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteBCMPZ.tex}} - -\newcommand{\sailfnexecuteSYSCALL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSYSCALL.tex}} - -\newcommand{\sailfnexecuteBREAK}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteBREAK.tex}} - -\newcommand{\sailfnexecuteWAIT}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteWAIT.tex}} - -\newcommand{\sailfnexecuteTRAPREG}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteTRAPREG.tex}} - -\newcommand{\sailfnexecuteTRAPIMM}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteTRAPIMM.tex}} - -\newcommand{\sailfnexecuteLoad}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteLoad.tex}} - -\newcommand{\sailfnexecuteStore}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteStore.tex}} - -\newcommand{\sailfnexecuteLWL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteLWL.tex}} - -\newcommand{\sailfnexecuteLWR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteLWR.tex}} - -\newcommand{\sailfnexecuteSWL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSWL.tex}} - -\newcommand{\sailfnexecuteSWR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSWR.tex}} - -\newcommand{\sailfnexecuteLDL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteLDL.tex}} - -\newcommand{\sailfnexecuteLDR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteLDR.tex}} - -\newcommand{\sailfnexecuteSDL}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSDL.tex}} - -\newcommand{\sailfnexecuteSDR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSDR.tex}} - -\newcommand{\sailfnexecuteCACHE}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCACHE.tex}} - -\newcommand{\sailfnexecuteSYNC}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteSYNC.tex}} - -\newcommand{\sailfnexecuteMFCzero}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMFCzero.tex}} - -\newcommand{\sailfnexecuteHCF}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteHCF.tex}} - -\newcommand{\sailfnexecuteMTCzero}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteMTCzero.tex}} - -\newcommand{\sailfnexecuteTLBWI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteTLBWI.tex}} - -\newcommand{\sailfnexecuteTLBWR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteTLBWR.tex}} - -\newcommand{\sailfnexecuteTLBR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteTLBR.tex}} - -\newcommand{\sailfnexecuteTLBP}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteTLBP.tex}} - -\newcommand{\sailfnexecuteRDHWR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteRDHWR.tex}} - -\newcommand{\sailfnexecuteERET}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteERET.tex}} - -\newcommand{\sailfnexecuteCGetPerm}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetPerm.tex}} - -\newcommand{\sailfnexecuteCGetType}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetType.tex}} - -\newcommand{\sailfnexecuteCGetBase}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetBase.tex}} - -\newcommand{\sailfnexecuteCGetOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetOffset.tex}} - -\newcommand{\sailfnexecuteCGetLen}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetLen.tex}} - -\newcommand{\sailfnexecuteCGetTag}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetTag.tex}} - -\newcommand{\sailfnexecuteCGetSealed}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetSealed.tex}} - -\newcommand{\sailfnexecuteCGetAddr}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetAddr.tex}} - -\newcommand{\sailfnexecuteCGetPCC}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetPCC.tex}} - -\newcommand{\sailfnexecuteCGetPCCSetOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetPCCSetOffset.tex}} - -\newcommand{\sailfnexecuteCGetCause}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCGetCause.tex}} - -\newcommand{\sailfnexecuteCSetCause}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSetCause.tex}} - -\newcommand{\sailfnexecuteCReadHwr}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCReadHwr.tex}} - -\newcommand{\sailfnexecuteCWriteHwr}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCWriteHwr.tex}} - -\newcommand{\sailfnexecuteCAndPerm}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCAndPerm.tex}} - -\newcommand{\sailfnexecuteCToPtr}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCToPtr.tex}} - -\newcommand{\sailfnexecuteCSub}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSub.tex}} - -\newcommand{\sailfnexecuteCPtrCmp}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCPtrCmp.tex}} - -\newcommand{\sailfnexecuteCIncOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCIncOffset.tex}} - -\newcommand{\sailfnexecuteCIncOffsetImmediate}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCIncOffsetImmediate.tex}} - -\newcommand{\sailfnexecuteCSetOffset}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSetOffset.tex}} - -\newcommand{\sailfnexecuteCSetBounds}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSetBounds.tex}} - -\newcommand{\sailfnexecuteCSetBoundsImmediate}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSetBoundsImmediate.tex}} - -\newcommand{\sailfnexecuteCSetBoundsExact}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSetBoundsExact.tex}} - -\newcommand{\sailfnexecuteCClearTag}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCClearTag.tex}} - -\newcommand{\sailfnexecuteCMOVX}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCMOVX.tex}} - -\newcommand{\sailfnexecuteClearRegs}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteClearRegs.tex}} - -\newcommand{\sailfnexecuteCFromPtr}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCFromPtr.tex}} - -\newcommand{\sailfnexecuteCBuildCap}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCBuildCap.tex}} - -\newcommand{\sailfnexecuteCCopyType}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCCopyType.tex}} - -\newcommand{\sailfnexecuteCCheckPerm}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCCheckPerm.tex}} - -\newcommand{\sailfnexecuteCCheckType}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCCheckType.tex}} - -\newcommand{\sailfnexecuteCTestSubset}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCTestSubset.tex}} - -\newcommand{\sailfnexecuteCSeal}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSeal.tex}} - -\newcommand{\sailfnexecuteCCSeal}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCCSeal.tex}} - -\newcommand{\sailfnexecuteCUnseal}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCUnseal.tex}} - -\newcommand{\sailfnexecuteCCall}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCCall.tex}} - -\newcommand{\sailsailfnexecuteCCallv}{ \lstinputlisting[language=sail]{sail_latex/sailsailfnexecuteCCallv.tex}} - -\newcommand{\sailfnexecuteCReturn}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCReturn.tex}} - -\newcommand{\sailfnexecuteCBX}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCBX.tex}} - -\newcommand{\sailfnexecuteCBZ}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCBZ.tex}} - -\newcommand{\sailfnexecuteCJALR}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCJALR.tex}} - -\newcommand{\sailfnexecuteCLoad}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCLoad.tex}} - -\newcommand{\sailfnexecuteCStore}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCStore.tex}} - -\newcommand{\sailfnexecuteCSC}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCSC.tex}} - -\newcommand{\sailfnexecuteCLC}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCLC.tex}} - -\newcommand{\sailfnexecuteCtwoDump}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteCtwoDump.tex}} - -\newcommand{\sailfnexecuteRI}{ \lstinputlisting[language=sail]{sail_latex/sailfnexecuteRI.tex}} - - - -\newcommand{\sailsupportedinstructions}{\label{zsupportedzyinstructions} \lstinputlisting[language=sail]{sail_latex/sailsupportedinstructions.tex}} - -\newcommand{\sailfnsupportedinstructions}{\label{zsupportedzyinstructions} \lstinputlisting[language=sail]{sail_latex/sailfnsupportedinstructions.tex}} - diff --git a/cheri/sail_latex/sailAccessLevel.tex b/cheri/sail_latex/sailAccessLevel.tex deleted file mode 100644 index 9e7ad495..00000000 --- a/cheri/sail_latex/sailAccessLevel.tex +++ /dev/null @@ -1 +0,0 @@ -enum AccessLevel = {User, Supervisor, Kernel} diff --git a/cheri/sail_latex/sailAccessLevelofnum.tex b/cheri/sail_latex/sailAccessLevelofnum.tex deleted file mode 100644 index d958c3e0..00000000 --- a/cheri/sail_latex/sailAccessLevelofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val AccessLevel_of_num : forall ('e : Int), 0 <= 'e & 'e <= 2. atom('e) -> AccessLevel diff --git a/cheri/sail_latex/sailBitStr.tex b/cheri/sail_latex/sailBitStr.tex deleted file mode 100644 index a0d408ab..00000000 --- a/cheri/sail_latex/sailBitStr.tex +++ /dev/null @@ -1 +0,0 @@ -val BitStr = "string_of_bits" : forall 'n. #\hyperref[zbits]{bits}#('n) -> string diff --git a/cheri/sail_latex/sailCPtrCmpOp.tex b/cheri/sail_latex/sailCPtrCmpOp.tex deleted file mode 100644 index cb0a73ae..00000000 --- a/cheri/sail_latex/sailCPtrCmpOp.tex +++ /dev/null @@ -1,10 +0,0 @@ -enum CPtrCmpOp = { - CEQ, - CNE, - CLT, - CLE, - CLTU, - CLEU, - CEXEQ, - CNEXEQ -} diff --git a/cheri/sail_latex/sailCPtrCmpOpofnum.tex b/cheri/sail_latex/sailCPtrCmpOpofnum.tex deleted file mode 100644 index bd6ca31c..00000000 --- a/cheri/sail_latex/sailCPtrCmpOpofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val CPtrCmpOp_of_num : forall ('e : Int), 0 <= 'e & 'e <= 7. atom('e) -> CPtrCmpOp diff --git a/cheri/sail_latex/sailCapCauseReg.tex b/cheri/sail_latex/sailCapCauseReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailCapCauseReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailCapEx.tex b/cheri/sail_latex/sailCapEx.tex deleted file mode 100644 index 636c85c9..00000000 --- a/cheri/sail_latex/sailCapEx.tex +++ /dev/null @@ -1,25 +0,0 @@ -enum CapEx = { - CapEx_None, - CapEx_LengthViolation, - CapEx_TagViolation, - CapEx_SealViolation, - CapEx_TypeViolation, - CapEx_CallTrap, - CapEx_ReturnTrap, - CapEx_TSSUnderFlow, - CapEx_UserDefViolation, - CapEx_TLBNoStoreCap, - CapEx_InexactBounds, - CapEx_GlobalViolation, - CapEx_PermitExecuteViolation, - CapEx_PermitLoadViolation, - CapEx_PermitStoreViolation, - CapEx_PermitLoadCapViolation, - CapEx_PermitStoreCapViolation, - CapEx_PermitStoreLocalCapViolation, - CapEx_PermitSealViolation, - CapEx_AccessSystemRegsViolation, - CapEx_PermitCCallViolation, - CapEx_AccessCCallIDCViolation, - CapEx_PermitUnsealViolation -} diff --git a/cheri/sail_latex/sailCapExCode.tex b/cheri/sail_latex/sailCapExCode.tex deleted file mode 100644 index 3611e1b8..00000000 --- a/cheri/sail_latex/sailCapExCode.tex +++ /dev/null @@ -1 +0,0 @@ -val CapExCode : CapEx -> bits(8) diff --git a/cheri/sail_latex/sailCapExofnum.tex b/cheri/sail_latex/sailCapExofnum.tex deleted file mode 100644 index dec981a6..00000000 --- a/cheri/sail_latex/sailCapExofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val CapEx_of_num : forall ('e : Int), 0 <= 'e & 'e <= 22. atom('e) -> CapEx diff --git a/cheri/sail_latex/sailCapLen.tex b/cheri/sail_latex/sailCapLen.tex deleted file mode 100644 index 812f45ff..00000000 --- a/cheri/sail_latex/sailCapLen.tex +++ /dev/null @@ -1 +0,0 @@ -type CapLen = range(0, 2 ^ 65) diff --git a/cheri/sail_latex/sailCapReg.tex b/cheri/sail_latex/sailCapReg.tex deleted file mode 100644 index f217492a..00000000 --- a/cheri/sail_latex/sailCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -type CapReg = #\hyperref[zbits]{bits}#(257) diff --git a/cheri/sail_latex/sailCapStruct.tex b/cheri/sail_latex/sailCapStruct.tex deleted file mode 100644 index 4b9a3386..00000000 --- a/cheri/sail_latex/sailCapStruct.tex +++ /dev/null @@ -1,22 +0,0 @@ -struct CapStruct = { - tag : bool , - padding : #\hyperref[zbits]{bits}#(8) , - otype : #\hyperref[zbits]{bits}#(24), - uperms : #\hyperref[zbits]{bits}#(16), - perm_reserved11_14 : #\hyperref[zbits]{bits}#(4) , - access_system_regs : bool , - permit_unseal : bool , - permit_ccall : bool , - permit_seal : bool , - permit_store_local_cap : bool , - permit_store_cap : bool , - permit_load_cap : bool , - permit_store : bool , - permit_load : bool , - permit_execute : bool , - global : bool , - sealed : bool , - address : #\hyperref[zbits]{bits}#(64), - base : #\hyperref[zbits]{bits}#(64), - length : #\hyperref[zbits]{bits}#(64), -} diff --git a/cheri/sail_latex/sailCauseReg.tex b/cheri/sail_latex/sailCauseReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailCauseReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailClearRegSet.tex b/cheri/sail_latex/sailClearRegSet.tex deleted file mode 100644 index c04ea7d4..00000000 --- a/cheri/sail_latex/sailClearRegSet.tex +++ /dev/null @@ -1,6 +0,0 @@ -enum ClearRegSet = { -GPLo, -GPHi, -CLo, -CHi -} diff --git a/cheri/sail_latex/sailClearRegSetofnum.tex b/cheri/sail_latex/sailClearRegSetofnum.tex deleted file mode 100644 index c73d36d9..00000000 --- a/cheri/sail_latex/sailClearRegSetofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val ClearRegSet_of_num : forall ('e : Int), 0 <= 'e & 'e <= 3. atom('e) -> ClearRegSet diff --git a/cheri/sail_latex/sailComparison.tex b/cheri/sail_latex/sailComparison.tex deleted file mode 100644 index 083fc498..00000000 --- a/cheri/sail_latex/sailComparison.tex +++ /dev/null @@ -1,10 +0,0 @@ -enum Comparison = { - EQ, /* equal */ - NE, /* not equal */ - GE, /* signed greater than or equal */ - GEU,/* unsigned greater than or equal */ - GT, /* signed strictly greater than */ - LE, /* signed less than or equal */ - LT, /* signed strictly less than */ - LTU /* unsigned less than or qual */ -} diff --git a/cheri/sail_latex/sailComparisonofnum.tex b/cheri/sail_latex/sailComparisonofnum.tex deleted file mode 100644 index 02c9c48e..00000000 --- a/cheri/sail_latex/sailComparisonofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val Comparison_of_num : forall ('e : Int), 0 <= 'e & 'e <= 7. atom('e) -> Comparison diff --git a/cheri/sail_latex/sailContextReg.tex b/cheri/sail_latex/sailContextReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailContextReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailERETHook.tex b/cheri/sail_latex/sailERETHook.tex deleted file mode 100644 index 8eadde7b..00000000 --- a/cheri/sail_latex/sailERETHook.tex +++ /dev/null @@ -1 +0,0 @@ -val ERETHook : unit -> unit effect {rreg, wreg} diff --git a/cheri/sail_latex/sailException.tex b/cheri/sail_latex/sailException.tex deleted file mode 100644 index 800328ec..00000000 --- a/cheri/sail_latex/sailException.tex +++ /dev/null @@ -1,5 +0,0 @@ -enum Exception = -{ - Interrupt, TLBMod, TLBL, TLBS, AdEL, AdES, Sys, Bp, ResI, CpU, Ov, Tr, C2E, C2Trap, - XTLBRefillL, XTLBRefillS, XTLBInvL, XTLBInvS, MCheck -} diff --git a/cheri/sail_latex/sailExceptionCode.tex b/cheri/sail_latex/sailExceptionCode.tex deleted file mode 100644 index 395b9670..00000000 --- a/cheri/sail_latex/sailExceptionCode.tex +++ /dev/null @@ -1 +0,0 @@ -val ExceptionCode : Exception -> bits(5) diff --git a/cheri/sail_latex/sailExceptionofnum.tex b/cheri/sail_latex/sailExceptionofnum.tex deleted file mode 100644 index 394ae4e1..00000000 --- a/cheri/sail_latex/sailExceptionofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val Exception_of_num : forall ('e : Int), 0 <= 'e & 'e <= 18. atom('e) -> Exception diff --git a/cheri/sail_latex/sailMAX.tex b/cheri/sail_latex/sailMAX.tex deleted file mode 100644 index 07bace3b..00000000 --- a/cheri/sail_latex/sailMAX.tex +++ /dev/null @@ -1 +0,0 @@ -val MAX : forall 'n. atom('n) -> atom(2 ^ 'n - 1) effect pure diff --git a/cheri/sail_latex/sailMEMea.tex b/cheri/sail_latex/sailMEMea.tex deleted file mode 100644 index c5225019..00000000 --- a/cheri/sail_latex/sailMEMea.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEMea = {lem: "MEMea"} : forall 'n. - ( #\hyperref[zbits]{bits}#(64) , atom('n)) -> unit effect { eamem } diff --git a/cheri/sail_latex/sailMEMeaconditional.tex b/cheri/sail_latex/sailMEMeaconditional.tex deleted file mode 100644 index d966b986..00000000 --- a/cheri/sail_latex/sailMEMeaconditional.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEMea_conditional = {lem: "MEMea_conditional"} : forall 'n. - ( #\hyperref[zbits]{bits}#(64) , atom('n)) -> unit effect { eamem } diff --git a/cheri/sail_latex/sailMEMr.tex b/cheri/sail_latex/sailMEMr.tex deleted file mode 100644 index 75ddc94c..00000000 --- a/cheri/sail_latex/sailMEMr.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEMr = {lem: "MEMr"} : forall 'n, 'n >= 0. - ( #\hyperref[zbits]{bits}#(64) , atom('n) ) -> (#\hyperref[zbits]{bits}#(8 * 'n)) effect { rmem } diff --git a/cheri/sail_latex/sailMEMrreserve.tex b/cheri/sail_latex/sailMEMrreserve.tex deleted file mode 100644 index 11b4f3db..00000000 --- a/cheri/sail_latex/sailMEMrreserve.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEMr_reserve = {lem: "MEMr_reserve"} : forall 'n, 'n >= 0. - ( #\hyperref[zbits]{bits}#(64) , atom('n) ) -> (#\hyperref[zbits]{bits}#(8 * 'n)) effect { rmem } diff --git a/cheri/sail_latex/sailMEMrreservewrapper.tex b/cheri/sail_latex/sailMEMrreservewrapper.tex deleted file mode 100644 index b12713a2..00000000 --- a/cheri/sail_latex/sailMEMrreservewrapper.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMr_reserve_wrapper : forall 'n, 1 <= 'n <= 8 . ( #\hyperref[zbits]{bits}#(64) , atom('n) ) -> (#\hyperref[zbits]{bits}#(8 * 'n)) effect { rmem } diff --git a/cheri/sail_latex/sailMEMrtag.tex b/cheri/sail_latex/sailMEMrtag.tex deleted file mode 100644 index 9bcda0f4..00000000 --- a/cheri/sail_latex/sailMEMrtag.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMr_tag = "read_tag_bool" : #\hyperref[zbits]{bits}#(64) -> bool effect { rmemt } diff --git a/cheri/sail_latex/sailMEMrtagged.tex b/cheri/sail_latex/sailMEMrtagged.tex deleted file mode 100644 index 92c90c7b..00000000 --- a/cheri/sail_latex/sailMEMrtagged.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMr_tagged : #\hyperref[zbits]{bits}#(64) -> (bool, #\hyperref[zbits]{bits}#('cap_size * 8)) effect { escape, rmem, rmemt } diff --git a/cheri/sail_latex/sailMEMrtaggedreserve.tex b/cheri/sail_latex/sailMEMrtaggedreserve.tex deleted file mode 100644 index fb080251..00000000 --- a/cheri/sail_latex/sailMEMrtaggedreserve.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMr_tagged_reserve : #\hyperref[zbits]{bits}#(64) -> (bool, #\hyperref[zbits]{bits}#('cap_size * 8)) effect { escape, rmem, rmemt } diff --git a/cheri/sail_latex/sailMEMrwrapper.tex b/cheri/sail_latex/sailMEMrwrapper.tex deleted file mode 100644 index 7c8ce2fd..00000000 --- a/cheri/sail_latex/sailMEMrwrapper.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMr_wrapper : forall 'n, 1 <= 'n <= 8 . (#\hyperref[zbits]{bits}#(64), atom('n)) -> #\hyperref[zbits]{bits}#(8*'n) effect {rmem, rreg, wreg} diff --git a/cheri/sail_latex/sailMEMsync.tex b/cheri/sail_latex/sailMEMsync.tex deleted file mode 100644 index 5a66f5db..00000000 --- a/cheri/sail_latex/sailMEMsync.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEM_sync = {lem: "MEM_sync"} : - unit -> unit effect { barr } diff --git a/cheri/sail_latex/sailMEMval.tex b/cheri/sail_latex/sailMEMval.tex deleted file mode 100644 index 67c34697..00000000 --- a/cheri/sail_latex/sailMEMval.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEMval = {lem: "MEMval"} : forall 'n. - ( #\hyperref[zbits]{bits}#(64) , atom('n), #\hyperref[zbits]{bits}#(8*'n)) -> unit effect { wmv } diff --git a/cheri/sail_latex/sailMEMvalconditional.tex b/cheri/sail_latex/sailMEMvalconditional.tex deleted file mode 100644 index 9e0029e5..00000000 --- a/cheri/sail_latex/sailMEMvalconditional.tex +++ /dev/null @@ -1,2 +0,0 @@ -val MEMval_conditional = {lem: "MEMval_conditional"} : forall 'n. - ( #\hyperref[zbits]{bits}#(64) , atom('n), #\hyperref[zbits]{bits}#(8*'n)) -> bool effect { wmv } diff --git a/cheri/sail_latex/sailMEMwconditionalwrapper.tex b/cheri/sail_latex/sailMEMwconditionalwrapper.tex deleted file mode 100644 index 1d7cb3e8..00000000 --- a/cheri/sail_latex/sailMEMwconditionalwrapper.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMw_conditional_wrapper : forall 'n, 'n >= 1. (#\hyperref[zbits]{bits}#(64), atom('n), #\hyperref[zbits]{bits}#(8 * 'n)) -> bool effect {escape, wmv, wmvt, eamem} diff --git a/cheri/sail_latex/sailMEMwtag.tex b/cheri/sail_latex/sailMEMwtag.tex deleted file mode 100644 index 1319a340..00000000 --- a/cheri/sail_latex/sailMEMwtag.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMw_tag = "write_tag_bool" : (#\hyperref[zbits]{bits}#(64) , bool) -> unit effect { wmvt } diff --git a/cheri/sail_latex/sailMEMwtagged.tex b/cheri/sail_latex/sailMEMwtagged.tex deleted file mode 100644 index 4f8fd683..00000000 --- a/cheri/sail_latex/sailMEMwtagged.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMw_tagged : (#\hyperref[zbits]{bits}#(64), bool, #\hyperref[zbits]{bits}#('cap_size * 8)) -> unit effect { escape, eamem, wmv, wmvt } diff --git a/cheri/sail_latex/sailMEMwtaggedconditional.tex b/cheri/sail_latex/sailMEMwtaggedconditional.tex deleted file mode 100644 index f5ef7e17..00000000 --- a/cheri/sail_latex/sailMEMwtaggedconditional.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMw_tagged_conditional : (#\hyperref[zbits]{bits}#(64), bool, #\hyperref[zbits]{bits}#('cap_size * 8)) -> bool effect { escape, eamem, wmv, wmvt } diff --git a/cheri/sail_latex/sailMEMwwrapper.tex b/cheri/sail_latex/sailMEMwwrapper.tex deleted file mode 100644 index db438818..00000000 --- a/cheri/sail_latex/sailMEMwwrapper.tex +++ /dev/null @@ -1 +0,0 @@ -val MEMw_wrapper : forall 'n, 'n >= 1. (#\hyperref[zbits]{bits}#(64), atom('n), #\hyperref[zbits]{bits}#(8 * 'n)) -> unit effect {escape, wmv, wmvt, wreg, eamem} diff --git a/cheri/sail_latex/sailMIPSread.tex b/cheri/sail_latex/sailMIPSread.tex deleted file mode 100644 index 92ca59cc..00000000 --- a/cheri/sail_latex/sailMIPSread.tex +++ /dev/null @@ -1 +0,0 @@ -val __MIPS_read : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#(64), atom('n)) -> #\hyperref[zbits]{bits}#(8 * 'n) effect {rmem} diff --git a/cheri/sail_latex/sailMIPSwrite.tex b/cheri/sail_latex/sailMIPSwrite.tex deleted file mode 100644 index cc67fa20..00000000 --- a/cheri/sail_latex/sailMIPSwrite.tex +++ /dev/null @@ -1 +0,0 @@ -val __MIPS_write : forall 'n. (#\hyperref[zbits]{bits}#(64), atom('n), #\hyperref[zbits]{bits}#(8 * 'n)) -> unit effect {wmv} diff --git a/cheri/sail_latex/sailMemAccessType.tex b/cheri/sail_latex/sailMemAccessType.tex deleted file mode 100644 index 436b40bc..00000000 --- a/cheri/sail_latex/sailMemAccessType.tex +++ /dev/null @@ -1 +0,0 @@ -enum MemAccessType = {Instruction, LoadData, StoreData} diff --git a/cheri/sail_latex/sailMemAccessTypeofnum.tex b/cheri/sail_latex/sailMemAccessTypeofnum.tex deleted file mode 100644 index 9147f6e3..00000000 --- a/cheri/sail_latex/sailMemAccessTypeofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val MemAccessType_of_num : forall ('e : Int), 0 <= 'e & 'e <= 2. atom('e) -> MemAccessType diff --git a/cheri/sail_latex/sailMkCapCauseReg.tex b/cheri/sail_latex/sailMkCapCauseReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkCapCauseReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkCauseReg.tex b/cheri/sail_latex/sailMkCauseReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkCauseReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkContextReg.tex b/cheri/sail_latex/sailMkContextReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkContextReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkStatusReg.tex b/cheri/sail_latex/sailMkStatusReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkStatusReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkTLBEntry.tex b/cheri/sail_latex/sailMkTLBEntry.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkTLBEntry.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkTLBEntryHiReg.tex b/cheri/sail_latex/sailMkTLBEntryHiReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkTLBEntryHiReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkTLBEntryLoReg.tex b/cheri/sail_latex/sailMkTLBEntryLoReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkTLBEntryLoReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailMkXContextReg.tex b/cheri/sail_latex/sailMkXContextReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailMkXContextReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailNotWordVal.tex b/cheri/sail_latex/sailNotWordVal.tex deleted file mode 100644 index e6689c14..00000000 --- a/cheri/sail_latex/sailNotWordVal.tex +++ /dev/null @@ -1 +0,0 @@ -val NotWordVal : #\hyperref[zbits]{bits}#(64) -> bool effect pure diff --git a/cheri/sail_latex/sailReadRAM.tex b/cheri/sail_latex/sailReadRAM.tex deleted file mode 100644 index 68d629a6..00000000 --- a/cheri/sail_latex/sailReadRAM.tex +++ /dev/null @@ -1,2 +0,0 @@ -val __ReadRAM = "read_ram" : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), #\hyperref[zbits]{bits}#('m), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#(8 * 'n) effect {rmem} diff --git a/cheri/sail_latex/sailSignalException.tex b/cheri/sail_latex/sailSignalException.tex deleted file mode 100644 index 44205587..00000000 --- a/cheri/sail_latex/sailSignalException.tex +++ /dev/null @@ -1 +0,0 @@ -val SignalException : forall ('o : Type) . Exception -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailSignalExceptionBadAddr.tex b/cheri/sail_latex/sailSignalExceptionBadAddr.tex deleted file mode 100644 index f54e77e7..00000000 --- a/cheri/sail_latex/sailSignalExceptionBadAddr.tex +++ /dev/null @@ -1 +0,0 @@ -val SignalExceptionBadAddr : forall ('o : Type) . (Exception, #\hyperref[zbits]{bits}#(64)) -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailSignalExceptionMIPS.tex b/cheri/sail_latex/sailSignalExceptionMIPS.tex deleted file mode 100644 index ce88e5d6..00000000 --- a/cheri/sail_latex/sailSignalExceptionMIPS.tex +++ /dev/null @@ -1 +0,0 @@ -val SignalExceptionMIPS : forall ('o : Type) . (Exception, #\hyperref[zbits]{bits}#(64)) -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailSignalExceptionTLB.tex b/cheri/sail_latex/sailSignalExceptionTLB.tex deleted file mode 100644 index 08036f99..00000000 --- a/cheri/sail_latex/sailSignalExceptionTLB.tex +++ /dev/null @@ -1 +0,0 @@ -val SignalExceptionTLB : forall ('o : Type) . (Exception, #\hyperref[zbits]{bits}#(64)) -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailStatusReg.tex b/cheri/sail_latex/sailStatusReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailStatusReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailTLBEntry.tex b/cheri/sail_latex/sailTLBEntry.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailTLBEntry.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailTLBEntryHiReg.tex b/cheri/sail_latex/sailTLBEntryHiReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailTLBEntryHiReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailTLBEntryLoReg.tex b/cheri/sail_latex/sailTLBEntryLoReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailTLBEntryLoReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailTLBIndexT.tex b/cheri/sail_latex/sailTLBIndexT.tex deleted file mode 100644 index c51bd6bb..00000000 --- a/cheri/sail_latex/sailTLBIndexT.tex +++ /dev/null @@ -1 +0,0 @@ -type TLBIndexT = (#\hyperref[zbits]{bits}#(6)) diff --git a/cheri/sail_latex/sailTLBTranslate.tex b/cheri/sail_latex/sailTLBTranslate.tex deleted file mode 100644 index d09725f9..00000000 --- a/cheri/sail_latex/sailTLBTranslate.tex +++ /dev/null @@ -1 +0,0 @@ -val TLBTranslate : (#\hyperref[zbits]{bits}#(64), MemAccessType) -> #\hyperref[zbits]{bits}#(64) effect {rreg, wreg, escape, undef} diff --git a/cheri/sail_latex/sailTLBTranslateC.tex b/cheri/sail_latex/sailTLBTranslateC.tex deleted file mode 100644 index 0d99ab7e..00000000 --- a/cheri/sail_latex/sailTLBTranslateC.tex +++ /dev/null @@ -1 +0,0 @@ -val TLBTranslateC : (#\hyperref[zbits]{bits}#(64), MemAccessType) -> (#\hyperref[zbits]{bits}#(64), bool) effect {escape, rreg, undef, wreg} diff --git a/cheri/sail_latex/sailTLBTranslatetwo.tex b/cheri/sail_latex/sailTLBTranslatetwo.tex deleted file mode 100644 index 310675f4..00000000 --- a/cheri/sail_latex/sailTLBTranslatetwo.tex +++ /dev/null @@ -1 +0,0 @@ -val TLBTranslate2 : (#\hyperref[zbits]{bits}#(64), MemAccessType) -> (#\hyperref[zbits]{bits}#(64), bool) effect {rreg, wreg, undef, escape} diff --git a/cheri/sail_latex/sailTLBWriteEntry.tex b/cheri/sail_latex/sailTLBWriteEntry.tex deleted file mode 100644 index 84d4fa70..00000000 --- a/cheri/sail_latex/sailTLBWriteEntry.tex +++ /dev/null @@ -1 +0,0 @@ -val TLBWriteEntry : TLBIndexT -> unit effect {rreg, wreg, escape} diff --git a/cheri/sail_latex/sailTranslatePC.tex b/cheri/sail_latex/sailTranslatePC.tex deleted file mode 100644 index c962c7e1..00000000 --- a/cheri/sail_latex/sailTranslatePC.tex +++ /dev/null @@ -1 +0,0 @@ -val TranslatePC : #\hyperref[zbits]{bits}#(64) -> #\hyperref[zbits]{bits}#(64) effect {rreg, wreg, escape, undef} diff --git a/cheri/sail_latex/sailWordType.tex b/cheri/sail_latex/sailWordType.tex deleted file mode 100644 index 632efe95..00000000 --- a/cheri/sail_latex/sailWordType.tex +++ /dev/null @@ -1 +0,0 @@ -enum WordType = { B, H, W, D} diff --git a/cheri/sail_latex/sailWordTypeUnaligned.tex b/cheri/sail_latex/sailWordTypeUnaligned.tex deleted file mode 100644 index 3724733e..00000000 --- a/cheri/sail_latex/sailWordTypeUnaligned.tex +++ /dev/null @@ -1 +0,0 @@ -enum WordTypeUnaligned = { WL, WR, DL, DR } diff --git a/cheri/sail_latex/sailWordTypeUnalignedofnum.tex b/cheri/sail_latex/sailWordTypeUnalignedofnum.tex deleted file mode 100644 index a36d9748..00000000 --- a/cheri/sail_latex/sailWordTypeUnalignedofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val WordTypeUnaligned_of_num : forall ('e : Int), 0 <= 'e & 'e <= 3. atom('e) -> WordTypeUnaligned diff --git a/cheri/sail_latex/sailWordTypeofnum.tex b/cheri/sail_latex/sailWordTypeofnum.tex deleted file mode 100644 index 85872610..00000000 --- a/cheri/sail_latex/sailWordTypeofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val WordType_of_num : forall ('e : Int), 0 <= 'e & 'e <= 3. atom('e) -> WordType diff --git a/cheri/sail_latex/sailWriteRAM.tex b/cheri/sail_latex/sailWriteRAM.tex deleted file mode 100644 index 2ed4aca2..00000000 --- a/cheri/sail_latex/sailWriteRAM.tex +++ /dev/null @@ -1,2 +0,0 @@ -val __WriteRAM = "write_ram" : forall 'n 'm. - (atom('m), atom('n), #\hyperref[zbits]{bits}#('m), #\hyperref[zbits]{bits}#('m), #\hyperref[zbits]{bits}#(8 * 'n)) -> bool effect {wmv} diff --git a/cheri/sail_latex/sailXContextReg.tex b/cheri/sail_latex/sailXContextReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailXContextReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailabsatom.tex b/cheri/sail_latex/sailabsatom.tex deleted file mode 100644 index 5164ef32..00000000 --- a/cheri/sail_latex/sailabsatom.tex +++ /dev/null @@ -1,7 +0,0 @@ -val abs_atom = { - smt : "abs", - ocaml: "abs_int", - lem: "abs_int", - c: "abs_int", - coq: "abs_with_eq" -} : forall 'n. atom('n) -> {'o, 'o = #\hyperref[zabszyatom]{abs\_atom}#('n). atom('o)} diff --git a/cheri/sail_latex/sailabsint.tex b/cheri/sail_latex/sailabsint.tex deleted file mode 100644 index d3b67cfb..00000000 --- a/cheri/sail_latex/sailabsint.tex +++ /dev/null @@ -1,6 +0,0 @@ -val abs_int = { - smt : "abs", - ocaml: "abs_int", - lem: "abs_int", - coq: "Z.abs" -} : (int, int) -> int diff --git a/cheri/sail_latex/sailaddatom.tex b/cheri/sail_latex/sailaddatom.tex deleted file mode 100644 index 8b6ac810..00000000 --- a/cheri/sail_latex/sailaddatom.tex +++ /dev/null @@ -1,2 +0,0 @@ -val add_atom = {ocaml: "add_int", lem: "integerAdd", c: "add_int", coq: "Z.add"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n + 'm) diff --git a/cheri/sail_latex/sailaddbits.tex b/cheri/sail_latex/sailaddbits.tex deleted file mode 100644 index 95f653d1..00000000 --- a/cheri/sail_latex/sailaddbits.tex +++ /dev/null @@ -1,6 +0,0 @@ -val add_bits = { - ocaml: "add_vec", - lem: "add_vec", - c: "add_bits", - coq: "add_vec" -} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailaddbitsint.tex b/cheri/sail_latex/sailaddbitsint.tex deleted file mode 100644 index ee9a8aa2..00000000 --- a/cheri/sail_latex/sailaddbitsint.tex +++ /dev/null @@ -1,6 +0,0 @@ -val add_bits_int = { - ocaml: "add_vec_int", - lem: "add_vec_int", - c: "add_bits_int", - coq: "add_vec_int" -} : forall 'n. (#\hyperref[zbits]{bits}#('n), int) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailaddint.tex b/cheri/sail_latex/sailaddint.tex deleted file mode 100644 index 9fe5b078..00000000 --- a/cheri/sail_latex/sailaddint.tex +++ /dev/null @@ -1 +0,0 @@ -val add_int = {ocaml: "add_int", lem: "integerAdd", c: "add_int", coq: "Z.add"} : (int, int) -> int diff --git a/cheri/sail_latex/sailaddrWrapper.tex b/cheri/sail_latex/sailaddrWrapper.tex deleted file mode 100644 index 506f9f99..00000000 --- a/cheri/sail_latex/sailaddrWrapper.tex +++ /dev/null @@ -1 +0,0 @@ -val addrWrapper : (#\hyperref[zbits]{bits}#(64), MemAccessType, WordType) -> #\hyperref[zbits]{bits}#(64) effect {rreg, wreg, escape} diff --git a/cheri/sail_latex/sailaddrWrapperUnaligned.tex b/cheri/sail_latex/sailaddrWrapperUnaligned.tex deleted file mode 100644 index bb266a52..00000000 --- a/cheri/sail_latex/sailaddrWrapperUnaligned.tex +++ /dev/null @@ -1 +0,0 @@ -val addrWrapperUnaligned : (#\hyperref[zbits]{bits}#(64), MemAccessType, WordTypeUnaligned) -> #\hyperref[zbits]{bits}#(64) effect {rreg, wreg, escape} diff --git a/cheri/sail_latex/sailaddrange.tex b/cheri/sail_latex/sailaddrange.tex deleted file mode 100644 index fbf498b1..00000000 --- a/cheri/sail_latex/sailaddrange.tex +++ /dev/null @@ -1,2 +0,0 @@ -val add_range = {ocaml: "add_int", lem: "integerAdd", coq: "add_range", c: "add_int"} : forall 'n 'm 'o 'p. - (range('n, 'm), range('o, 'p)) -> range('n + 'o, 'm + 'p) diff --git a/cheri/sail_latex/sailaddvec.tex b/cheri/sail_latex/sailaddvec.tex deleted file mode 100644 index bb625afe..00000000 --- a/cheri/sail_latex/sailaddvec.tex +++ /dev/null @@ -1 +0,0 @@ -val add_vec = "add_vec" : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailaddvecint.tex b/cheri/sail_latex/sailaddvecint.tex deleted file mode 100644 index 189ad4aa..00000000 --- a/cheri/sail_latex/sailaddvecint.tex +++ /dev/null @@ -1 +0,0 @@ -val add_vec_int = "add_vec_int" : forall 'n. (#\hyperref[zbits]{bits}#('n), int) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailandbits.tex b/cheri/sail_latex/sailandbits.tex deleted file mode 100644 index 8e35bd5b..00000000 --- a/cheri/sail_latex/sailandbits.tex +++ /dev/null @@ -1 +0,0 @@ -val and_bits = {c:"and_bits", _: "and_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailandbool.tex b/cheri/sail_latex/sailandbool.tex deleted file mode 100644 index 926dce9f..00000000 --- a/cheri/sail_latex/sailandbool.tex +++ /dev/null @@ -1 +0,0 @@ -val and_bool = {coq: "andb", _: "and_bool"} : (bool, bool) -> bool diff --git a/cheri/sail_latex/sailappend.tex b/cheri/sail_latex/sailappend.tex deleted file mode 100644 index 56c12116..00000000 --- a/cheri/sail_latex/sailappend.tex +++ /dev/null @@ -1 +0,0 @@ -overload append = {bitvector_concat}
\ No newline at end of file diff --git a/cheri/sail_latex/sailappendsixfour.tex b/cheri/sail_latex/sailappendsixfour.tex deleted file mode 100644 index 633593b3..00000000 --- a/cheri/sail_latex/sailappendsixfour.tex +++ /dev/null @@ -1 +0,0 @@ -val "append_64" : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#(64)) -> #\hyperref[zbits]{bits}#('n + 64) diff --git a/cheri/sail_latex/sailbits.tex b/cheri/sail_latex/sailbits.tex deleted file mode 100644 index 88255b5a..00000000 --- a/cheri/sail_latex/sailbits.tex +++ /dev/null @@ -1 +0,0 @@ -type #\hyperref[zbits]{bits}# ('n : Int) = vector('n, dec, bit) diff --git a/cheri/sail_latex/sailbitstobool.tex b/cheri/sail_latex/sailbitstobool.tex deleted file mode 100644 index 17cb3483..00000000 --- a/cheri/sail_latex/sailbitstobool.tex +++ /dev/null @@ -1 +0,0 @@ -val cast bits_to_bool : #\hyperref[zbits]{bits}#(1) -> bool diff --git a/cheri/sail_latex/sailbittobool.tex b/cheri/sail_latex/sailbittobool.tex deleted file mode 100644 index 13a2dfb8..00000000 --- a/cheri/sail_latex/sailbittobool.tex +++ /dev/null @@ -1 +0,0 @@ -val cast bit_to_bool : bit -> bool diff --git a/cheri/sail_latex/sailbitvectoraccess.tex b/cheri/sail_latex/sailbitvectoraccess.tex deleted file mode 100644 index 4bb98eb8..00000000 --- a/cheri/sail_latex/sailbitvectoraccess.tex +++ /dev/null @@ -1,6 +0,0 @@ -val bitvector_access = { - ocaml: "access", - lem: "access_vec_dec", - coq: "access_vec_dec", - c: "vector_access" -} : forall ('n : Int), 'n >= 0. (#\hyperref[zbits]{bits}#('n), int) -> bit diff --git a/cheri/sail_latex/sailbitvectorconcat.tex b/cheri/sail_latex/sailbitvectorconcat.tex deleted file mode 100644 index afc03901..00000000 --- a/cheri/sail_latex/sailbitvectorconcat.tex +++ /dev/null @@ -1,2 +0,0 @@ -val bitvector_concat = {ocaml: "append", lem: "concat_vec", c: "append", coq: "concat_vec"} : forall ('n : Int) ('m : Int). - (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n + 'm) diff --git a/cheri/sail_latex/sailbitvectorlength.tex b/cheri/sail_latex/sailbitvectorlength.tex deleted file mode 100644 index ac601acd..00000000 --- a/cheri/sail_latex/sailbitvectorlength.tex +++ /dev/null @@ -1 +0,0 @@ -val bitvector_length = {coq: "length_mword", _:"length"} : forall 'n. #\hyperref[zbits]{bits}#('n) -> atom('n) diff --git a/cheri/sail_latex/sailbitvectorupdate.tex b/cheri/sail_latex/sailbitvectorupdate.tex deleted file mode 100644 index 6524146e..00000000 --- a/cheri/sail_latex/sailbitvectorupdate.tex +++ /dev/null @@ -1,6 +0,0 @@ -val bitvector_update = { - ocaml: "update", - lem: "update_vec_dec", - coq: "update_vec_dec", - c: "vector_update" -} : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('n), int, bit) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailbooltobits.tex b/cheri/sail_latex/sailbooltobits.tex deleted file mode 100644 index 711ab763..00000000 --- a/cheri/sail_latex/sailbooltobits.tex +++ /dev/null @@ -1 +0,0 @@ -val cast bool_to_bits : bool -> #\hyperref[zbits]{bits}#(1) diff --git a/cheri/sail_latex/sailcapRegToCapStruct.tex b/cheri/sail_latex/sailcapRegToCapStruct.tex deleted file mode 100644 index bd64d554..00000000 --- a/cheri/sail_latex/sailcapRegToCapStruct.tex +++ /dev/null @@ -1 +0,0 @@ -val capRegToCapStruct : CapReg -> CapStruct diff --git a/cheri/sail_latex/sailcapStructToCapReg.tex b/cheri/sail_latex/sailcapStructToCapReg.tex deleted file mode 100644 index b5409845..00000000 --- a/cheri/sail_latex/sailcapStructToCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -val capStructToCapReg : CapStruct -> CapReg diff --git a/cheri/sail_latex/sailcapStructToMemBits.tex b/cheri/sail_latex/sailcapStructToMemBits.tex deleted file mode 100644 index 36f3a22b..00000000 --- a/cheri/sail_latex/sailcapStructToMemBits.tex +++ /dev/null @@ -1 +0,0 @@ -val capStructToMemBits : CapStruct -> bits(256) diff --git a/cheri/sail_latex/sailcapStructToMemBitstwofivesix.tex b/cheri/sail_latex/sailcapStructToMemBitstwofivesix.tex deleted file mode 100644 index dacd98f8..00000000 --- a/cheri/sail_latex/sailcapStructToMemBitstwofivesix.tex +++ /dev/null @@ -1 +0,0 @@ -val capStructToMemBits256 : CapStruct -> bits(256) diff --git a/cheri/sail_latex/sailcapToString.tex b/cheri/sail_latex/sailcapToString.tex deleted file mode 100644 index 554d4320..00000000 --- a/cheri/sail_latex/sailcapToString.tex +++ /dev/null @@ -1 +0,0 @@ -val capToString : CapStruct -> string effect {escape} diff --git a/cheri/sail_latex/sailcastunitvec.tex b/cheri/sail_latex/sailcastunitvec.tex deleted file mode 100644 index e0391ded..00000000 --- a/cheri/sail_latex/sailcastunitvec.tex +++ /dev/null @@ -1 +0,0 @@ -val cast cast_unit_vec : bit -> #\hyperref[zbits]{bits}#(1) diff --git a/cheri/sail_latex/sailcheckCPtwousable.tex b/cheri/sail_latex/sailcheckCPtwousable.tex deleted file mode 100644 index bfdca829..00000000 --- a/cheri/sail_latex/sailcheckCPtwousable.tex +++ /dev/null @@ -1 +0,0 @@ -val checkCP2usable : unit -> unit effect {rreg, wreg, escape} diff --git a/cheri/sail_latex/sailcheckCPzeroAccess.tex b/cheri/sail_latex/sailcheckCPzeroAccess.tex deleted file mode 100644 index facf1a49..00000000 --- a/cheri/sail_latex/sailcheckCPzeroAccess.tex +++ /dev/null @@ -1 +0,0 @@ -val checkCP0Access : unit->unit effect{escape, rreg, wreg} diff --git a/cheri/sail_latex/sailcheckDDCPerms.tex b/cheri/sail_latex/sailcheckDDCPerms.tex deleted file mode 100644 index f8598091..00000000 --- a/cheri/sail_latex/sailcheckDDCPerms.tex +++ /dev/null @@ -1 +0,0 @@ -val checkDDCPerms : (CapStruct, MemAccessType) -> unit effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailcompare.tex b/cheri/sail_latex/sailcompare.tex deleted file mode 100644 index 487ee094..00000000 --- a/cheri/sail_latex/sailcompare.tex +++ /dev/null @@ -1 +0,0 @@ -val compare : (Comparison, #\hyperref[zbits]{bits}#(64), #\hyperref[zbits]{bits}#(64)) -> bool diff --git a/cheri/sail_latex/sailconcatstr.tex b/cheri/sail_latex/sailconcatstr.tex deleted file mode 100644 index 07556728..00000000 --- a/cheri/sail_latex/sailconcatstr.tex +++ /dev/null @@ -1 +0,0 @@ -val concat_str = {lem: "stringAppend", coq: "String.append", _: "concat_str"} : (string, string) -> string diff --git a/cheri/sail_latex/sailcptwonextpc.tex b/cheri/sail_latex/sailcptwonextpc.tex deleted file mode 100644 index dca02a22..00000000 --- a/cheri/sail_latex/sailcptwonextpc.tex +++ /dev/null @@ -1 +0,0 @@ -val cp2_next_pc: unit -> unit effect {rreg, wreg} diff --git a/cheri/sail_latex/saildecode.tex b/cheri/sail_latex/saildecode.tex deleted file mode 100644 index 0dc95714..00000000 --- a/cheri/sail_latex/saildecode.tex +++ /dev/null @@ -1 +0,0 @@ -val decode : #\hyperref[zbits]{bits}#(32) -> #\hyperref[zoption]{option}#(ast) effect pure diff --git a/cheri/sail_latex/saildecodefailure.tex b/cheri/sail_latex/saildecodefailure.tex deleted file mode 100644 index 454da4c5..00000000 --- a/cheri/sail_latex/saildecodefailure.tex +++ /dev/null @@ -1,6 +0,0 @@ -enum decode_failure = { - no_matching_pattern, - unsupported_instruction, - illegal_instruction, - internal_error -} diff --git a/cheri/sail_latex/saildecodefailureofnum.tex b/cheri/sail_latex/saildecodefailureofnum.tex deleted file mode 100644 index 318b7b9d..00000000 --- a/cheri/sail_latex/saildecodefailureofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val decode_failure_of_num : forall ('e : Int), 0 <= 'e & 'e <= 3. atom('e) -> decode_failure diff --git a/cheri/sail_latex/saildiv.tex b/cheri/sail_latex/saildiv.tex deleted file mode 100644 index 58318fe9..00000000 --- a/cheri/sail_latex/saildiv.tex +++ /dev/null @@ -1,7 +0,0 @@ -val div = { - smt: "div", - ocaml: "quotient", - lem: "integerDiv", - c: "tdiv_int", - coq: "div_with_eq" -} : forall 'n 'm. (atom('n), atom('m)) -> {'o, 'o = #\hyperref[zdiv]{div}#('n, 'm). atom('o)} diff --git a/cheri/sail_latex/saildivint.tex b/cheri/sail_latex/saildivint.tex deleted file mode 100644 index 34ae6121..00000000 --- a/cheri/sail_latex/saildivint.tex +++ /dev/null @@ -1,7 +0,0 @@ -val div_int = { - smt: "div", - ocaml: "quotient", - lem: "integerDiv", - c: "tdiv_int", - coq: "Z.quot" -} : (int, int) -> int diff --git a/cheri/sail_latex/saildumpcptwostate.tex b/cheri/sail_latex/saildumpcptwostate.tex deleted file mode 100644 index 46ee6818..00000000 --- a/cheri/sail_latex/saildumpcptwostate.tex +++ /dev/null @@ -1 +0,0 @@ -val dump_cp2_state : unit -> unit effect {rreg, escape} diff --git a/cheri/sail_latex/saileqanything.tex b/cheri/sail_latex/saileqanything.tex deleted file mode 100644 index 9b5d3c92..00000000 --- a/cheri/sail_latex/saileqanything.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_anything = {ocaml: "(#\hyperref[zfun]{fun}# (x, y) -> x = y)", lem: "eq", coq: "generic_eq", _:"eq_anything"} : forall ('a : Type). ('a, 'a) -> bool diff --git a/cheri/sail_latex/saileqatom.tex b/cheri/sail_latex/saileqatom.tex deleted file mode 100644 index 0325ab15..00000000 --- a/cheri/sail_latex/saileqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_atom = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latex/saileqbit.tex b/cheri/sail_latex/saileqbit.tex deleted file mode 100644 index 205d3436..00000000 --- a/cheri/sail_latex/saileqbit.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_bit = { lem : "eq", _ : "eq_bit" } : (bit, bit) -> bool diff --git a/cheri/sail_latex/saileqbits.tex b/cheri/sail_latex/saileqbits.tex deleted file mode 100644 index e78ed19a..00000000 --- a/cheri/sail_latex/saileqbits.tex +++ /dev/null @@ -1,6 +0,0 @@ -val eq_bits = { - ocaml: "eq_list", - lem: "eq_vec", - c: "eq_bits", - coq: "eq_vec" -} : forall 'n. (vector('n, dec, bit), vector('n, dec, bit)) -> bool diff --git a/cheri/sail_latex/saileqbittwo.tex b/cheri/sail_latex/saileqbittwo.tex deleted file mode 100644 index 59353940..00000000 --- a/cheri/sail_latex/saileqbittwo.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_bit2 = "eq_bit" : (bit, bit) -> bool diff --git a/cheri/sail_latex/saileqbool.tex b/cheri/sail_latex/saileqbool.tex deleted file mode 100644 index 4d2c346b..00000000 --- a/cheri/sail_latex/saileqbool.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_bool = {ocaml: "eq_bool", lem: "eq", c: "eq_bool", coq: "Bool.eqb"} : (bool, bool) -> bool diff --git a/cheri/sail_latex/saileqint.tex b/cheri/sail_latex/saileqint.tex deleted file mode 100644 index 4c0462c1..00000000 --- a/cheri/sail_latex/saileqint.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_int = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : (int, int) -> bool diff --git a/cheri/sail_latex/saileqrange.tex b/cheri/sail_latex/saileqrange.tex deleted file mode 100644 index 7f1cd5f2..00000000 --- a/cheri/sail_latex/saileqrange.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_range = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "eq_range"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool diff --git a/cheri/sail_latex/sailexecute.tex b/cheri/sail_latex/sailexecute.tex deleted file mode 100644 index 69282932..00000000 --- a/cheri/sail_latex/sailexecute.tex +++ /dev/null @@ -1 +0,0 @@ -val execute : ast -> unit effect {barr, eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} diff --git a/cheri/sail_latex/sailexecutebranch.tex b/cheri/sail_latex/sailexecutebranch.tex deleted file mode 100644 index a4582e82..00000000 --- a/cheri/sail_latex/sailexecutebranch.tex +++ /dev/null @@ -1 +0,0 @@ -val execute_branch : #\hyperref[zbits]{bits}#(64) -> unit effect {wreg} diff --git a/cheri/sail_latex/sailexecutebranchpcc.tex b/cheri/sail_latex/sailexecutebranchpcc.tex deleted file mode 100644 index f94d4e7d..00000000 --- a/cheri/sail_latex/sailexecutebranchpcc.tex +++ /dev/null @@ -1 +0,0 @@ -val execute_branch_pcc : CapStruct -> unit effect {wreg} diff --git a/cheri/sail_latex/sailextendLoad.tex b/cheri/sail_latex/sailextendLoad.tex deleted file mode 100644 index d403c83c..00000000 --- a/cheri/sail_latex/sailextendLoad.tex +++ /dev/null @@ -1 +0,0 @@ -val extendLoad : forall 'sz, 'sz <= 64 . (#\hyperref[zbits]{bits}#('sz), bool) -> #\hyperref[zbits]{bits}#(64) effect pure diff --git a/cheri/sail_latex/sailfnAccessLevelofnum.tex b/cheri/sail_latex/sailfnAccessLevelofnum.tex deleted file mode 100644 index a8446000..00000000 --- a/cheri/sail_latex/sailfnAccessLevelofnum.tex +++ /dev/null @@ -1,5 +0,0 @@ -function AccessLevel_of_num arg# = match arg# { - 0 => User, - 1 => Supervisor, - _ => Kernel -} diff --git a/cheri/sail_latex/sailfnCPtrCmpOpofnum.tex b/cheri/sail_latex/sailfnCPtrCmpOpofnum.tex deleted file mode 100644 index 6ab563f3..00000000 --- a/cheri/sail_latex/sailfnCPtrCmpOpofnum.tex +++ /dev/null @@ -1,10 +0,0 @@ -function CPtrCmpOp_of_num arg# = match arg# { - 0 => CEQ, - 1 => CNE, - 2 => CLT, - 3 => CLE, - 4 => CLTU, - 5 => CLEU, - 6 => CEXEQ, - _ => CNEXEQ -} diff --git a/cheri/sail_latex/sailfnCapExCode.tex b/cheri/sail_latex/sailfnCapExCode.tex deleted file mode 100644 index 324612a0..00000000 --- a/cheri/sail_latex/sailfnCapExCode.tex +++ /dev/null @@ -1,26 +0,0 @@ -function #\hyperref[zCapExCode]{CapExCode}#(ex) : CapEx -> #\hyperref[zbits]{bits}#(8)= - match ex { - CapEx_None => 0x00, - CapEx_LengthViolation => 0x01, - CapEx_TagViolation => 0x02, - CapEx_SealViolation => 0x03, - CapEx_TypeViolation => 0x04, - CapEx_CallTrap => 0x05, - CapEx_ReturnTrap => 0x06, - CapEx_TSSUnderFlow => 0x07, - CapEx_UserDefViolation => 0x08, - CapEx_TLBNoStoreCap => 0x09, - CapEx_InexactBounds => 0x0a, - CapEx_GlobalViolation => 0x10, - CapEx_PermitExecuteViolation => 0x11, - CapEx_PermitLoadViolation => 0x12, - CapEx_PermitStoreViolation => 0x13, - CapEx_PermitLoadCapViolation => 0x14, - CapEx_PermitStoreCapViolation => 0x15, - CapEx_PermitStoreLocalCapViolation => 0x16, - CapEx_PermitSealViolation => 0x17, - CapEx_AccessSystemRegsViolation => 0x18, - CapEx_PermitCCallViolation => 0x19, - CapEx_AccessCCallIDCViolation => 0x1a, - CapEx_PermitUnsealViolation => 0x1b - } diff --git a/cheri/sail_latex/sailfnCapExofnum.tex b/cheri/sail_latex/sailfnCapExofnum.tex deleted file mode 100644 index 1bb6f2d1..00000000 --- a/cheri/sail_latex/sailfnCapExofnum.tex +++ /dev/null @@ -1,25 +0,0 @@ -function CapEx_of_num arg# = match arg# { - 0 => CapEx_None, - 1 => CapEx_LengthViolation, - 2 => CapEx_TagViolation, - 3 => CapEx_SealViolation, - 4 => CapEx_TypeViolation, - 5 => CapEx_CallTrap, - 6 => CapEx_ReturnTrap, - 7 => CapEx_TSSUnderFlow, - 8 => CapEx_UserDefViolation, - 9 => CapEx_TLBNoStoreCap, - 10 => CapEx_InexactBounds, - 11 => CapEx_GlobalViolation, - 12 => CapEx_PermitExecuteViolation, - 13 => CapEx_PermitLoadViolation, - 14 => CapEx_PermitStoreViolation, - 15 => CapEx_PermitLoadCapViolation, - 16 => CapEx_PermitStoreCapViolation, - 17 => CapEx_PermitStoreLocalCapViolation, - 18 => CapEx_PermitSealViolation, - 19 => CapEx_AccessSystemRegsViolation, - 20 => CapEx_PermitCCallViolation, - 21 => CapEx_AccessCCallIDCViolation, - _ => CapEx_PermitUnsealViolation -} diff --git a/cheri/sail_latex/sailfnClearRegSetofnum.tex b/cheri/sail_latex/sailfnClearRegSetofnum.tex deleted file mode 100644 index edfe64e3..00000000 --- a/cheri/sail_latex/sailfnClearRegSetofnum.tex +++ /dev/null @@ -1,6 +0,0 @@ -function ClearRegSet_of_num arg# = match arg# { - 0 => GPLo, - 1 => GPHi, - 2 => CLo, - _ => CHi -} diff --git a/cheri/sail_latex/sailfnComparisonofnum.tex b/cheri/sail_latex/sailfnComparisonofnum.tex deleted file mode 100644 index 8ff4bfc1..00000000 --- a/cheri/sail_latex/sailfnComparisonofnum.tex +++ /dev/null @@ -1,10 +0,0 @@ -function Comparison_of_num arg# = match arg# { - 0 => EQ, - 1 => NE, - 2 => GE, - 3 => GEU, - 4 => GT, - 5 => LE, - 6 => LT, - _ => LTU -} diff --git a/cheri/sail_latex/sailfnERETHook.tex b/cheri/sail_latex/sailfnERETHook.tex deleted file mode 100644 index bac1f738..00000000 --- a/cheri/sail_latex/sailfnERETHook.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zERETHook]{ERETHook}#() : unit -> unit = - { - nextPCC = EPCC; - delayedPCC = EPCC; /* always write delayedPCC together with nextPCC so - that non-capability branches don't override PCC */ - } diff --git a/cheri/sail_latex/sailfnExceptionCode.tex b/cheri/sail_latex/sailfnExceptionCode.tex deleted file mode 100644 index b34ab2ab..00000000 --- a/cheri/sail_latex/sailfnExceptionCode.tex +++ /dev/null @@ -1,23 +0,0 @@ -function #\hyperref[zExceptionCode]{ExceptionCode}# (ex) : Exception -> #\hyperref[zbits]{bits}#(5)= - let x : #\hyperref[zbits]{bits}#(8) = match ex - { - Interrupt => 0x00, /* Interrupt */ - TLBMod => 0x01, /* TLB modification exception */ - TLBL => 0x02, /* TLB #\hyperref[zexception]{exception}# (load or fetch) */ - TLBS => 0x03, /* TLB #\hyperref[zexception]{exception}# (store) */ - AdEL => 0x04, /* Address #\hyperref[zerror]{error}# (load or fetch) */ - AdES => 0x05, /* Address #\hyperref[zerror]{error}# (store) */ - Sys => 0x08, /* Syscall */ - Bp => 0x09, /* Breakpoint */ - ResI => 0x0a, /* Reserved instruction */ - CpU => 0x0b, /* Coprocessor Unusable */ - Ov => 0x0c, /* Arithmetic overflow */ - Tr => 0x0d, /* Trap */ - C2E => 0x12, /* C2E coprocessor 2 exception */ - C2Trap => 0x12, /* C2Trap maps to same exception code, different vector */ - XTLBRefillL => 0x02, - XTLBRefillS => 0x03, - XTLBInvL => 0x02, - XTLBInvS => 0x03, - MCheck => 0x18 - } in x[4..0] diff --git a/cheri/sail_latex/sailfnExceptionofnum.tex b/cheri/sail_latex/sailfnExceptionofnum.tex deleted file mode 100644 index 0ffd2ef1..00000000 --- a/cheri/sail_latex/sailfnExceptionofnum.tex +++ /dev/null @@ -1,21 +0,0 @@ -function Exception_of_num arg# = match arg# { - 0 => Interrupt, - 1 => TLBMod, - 2 => TLBL, - 3 => TLBS, - 4 => AdEL, - 5 => AdES, - 6 => Sys, - 7 => Bp, - 8 => ResI, - 9 => CpU, - 10 => Ov, - 11 => Tr, - 12 => C2E, - 13 => C2Trap, - 14 => XTLBRefillL, - 15 => XTLBRefillS, - 16 => XTLBInvL, - 17 => XTLBInvS, - _ => MCheck -} diff --git a/cheri/sail_latex/sailfnMAX.tex b/cheri/sail_latex/sailfnMAX.tex deleted file mode 100644 index e9a6a650..00000000 --- a/cheri/sail_latex/sailfnMAX.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMAX]{MAX}#(n) = #\hyperref[zpowtwo]{pow2}#(n) - 1 diff --git a/cheri/sail_latex/sailfnMEMea.tex b/cheri/sail_latex/sailfnMEMea.tex deleted file mode 100644 index 1bd08739..00000000 --- a/cheri/sail_latex/sailfnMEMea.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMea]{MEMea}# (addr, size) = #\hyperref[zskipzyeamem]{skip\_eamem}#() diff --git a/cheri/sail_latex/sailfnMEMeaconditional.tex b/cheri/sail_latex/sailfnMEMeaconditional.tex deleted file mode 100644 index 65930634..00000000 --- a/cheri/sail_latex/sailfnMEMeaconditional.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMeazyconditional]{MEMea\_conditional}# (addr, size) = #\hyperref[zskipzyeamem]{skip\_eamem}#() diff --git a/cheri/sail_latex/sailfnMEMr.tex b/cheri/sail_latex/sailfnMEMr.tex deleted file mode 100644 index bae85b70..00000000 --- a/cheri/sail_latex/sailfnMEMr.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMr]{MEMr}# (addr, size) = #\hyperref[zzyzyMIPSzyread]{\_\_MIPS\_read}#(addr, size) diff --git a/cheri/sail_latex/sailfnMEMrreserve.tex b/cheri/sail_latex/sailfnMEMrreserve.tex deleted file mode 100644 index 9339f02b..00000000 --- a/cheri/sail_latex/sailfnMEMrreserve.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMrzyreserve]{MEMr\_reserve}# (addr, size) = #\hyperref[zzyzyMIPSzyread]{\_\_MIPS\_read}#(addr, size) diff --git a/cheri/sail_latex/sailfnMEMrreservewrapper.tex b/cheri/sail_latex/sailfnMEMrreservewrapper.tex deleted file mode 100644 index fc8ea6c7..00000000 --- a/cheri/sail_latex/sailfnMEMrreservewrapper.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zMEMrzyreservezywrapper]{MEMr\_reserve\_wrapper}# (addr , size) = - #\hyperref[zreversezyendianness]{reverse\_endianness}#(#\hyperref[zMEMrzyreserve]{MEMr\_reserve}#(addr, size)) diff --git a/cheri/sail_latex/sailfnMEMrtagged.tex b/cheri/sail_latex/sailfnMEMrtagged.tex deleted file mode 100644 index 8c338860..00000000 --- a/cheri/sail_latex/sailfnMEMrtagged.tex +++ /dev/null @@ -1,8 +0,0 @@ -function #\hyperref[zMEMrzytagged]{MEMr\_tagged}# (addr) = -{ - /* assumes addr is cap. aligned */ - assert(#\hyperref[zunsigned]{unsigned}#(addr) % cap_size == 0); - let tag = #\hyperref[zMEMrzytag]{MEMr\_tag}#(addr) in - let data = #\hyperref[zMEMr]{MEMr}#(addr, cap_size) in - (tag, #\hyperref[zreversezyendianness]{reverse\_endianness}#(data)) -} diff --git a/cheri/sail_latex/sailfnMEMrtaggedreserve.tex b/cheri/sail_latex/sailfnMEMrtaggedreserve.tex deleted file mode 100644 index 2605592a..00000000 --- a/cheri/sail_latex/sailfnMEMrtaggedreserve.tex +++ /dev/null @@ -1,8 +0,0 @@ -function #\hyperref[zMEMrzytaggedzyreserve]{MEMr\_tagged\_reserve}# (addr) = -{ - /* assumes addr is cap. aligned */ - assert(#\hyperref[zunsigned]{unsigned}#(addr) % cap_size == 0); - let tag = #\hyperref[zMEMrzytag]{MEMr\_tag}#(addr) in - let data = #\hyperref[zMEMrzyreserve]{MEMr\_reserve}#(addr, cap_size) in - (tag, #\hyperref[zreversezyendianness]{reverse\_endianness}#(data)) -} diff --git a/cheri/sail_latex/sailfnMEMrwrapper.tex b/cheri/sail_latex/sailfnMEMrwrapper.tex deleted file mode 100644 index 68576849..00000000 --- a/cheri/sail_latex/sailfnMEMrwrapper.tex +++ /dev/null @@ -1,13 +0,0 @@ -function #\hyperref[zMEMrzywrapper]{MEMr\_wrapper}# (addr, size) = - if (addr == 0x000000007f000000) then - { - let rvalid = UART_RVALID in - { - UART_RVALID = [bitzero]; - #\hyperref[zmask]{mask}#(0x00000000 @ UART_RDATA @ rvalid @ 0b0000000 @ 0x0000) - } - } - else if (addr == 0x000000007f000004) then - #\hyperref[zmask]{mask}#(0x000000000004ffff) /* Always plenty of write space available and jtag activity */ - else - #\hyperref[zreversezyendianness]{reverse\_endianness}#(#\hyperref[zMEMr]{MEMr}#(addr, size)) /* MEMr assumes little endian */ diff --git a/cheri/sail_latex/sailfnMEMsync.tex b/cheri/sail_latex/sailfnMEMsync.tex deleted file mode 100644 index 5a0bc91c..00000000 --- a/cheri/sail_latex/sailfnMEMsync.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMzysync]{MEM\_sync}# () = #\hyperref[zskipzybarr]{skip\_barr}#() diff --git a/cheri/sail_latex/sailfnMEMval.tex b/cheri/sail_latex/sailfnMEMval.tex deleted file mode 100644 index 73795344..00000000 --- a/cheri/sail_latex/sailfnMEMval.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMval]{MEMval}# (addr, size, data) = #\hyperref[zzyzyMIPSzywrite]{\_\_MIPS\_write}#(addr, size, data) diff --git a/cheri/sail_latex/sailfnMEMvalconditional.tex b/cheri/sail_latex/sailfnMEMvalconditional.tex deleted file mode 100644 index 906bbd68..00000000 --- a/cheri/sail_latex/sailfnMEMvalconditional.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zMEMvalzyconditional]{MEMval\_conditional}# (addr, size, data) = { #\hyperref[zzyzyMIPSzywrite]{\_\_MIPS\_write}#(addr, size, data); true } diff --git a/cheri/sail_latex/sailfnMEMwconditionalwrapper.tex b/cheri/sail_latex/sailfnMEMwconditionalwrapper.tex deleted file mode 100644 index 04ce8389..00000000 --- a/cheri/sail_latex/sailfnMEMwconditionalwrapper.tex +++ /dev/null @@ -1,11 +0,0 @@ -function #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(addr, size, data) = - { - /* require that writes don't cross capability #\hyperref[zboundaries]{boundaries}# (should be true due to mips alignment requirements) */ - assert((addr & cap_addr_mask) == ((addr + #\hyperref[ztozybits]{to\_bits}#(64, size - 1)) & cap_addr_mask)); - #\hyperref[zMEMeazyconditional]{MEMea\_conditional}#(addr, size); - success = #\hyperref[zMEMvalzyconditional]{MEMval\_conditional}#(addr,size,#\hyperref[zreversezyendianness]{reverse\_endianness}#(data)); - if success then - /* On cheri non-capability writes must clear the corresponding tag */ - #\hyperref[zMEMwzytag]{MEMw\_tag}#(addr & cap_addr_mask, false); - success; - } diff --git a/cheri/sail_latex/sailfnMEMwtagged.tex b/cheri/sail_latex/sailfnMEMwtagged.tex deleted file mode 100644 index 3b7aab53..00000000 --- a/cheri/sail_latex/sailfnMEMwtagged.tex +++ /dev/null @@ -1,8 +0,0 @@ -function #\hyperref[zMEMwzytagged]{MEMw\_tagged}#(addr, tag, data) = -{ - /* assumes addr is cap. aligned */ - assert(#\hyperref[zunsigned]{unsigned}#(addr) % cap_size == 0); - #\hyperref[zMEMea]{MEMea}#(addr, cap_size); - #\hyperref[zMEMval]{MEMval}#(addr, cap_size, #\hyperref[zreversezyendianness]{reverse\_endianness}#(data)); - #\hyperref[zMEMwzytag]{MEMw\_tag}#(addr, tag); -} diff --git a/cheri/sail_latex/sailfnMEMwtaggedconditional.tex b/cheri/sail_latex/sailfnMEMwtaggedconditional.tex deleted file mode 100644 index 75d9efb3..00000000 --- a/cheri/sail_latex/sailfnMEMwtaggedconditional.tex +++ /dev/null @@ -1,10 +0,0 @@ -function #\hyperref[zMEMwzytaggedzyconditional]{MEMw\_tagged\_conditional}#(addr, tag, data) = -{ - /* assumes addr is cap. aligned */ - assert(#\hyperref[zunsigned]{unsigned}#(addr) % cap_size == 0); - #\hyperref[zMEMeazyconditional]{MEMea\_conditional}#(addr, cap_size); - success = #\hyperref[zMEMvalzyconditional]{MEMval\_conditional}#(addr, cap_size, #\hyperref[zreversezyendianness]{reverse\_endianness}#(data)); - if success then - #\hyperref[zMEMwzytag]{MEMw\_tag}#(addr, tag); - success; -} diff --git a/cheri/sail_latex/sailfnMEMwwrapper.tex b/cheri/sail_latex/sailfnMEMwwrapper.tex deleted file mode 100644 index 6f83825c..00000000 --- a/cheri/sail_latex/sailfnMEMwwrapper.tex +++ /dev/null @@ -1,16 +0,0 @@ -function #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(addr, size, data) = - let ledata = #\hyperref[zreversezyendianness]{reverse\_endianness}#(data) in - if (addr == 0x000000007f000000) then - { - UART_WDATA = ledata[7..0]; - UART_WRITTEN = 0b1; - } - else - { - /* require that writes don't cross capability #\hyperref[zboundaries]{boundaries}# (should be true due to mips alignment requirements) */ - assert((addr & cap_addr_mask) == ((addr + #\hyperref[ztozybits]{to\_bits}#(64, size - 1)) & cap_addr_mask)); - #\hyperref[zMEMea]{MEMea}#(addr, size); - #\hyperref[zMEMval]{MEMval}#(addr, size, ledata); - /* On cheri non-capability writes must clear the corresponding tag*/ - #\hyperref[zMEMwzytag]{MEMw\_tag}#(addr & cap_addr_mask, false); - } diff --git a/cheri/sail_latex/sailfnMIPSread.tex b/cheri/sail_latex/sailfnMIPSread.tex deleted file mode 100644 index ee937856..00000000 --- a/cheri/sail_latex/sailfnMIPSread.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zzyzyMIPSzyread]{\_\_MIPS\_read}# (addr, width) = #\hyperref[zzyzyReadRAM]{\_\_ReadRAM}#(64, width, 0x0000_0000_0000_0000, addr) diff --git a/cheri/sail_latex/sailfnMIPSwrite.tex b/cheri/sail_latex/sailfnMIPSwrite.tex deleted file mode 100644 index 5e81f335..00000000 --- a/cheri/sail_latex/sailfnMIPSwrite.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zzyzyMIPSzywrite]{\_\_MIPS\_write}# (addr, width, data) = let _ = #\hyperref[zzyzyWriteRAM]{\_\_WriteRAM}#(64, width, 0x0000_0000_0000_0000, addr, data) in () diff --git a/cheri/sail_latex/sailfnMemAccessTypeofnum.tex b/cheri/sail_latex/sailfnMemAccessTypeofnum.tex deleted file mode 100644 index a16af4e9..00000000 --- a/cheri/sail_latex/sailfnMemAccessTypeofnum.tex +++ /dev/null @@ -1,5 +0,0 @@ -function MemAccessType_of_num arg# = match arg# { - 0 => Instruction, - 1 => LoadData, - _ => StoreData -} diff --git a/cheri/sail_latex/sailfnMkCapCauseReg.tex b/cheri/sail_latex/sailfnMkCapCauseReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkCapCauseReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkCauseReg.tex b/cheri/sail_latex/sailfnMkCauseReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkCauseReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkContextReg.tex b/cheri/sail_latex/sailfnMkContextReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkContextReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkStatusReg.tex b/cheri/sail_latex/sailfnMkStatusReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkStatusReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkTLBEntry.tex b/cheri/sail_latex/sailfnMkTLBEntry.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkTLBEntry.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkTLBEntryHiReg.tex b/cheri/sail_latex/sailfnMkTLBEntryHiReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkTLBEntryHiReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkTLBEntryLoReg.tex b/cheri/sail_latex/sailfnMkTLBEntryLoReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkTLBEntryLoReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnMkXContextReg.tex b/cheri/sail_latex/sailfnMkXContextReg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnMkXContextReg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnNotWordVal.tex b/cheri/sail_latex/sailfnNotWordVal.tex deleted file mode 100644 index b6222084..00000000 --- a/cheri/sail_latex/sailfnNotWordVal.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zNotWordVal]{NotWordVal}# (word) = - (word[31] ^^ 32) != word[63..32] diff --git a/cheri/sail_latex/sailfnSignalException.tex b/cheri/sail_latex/sailfnSignalException.tex deleted file mode 100644 index a91f582e..00000000 --- a/cheri/sail_latex/sailfnSignalException.tex +++ /dev/null @@ -1,18 +0,0 @@ -function #\hyperref[zSignalException]{SignalException}# (ex) = - { - if (#\hyperref[znot]{not}# (CP0Status.#\hyperref[zEXL]{EXL}#())) then { - let pc = PC in - let pcc = #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC) in - let (success, epcc) = #\hyperref[zsetCapOffset]{setCapOffset}#(pcc, pc) in - if (success) then - EPCC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(epcc) - else - EPCC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(#\hyperref[zintzytozycap]{int\_to\_cap}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(pcc)) + #\hyperref[zunsigned]{unsigned}#(pc))); - }; - - nextPCC = KCC; - delayedPCC = KCC; /* always write delayedPCC together with nextPCC so - that non-capability branches don't override PCC */ - let base = #\hyperref[zgetCapBase]{getCapBase}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KCC)) in - #\hyperref[zSignalExceptionMIPS]{SignalExceptionMIPS}#(ex, #\hyperref[ztozybits]{to\_bits}#(64, base)); - } diff --git a/cheri/sail_latex/sailfnSignalExceptionBadAddr.tex b/cheri/sail_latex/sailfnSignalExceptionBadAddr.tex deleted file mode 100644 index d35ed9e8..00000000 --- a/cheri/sail_latex/sailfnSignalExceptionBadAddr.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(ex, badAddr) = - { - CP0BadVAddr = badAddr; - #\hyperref[zSignalException]{SignalException}#(ex); - } diff --git a/cheri/sail_latex/sailfnSignalExceptionMIPS.tex b/cheri/sail_latex/sailfnSignalExceptionMIPS.tex deleted file mode 100644 index 8d3f762a..00000000 --- a/cheri/sail_latex/sailfnSignalExceptionMIPS.tex +++ /dev/null @@ -1,39 +0,0 @@ -function #\hyperref[zSignalExceptionMIPS]{SignalExceptionMIPS}# (ex, kccBase) = - { - /* Only update EPC and BD if not already in EXL mode */ - if (~ (CP0Status.#\hyperref[zEXL]{EXL}#())) then - { - if (inBranchDelay[0]) then - { - CP0EPC = PC - 4; - CP0Cause->#\hyperref[zBD]{BD}#() = 0b1; - } - else - { - CP0EPC = PC; - CP0Cause->#\hyperref[zBD]{BD}#() = 0b0; - } - }; - - /* choose an exception vector to branch to. Some are not supported - e.g. Reset */ - vectorOffset = - if (CP0Status.#\hyperref[zEXL]{EXL}#()) then - 0x180 /* Always use common vector if in exception mode already */ - else if ((ex == XTLBRefillL) | (ex == XTLBRefillS)) then - 0x080 - else if (ex == C2Trap) then - 0x280 /* Special vector for CHERI traps */ - else - 0x180; /* Common vector */ - vectorBase : #\hyperref[zbits]{bits}#(64) = if CP0Status.#\hyperref[zBEV]{BEV}#() then - 0xFFFFFFFFBFC00200 - else - 0xFFFFFFFF80000000; - /* On CHERI we have to subtract KCC.base so that we end up at the - right absolute vector address after indirecting via new PCC */ - nextPC = vectorBase + #\hyperref[zsignzyextend]{sign\_extend}#(vectorOffset) - kccBase; - CP0Cause->#\hyperref[zExcCode]{ExcCode}#() = #\hyperref[zExceptionCode]{ExceptionCode}#(ex); - CP0Status->#\hyperref[zEXL]{EXL}#() = 0b1; - throw (#\hyperref[zISAException]{ISAException}#()); - } diff --git a/cheri/sail_latex/sailfnSignalExceptionTLB.tex b/cheri/sail_latex/sailfnSignalExceptionTLB.tex deleted file mode 100644 index a523d7b6..00000000 --- a/cheri/sail_latex/sailfnSignalExceptionTLB.tex +++ /dev/null @@ -1,9 +0,0 @@ -function #\hyperref[zSignalExceptionTLB]{SignalExceptionTLB}#(ex, badAddr) = { - CP0BadVAddr = badAddr; - TLBContext->#\hyperref[zBadVPNtwo]{BadVPN2}#() = (badAddr[31..13]); - TLBXContext->#\hyperref[zXBadVPNtwo]{XBadVPN2}#()= (badAddr[39..13]); - TLBXContext->#\hyperref[zXR]{XR}#() = (badAddr[63..62]); - TLBEntryHi->#\hyperref[zR]{R}#() = (badAddr[63..62]); - TLBEntryHi->#\hyperref[zVPNtwo]{VPN2}#() = (badAddr[39..13]); - #\hyperref[zSignalException]{SignalException}#(ex); -} diff --git a/cheri/sail_latex/sailfnTLBTranslate.tex b/cheri/sail_latex/sailfnTLBTranslate.tex deleted file mode 100644 index e40518c3..00000000 --- a/cheri/sail_latex/sailfnTLBTranslate.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zTLBTranslate]{TLBTranslate}# (vAddr, accessType) = - let (addr, c) = #\hyperref[zTLBTranslateC]{TLBTranslateC}#(vAddr, accessType) in addr diff --git a/cheri/sail_latex/sailfnTLBTranslateC.tex b/cheri/sail_latex/sailfnTLBTranslateC.tex deleted file mode 100644 index d71c0841..00000000 --- a/cheri/sail_latex/sailfnTLBTranslateC.tex +++ /dev/null @@ -1,31 +0,0 @@ -function #\hyperref[zTLBTranslateC]{TLBTranslateC}# (vAddr, accessType) = - { - let currentAccessLevel = #\hyperref[zgetAccessLevel]{getAccessLevel}#() in - let compat32 = (vAddr[61..31] == 0b1111111111111111111111111111111) in - let (requiredLevel, addr) : (AccessLevel, #\hyperref[zoption]{option}#(#\hyperref[zbits]{bits}#(64))) = match (vAddr[63..62]) { - 0b11 => match (compat32, vAddr[30..29]) { /* xkseg */ - (true, 0b11) => (Kernel, #\hyperref[zNone]{None}#() : #\hyperref[zoption]{option}#(#\hyperref[zbits]{bits}#(64))), /* kseg3 mapped 32-bit compat */ - (true, 0b10) => (Supervisor, #\hyperref[zNone]{None}#() : #\hyperref[zoption]{option}#(#\hyperref[zbits]{bits}#(64))), /* sseg mapped 32-bit compat */ - (true, 0b01) => (Kernel, #\hyperref[zSome]{Some}#(0x00000000 @ 0b000 @ vAddr[28..0])), /* kseg1 unmapped uncached 32-bit compat */ - (true, 0b00) => (Kernel, #\hyperref[zSome]{Some}#(0x00000000 @ 0b000 @ vAddr[28..0])), /* kseg0 unmapped cached 32-bit compat */ - (_, _) => (Kernel, #\hyperref[zNone]{None}#() : #\hyperref[zoption]{option}#(#\hyperref[zbits]{bits}#(64))) /* xkseg mapped */ - }, - 0b10 => (Kernel, #\hyperref[zSome]{Some}#(0b00000 @ vAddr[58..0])), /* xkphys bits 61-59 are cache #\hyperref[zmode]{mode}# (ignored) */ - 0b01 => (Supervisor, #\hyperref[zNone]{None}#() : #\hyperref[zoption]{option}#(#\hyperref[zbits]{bits}#(64))), /* xsseg - supervisor mapped */ - 0b00 => (User, #\hyperref[zNone]{None}#() : #\hyperref[zoption]{option}#(#\hyperref[zbits]{bits}#(64))) /* xuseg - user mapped */ - } in - if #\hyperref[znot]{not}#(#\hyperref[zgrantsAccess]{grantsAccess}#(currentAccessLevel, requiredLevel)) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(if (accessType == StoreData) then AdES else AdEL, vAddr) - else - let (pa, c) : (#\hyperref[zbits]{bits}#(64), bool) = match addr { - #\hyperref[zSome]{Some}#(a) => (a, false), - #\hyperref[zNone]{None}#() => if ((~(compat32)) & (#\hyperref[zunsigned]{unsigned}#(vAddr[61..0]) > MAX_VA)) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(if (accessType == StoreData) then AdES else AdEL, vAddr) - else - #\hyperref[zTLBTranslatetwo]{TLBTranslate2}#(vAddr, accessType) - } - in if (#\hyperref[zunsigned]{unsigned}#(pa) > MAX_PA) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(if (accessType == StoreData) then AdES else AdEL, vAddr) - else - (pa, c) - } diff --git a/cheri/sail_latex/sailfnTLBTranslatetwo.tex b/cheri/sail_latex/sailfnTLBTranslatetwo.tex deleted file mode 100644 index 126159f7..00000000 --- a/cheri/sail_latex/sailfnTLBTranslatetwo.tex +++ /dev/null @@ -1,36 +0,0 @@ -function #\hyperref[zTLBTranslatetwo]{TLBTranslate2}# (vAddr, accessType) = { - let idx = #\hyperref[ztlbSearch]{tlbSearch}#(vAddr) in - match idx { - #\hyperref[zSome]{Some}#(idx) => - let i as atom(_) = #\hyperref[zunsigned]{unsigned}#(idx) in - let entry = #\hyperref[zregzyderef]{reg\_deref}#(TLBEntries[i]) in - let entryMask = entry.#\hyperref[zpagemask]{pagemask}#() in - let 'evenOddBit : range(12,28) = match (entryMask) { - 0x0000 => 12, - 0x0003 => 14, - 0x000f => 16, - 0x003f => 18, - 0x00ff => 20, - 0x03ff => 22, - 0x0fff => 24, - 0x3fff => 26, - 0xffff => 28, - _ => undefined - } in - let isOdd = (vAddr[evenOddBit]) in - let (caps : #\hyperref[zbits]{bits}#(1), capl : #\hyperref[zbits]{bits}#(1), pfn : #\hyperref[zbits]{bits}#(24), d : #\hyperref[zbits]{bits}#(1), v : #\hyperref[zbits]{bits}#(1)) = - if (isOdd) then - (entry.#\hyperref[zcapsone]{caps1}#(), entry.#\hyperref[zcaplone]{capl1}#(), entry.#\hyperref[zpfnone]{pfn1}#(), entry.#\hyperref[zdone]{d1}#(), entry.#\hyperref[zvone]{v1}#()) - else - (entry.#\hyperref[zcapszero]{caps0}#(), entry.#\hyperref[zcaplzero]{capl0}#(), entry.#\hyperref[zpfnzero]{pfn0}#(), entry.#\hyperref[zdzero]{d0}#(), entry.#\hyperref[zvzero]{v0}#()) in - if (~(v)) then - #\hyperref[zSignalExceptionTLB]{SignalExceptionTLB}#(if (accessType == StoreData) then XTLBInvS else XTLBInvL, vAddr) - else if ((accessType == StoreData) & ~(d)) then - #\hyperref[zSignalExceptionTLB]{SignalExceptionTLB}#(TLBMod, vAddr) - else - let res : #\hyperref[zbits]{bits}#(64) = #\hyperref[zzzerozyextend]{zero\_extend}#(pfn[23..(evenOddBit - 12)] @ vAddr[(evenOddBit - 1) .. 0]) in - (res, #\hyperref[zbitszytozybool]{bits\_to\_bool}#(if (accessType == StoreData) then caps else capl)), - #\hyperref[zNone]{None}#() => #\hyperref[zSignalExceptionTLB]{SignalExceptionTLB}#( - if (accessType == StoreData) then XTLBRefillS else XTLBRefillL, vAddr) - } -} diff --git a/cheri/sail_latex/sailfnTLBWriteEntry.tex b/cheri/sail_latex/sailfnTLBWriteEntry.tex deleted file mode 100644 index ba2762ea..00000000 --- a/cheri/sail_latex/sailfnTLBWriteEntry.tex +++ /dev/null @@ -1,36 +0,0 @@ -function #\hyperref[zTLBWriteEntry]{TLBWriteEntry}#(idx) = { - pagemask = TLBPageMask; - match pagemask { - 0x0000 => (), - 0x0003 => (), - 0x000f => (), - 0x003f => (), - 0x00ff => (), - 0x03ff => (), - 0x0fff => (), - 0x3fff => (), - 0xffff => (), - _ => (#\hyperref[zSignalException]{SignalException}#(MCheck)) - }; - let i as atom(_) = #\hyperref[zunsigned]{unsigned}#(idx) in - let entry = TLBEntries[i] in { - entry.#\hyperref[zpagemask]{pagemask}#() = pagemask; - entry.#\hyperref[zr]{r}#() = TLBEntryHi.#\hyperref[zR]{R}#(); - entry.#\hyperref[zvpntwo]{vpn2}#() = TLBEntryHi.#\hyperref[zVPNtwo]{VPN2}#(); - entry.#\hyperref[zasid]{asid}#() = TLBEntryHi.#\hyperref[zASID]{ASID}#(); - entry.#\hyperref[zg]{g}#() = ((TLBEntryLo0.#\hyperref[zG]{G}#()) & (TLBEntryLo1.#\hyperref[zG]{G}#())); - entry.#\hyperref[zvalid]{valid}#() = bitone; - entry.#\hyperref[zcapszero]{caps0}#() = TLBEntryLo0.#\hyperref[zCapS]{CapS}#(); - entry.#\hyperref[zcaplzero]{capl0}#() = TLBEntryLo0.#\hyperref[zCapL]{CapL}#(); - entry.#\hyperref[zpfnzero]{pfn0}#() = TLBEntryLo0.#\hyperref[zPFN]{PFN}#(); - entry.#\hyperref[zczero]{c0}#() = TLBEntryLo0.#\hyperref[zC]{C}#(); - entry.#\hyperref[zdzero]{d0}#() = TLBEntryLo0.#\hyperref[zD]{D}#(); - entry.#\hyperref[zvzero]{v0}#() = TLBEntryLo0.#\hyperref[zV]{V}#(); - entry.#\hyperref[zcapsone]{caps1}#() = TLBEntryLo1.#\hyperref[zCapS]{CapS}#(); - entry.#\hyperref[zcaplone]{capl1}#() = TLBEntryLo1.#\hyperref[zCapL]{CapL}#(); - entry.#\hyperref[zpfnone]{pfn1}#() = TLBEntryLo1.#\hyperref[zPFN]{PFN}#(); - entry.#\hyperref[zcone]{c1}#() = TLBEntryLo1.#\hyperref[zC]{C}#(); - entry.#\hyperref[zdone]{d1}#() = TLBEntryLo1.#\hyperref[zD]{D}#(); - entry.#\hyperref[zvone]{v1}#() = TLBEntryLo1.#\hyperref[zV]{V}#(); - } -} diff --git a/cheri/sail_latex/sailfnTranslatePC.tex b/cheri/sail_latex/sailfnTranslatePC.tex deleted file mode 100644 index 5e43ffb4..00000000 --- a/cheri/sail_latex/sailfnTranslatePC.tex +++ /dev/null @@ -1,15 +0,0 @@ -function #\hyperref[zTranslatePC]{TranslatePC}# (vAddr) = { - #\hyperref[zincrementCPzeroCount]{incrementCP0Count}#(); - let pcc = #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC); - let base = #\hyperref[zgetCapBase]{getCapBase}#(pcc); - let top = #\hyperref[zgetCapTop]{getCapTop}#(pcc); - let absPC = base + #\hyperref[zunsigned]{unsigned}#(vAddr); - if ((absPC % 4) != 0) then /* bad PC alignment */ - (#\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, #\hyperref[ztozybits]{to\_bits}#(64, absPC))) /* XXX absPC may be truncated */ - else if #\hyperref[znot]{not}# (pcc.tag) then - (#\hyperref[zraisezyctwozyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_TagViolation)) - else if ((absPC + 4) > top) then - (#\hyperref[zraisezyctwozyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_LengthViolation)) - else - #\hyperref[zTLBTranslate]{TLBTranslate}#(#\hyperref[ztozybits]{to\_bits}#(64, absPC), Instruction) /* XXX assert absPC never gets truncated due to above check and top <= 2^64 for valid caps */ -} diff --git a/cheri/sail_latex/sailfnWordTypeUnalignedofnum.tex b/cheri/sail_latex/sailfnWordTypeUnalignedofnum.tex deleted file mode 100644 index 7b690587..00000000 --- a/cheri/sail_latex/sailfnWordTypeUnalignedofnum.tex +++ /dev/null @@ -1,6 +0,0 @@ -function WordTypeUnaligned_of_num arg# = match arg# { - 0 => WL, - 1 => WR, - 2 => DL, - _ => DR -} diff --git a/cheri/sail_latex/sailfnWordTypeofnum.tex b/cheri/sail_latex/sailfnWordTypeofnum.tex deleted file mode 100644 index f431606a..00000000 --- a/cheri/sail_latex/sailfnWordTypeofnum.tex +++ /dev/null @@ -1,6 +0,0 @@ -function WordType_of_num arg# = match arg# { - 0 => B, - 1 => H, - 2 => W, - _ => D -} diff --git a/cheri/sail_latex/sailfnaddrWrapper.tex b/cheri/sail_latex/sailfnaddrWrapper.tex deleted file mode 100644 index 6f1dd662..00000000 --- a/cheri/sail_latex/sailfnaddrWrapper.tex +++ /dev/null @@ -1,16 +0,0 @@ -function #\hyperref[zaddrWrapper]{addrWrapper}#(addr, accessType, width) = - { - ddc = #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(DDC); - #\hyperref[zcheckDDCPerms]{checkDDCPerms}#(ddc, accessType); - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(ddc); - vAddr = (cursor + #\hyperref[zunsigned]{unsigned}#(addr)) % #\hyperref[zpowtwo]{pow2}#(64); - size = #\hyperref[zwordWidthBytes]{wordWidthBytes}#(width); - base = #\hyperref[zgetCapBase]{getCapBase}#(ddc); - top = #\hyperref[zgetCapTop]{getCapTop}#(ddc); - if ((vAddr + size) > top) then - (#\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) - else if (vAddr < base) then - (#\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) - else - #\hyperref[ztozybits]{to\_bits}#(64, vAddr); - } diff --git a/cheri/sail_latex/sailfnaddrWrapperUnaligned.tex b/cheri/sail_latex/sailfnaddrWrapperUnaligned.tex deleted file mode 100644 index 47567f7e..00000000 --- a/cheri/sail_latex/sailfnaddrWrapperUnaligned.tex +++ /dev/null @@ -1,24 +0,0 @@ -function #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(addr, accessType, width) = - { - ddc = #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(DDC); - #\hyperref[zcheckDDCPerms]{checkDDCPerms}#(ddc, accessType); - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(ddc); - vAddr = (cursor + #\hyperref[zunsigned]{unsigned}#(addr)) % #\hyperref[zpowtwo]{pow2}#(64); - woffset = vAddr % 4; - doffset = vAddr % 8; - /* Compute the address and size of the bytes touched -- this depends on alignment. */ - let (waddr, size) : (int, int) = match width { - WL => (vAddr, 4 - woffset), - WR => (vAddr - woffset, woffset + 1), - DL => (vAddr, 8 - doffset), - DR => (vAddr - doffset, doffset + 1) - }; - base = #\hyperref[zgetCapBase]{getCapBase}#(ddc); - top = #\hyperref[zgetCapTop]{getCapTop}#(ddc); - if ((waddr + size) > top) then - (#\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) - else if (waddr < base) then - (#\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) - else - #\hyperref[ztozybits]{to\_bits}#(64, vAddr); - } diff --git a/cheri/sail_latex/sailfnbitstobool.tex b/cheri/sail_latex/sailfnbitstobool.tex deleted file mode 100644 index 1cb33076..00000000 --- a/cheri/sail_latex/sailfnbitstobool.tex +++ /dev/null @@ -1 +0,0 @@ -function bits_to_bool x = #\hyperref[zbitzytozybool]{bit\_to\_bool}#(x[0]) diff --git a/cheri/sail_latex/sailfnbittobool.tex b/cheri/sail_latex/sailfnbittobool.tex deleted file mode 100644 index a5eea578..00000000 --- a/cheri/sail_latex/sailfnbittobool.tex +++ /dev/null @@ -1,4 +0,0 @@ -function bit_to_bool b = match b { - bitone => true, - _ => false -} diff --git a/cheri/sail_latex/sailfnbooltobits.tex b/cheri/sail_latex/sailfnbooltobits.tex deleted file mode 100644 index 99075369..00000000 --- a/cheri/sail_latex/sailfnbooltobits.tex +++ /dev/null @@ -1 +0,0 @@ -function bool_to_bits x = if x then 0b1 else 0b0 diff --git a/cheri/sail_latex/sailfncapRegToCapStruct.tex b/cheri/sail_latex/sailfncapRegToCapStruct.tex deleted file mode 100644 index 5209e9f9..00000000 --- a/cheri/sail_latex/sailfncapRegToCapStruct.tex +++ /dev/null @@ -1,23 +0,0 @@ -function #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(capReg) : CapReg -> CapStruct = - struct { - tag = capReg[256], - padding = capReg[255..248], - otype = capReg[247..224], - uperms = capReg[223..208], - perm_reserved11_14 = capReg[207..204], - access_system_regs = capReg[203], - permit_unseal = capReg[202], - permit_ccall = capReg[201], - permit_seal = capReg[200], - permit_store_local_cap = capReg[199], - permit_store_cap = capReg[198], - permit_load_cap = capReg[197], - permit_store = capReg[196], - permit_load = capReg[195], - permit_execute = capReg[194], - global = capReg[193], - sealed = capReg[192], - address = capReg[191..128], - base = capReg[127..64], - length = capReg[63..0] - } diff --git a/cheri/sail_latex/sailfncapStructToCapReg.tex b/cheri/sail_latex/sailfncapStructToCapReg.tex deleted file mode 100644 index d0828429..00000000 --- a/cheri/sail_latex/sailfncapStructToCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(cap) : CapStruct -> CapReg = cap.tag @ #\hyperref[zcapStructToMemBitstwofivesix]{capStructToMemBits256}#(cap) diff --git a/cheri/sail_latex/sailfncapStructToMemBits.tex b/cheri/sail_latex/sailfncapStructToMemBits.tex deleted file mode 100644 index b85816b3..00000000 --- a/cheri/sail_latex/sailfncapStructToMemBits.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zcapStructToMemBits]{capStructToMemBits}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(256)= - #\hyperref[zcapStructToMemBitstwofivesix]{capStructToMemBits256}#(cap) ^ null_cap_bits diff --git a/cheri/sail_latex/sailfncapStructToMemBitstwofivesix.tex b/cheri/sail_latex/sailfncapStructToMemBitstwofivesix.tex deleted file mode 100644 index 0c775ae4..00000000 --- a/cheri/sail_latex/sailfncapStructToMemBitstwofivesix.tex +++ /dev/null @@ -1,10 +0,0 @@ -function #\hyperref[zcapStructToMemBitstwofivesix]{capStructToMemBits256}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(256) = - ( - cap.padding - @ cap.otype - @ #\hyperref[zgetCapPerms]{getCapPerms}#(cap) - @ cap.sealed - @ cap.address - @ cap.base - @ cap.length - ) diff --git a/cheri/sail_latex/sailfncapToString.tex b/cheri/sail_latex/sailfncapToString.tex deleted file mode 100644 index 2ad25883..00000000 --- a/cheri/sail_latex/sailfncapToString.tex +++ /dev/null @@ -1,16 +0,0 @@ -function capToString cap = { - #\hyperref[zskipzyescape]{skip\_escape}#(); /* because cheri128 getCapX functions contain asserts but cheri256 ones do not */ - #\hyperref[zconcatzystr]{concat\_str}#(" t:", - #\hyperref[zconcatzystr]{concat\_str}#(if cap.tag then "1" else "0", - #\hyperref[zconcatzystr]{concat\_str}#(" s:", - #\hyperref[zconcatzystr]{concat\_str}#(if cap.sealed then "1" else "0", - #\hyperref[zconcatzystr]{concat\_str}#(" perms:", - #\hyperref[zconcatzystr]{concat\_str}#(#\hyperref[zBitStr]{BitStr}#(0b0 @ #\hyperref[zgetCapPerms]{getCapPerms}#(cap)), - #\hyperref[zconcatzystr]{concat\_str}#(" type:", - #\hyperref[zconcatzystr]{concat\_str}#(#\hyperref[zBitStr]{BitStr}#(cap.otype), - #\hyperref[zconcatzystr]{concat\_str}#(" offset:", - #\hyperref[zconcatzystr]{concat\_str}#(#\hyperref[zBitStr]{BitStr}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapOffset]{getCapOffset}#(cap))), - #\hyperref[zconcatzystr]{concat\_str}#(" base:", - #\hyperref[zconcatzystr]{concat\_str}#(#\hyperref[zBitStr]{BitStr}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(cap))), - #\hyperref[zconcatzystr]{concat\_str}#(" length:", #\hyperref[zBitStr]{BitStr}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zmin]{min}#(#\hyperref[zgetCapLength]{getCapLength}#(cap), #\hyperref[zMAX]{MAX}#(64))))))))))))))))) - } diff --git a/cheri/sail_latex/sailfncastunitvec.tex b/cheri/sail_latex/sailfncastunitvec.tex deleted file mode 100644 index 1bb7a9e0..00000000 --- a/cheri/sail_latex/sailfncastunitvec.tex +++ /dev/null @@ -1,4 +0,0 @@ -function cast_unit_vec b = match b { - bitzero => 0b0, - _ => 0b1 -} diff --git a/cheri/sail_latex/sailfncheckCPtwousable.tex b/cheri/sail_latex/sailfncheckCPtwousable.tex deleted file mode 100644 index 8e7c29d7..00000000 --- a/cheri/sail_latex/sailfncheckCPtwousable.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zcheckCPtwousable]{checkCP2usable}# () = - if #\hyperref[znot]{not}# (CP0Status.#\hyperref[zCU]{CU}#()[2]) then { - CP0Cause->#\hyperref[zCE]{CE}#() = 0b10; - #\hyperref[zSignalException]{SignalException}#(CpU); - } diff --git a/cheri/sail_latex/sailfncheckCPzeroAccess.tex b/cheri/sail_latex/sailfncheckCPzeroAccess.tex deleted file mode 100644 index d63f00cf..00000000 --- a/cheri/sail_latex/sailfncheckCPzeroAccess.tex +++ /dev/null @@ -1,9 +0,0 @@ -function #\hyperref[zcheckCPzeroAccess]{checkCP0Access}# () = - { - let accessLevel = #\hyperref[zgetAccessLevel]{getAccessLevel}#() in - if ((accessLevel != Kernel) & (~(CP0Status.#\hyperref[zCU]{CU}#()[0]))) then - { - CP0Cause->#\hyperref[zCE]{CE}#() = 0b00; - #\hyperref[zSignalException]{SignalException}#(CpU); - } - } diff --git a/cheri/sail_latex/sailfncheckDDCPerms.tex b/cheri/sail_latex/sailfncheckDDCPerms.tex deleted file mode 100644 index 1675c666..00000000 --- a/cheri/sail_latex/sailfncheckDDCPerms.tex +++ /dev/null @@ -1,12 +0,0 @@ -function #\hyperref[zcheckDDCPerms]{checkDDCPerms}#(ddc : CapStruct, accessType: MemAccessType) = - { - if (#\hyperref[znot]{not}# (ddc.tag)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, 0b00000) - else if (ddc.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, 0b00000); - match accessType { - Instruction => assert(false), /* Only data accesses use DDC */ - LoadData => if (~(ddc.permit_load)) then (#\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, 0b00000)), - StoreData => if (~(ddc.permit_store)) then (#\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, 0b00000)) - }; - } diff --git a/cheri/sail_latex/sailfncompare.tex b/cheri/sail_latex/sailfncompare.tex deleted file mode 100644 index f4378ba7..00000000 --- a/cheri/sail_latex/sailfncompare.tex +++ /dev/null @@ -1,11 +0,0 @@ -function #\hyperref[zcompare]{compare}# (cmp, valA, valB) = - match cmp { - EQ => valA == valB, - NE => valA != valB, - GE => valA >=_s valB, - GEU => valA >=_u valB, - GT => valB <_s valA, - LE => valB >=_s valA, - LT => valA <_s valB, - LTU => valA <_u valB - } diff --git a/cheri/sail_latex/sailfncptwonextpc.tex b/cheri/sail_latex/sailfncptwonextpc.tex deleted file mode 100644 index c2a9c944..00000000 --- a/cheri/sail_latex/sailfncptwonextpc.tex +++ /dev/null @@ -1,8 +0,0 @@ -function #\hyperref[zcptwozynextzypc]{cp2\_next\_pc}# () = { - PCC = nextPCC; - if inBranchDelay then { - nextPCC = delayedPCC; - } else { - inCCallDelay = 0b0; - }; -} diff --git a/cheri/sail_latex/sailfndecodeSome.tex b/cheri/sail_latex/sailfndecodeSome.tex deleted file mode 100644 index 00a53489..00000000 --- a/cheri/sail_latex/sailfndecodeSome.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b10000000000000000000 @ 0b000010) = #\hyperref[zSome]{Some}#(#\hyperref[zTLBWI]{TLBWI}#() : ast) diff --git a/cheri/sail_latex/sailfndecodeSomeADD.tex b/cheri/sail_latex/sailfndecodeSomeADD.tex deleted file mode 100644 index 4b01b543..00000000 --- a/cheri/sail_latex/sailfndecodeSomeADD.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100000) = - #\hyperref[zSome]{Some}#(#\hyperref[zADD]{ADD}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeADDI.tex b/cheri/sail_latex/sailfndecodeSomeADDI.tex deleted file mode 100644 index 7706322f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeADDI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001000 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zADDI]{ADDI}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeADDIU.tex b/cheri/sail_latex/sailfndecodeSomeADDIU.tex deleted file mode 100644 index 27972a96..00000000 --- a/cheri/sail_latex/sailfndecodeSomeADDIU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001001 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zADDIU]{ADDIU}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeADDU.tex b/cheri/sail_latex/sailfndecodeSomeADDU.tex deleted file mode 100644 index 259cdfc9..00000000 --- a/cheri/sail_latex/sailfndecodeSomeADDU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100001) = - #\hyperref[zSome]{Some}#(#\hyperref[zADDU]{ADDU}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeAND.tex b/cheri/sail_latex/sailfndecodeSomeAND.tex deleted file mode 100644 index ecc6f7cb..00000000 --- a/cheri/sail_latex/sailfndecodeSomeAND.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100100) = - #\hyperref[zSome]{Some}#(#\hyperref[zAND]{AND}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeANDI.tex b/cheri/sail_latex/sailfndecodeSomeANDI.tex deleted file mode 100644 index fea6a112..00000000 --- a/cheri/sail_latex/sailfndecodeSomeANDI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001100 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zANDI]{ANDI}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeBCMPZ.tex b/cheri/sail_latex/sailfndecodeSomeBCMPZ.tex deleted file mode 100644 index 3221c8a3..00000000 --- a/cheri/sail_latex/sailfndecodeSomeBCMPZ.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b00000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, LT, false, false)) /* BLTZ */ diff --git a/cheri/sail_latex/sailfndecodeSomeBEQ.tex b/cheri/sail_latex/sailfndecodeSomeBEQ.tex deleted file mode 100644 index e520223e..00000000 --- a/cheri/sail_latex/sailfndecodeSomeBEQ.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000100 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBEQ]{BEQ}#(rs, rt, imm, false, false)) /* BEQ */ diff --git a/cheri/sail_latex/sailfndecodeSomeBREAK.tex b/cheri/sail_latex/sailfndecodeSomeBREAK.tex deleted file mode 100644 index e4978b0a..00000000 --- a/cheri/sail_latex/sailfndecodeSomeBREAK.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ code : #\hyperref[zbits]{bits}#(20) @ 0b001101) = - #\hyperref[zSome]{Some}#(#\hyperref[zBREAK]{BREAK}#()) /* code is ignored */ diff --git a/cheri/sail_latex/sailfndecodeSomeCACHE.tex b/cheri/sail_latex/sailfndecodeSomeCACHE.tex deleted file mode 100644 index c9f100fe..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCACHE.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b101111 @ base : regno @ op : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zCACHE]{CACHE}#(base, op, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeCAndPerm.tex b/cheri/sail_latex/sailfndecodeSomeCAndPerm.tex deleted file mode 100644 index 04f8dbb2..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCAndPerm.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00100 @ cd : regno @ cb : regno @ rt : regno @ 0b000 @ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCAndPerm]{CAndPerm}#(cd, cb, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCBX.tex b/cheri/sail_latex/sailfndecodeSomeCBX.tex deleted file mode 100644 index f009388f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCBX.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01001 @ cd : regno @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zCBX]{CBX}#(cd, imm, true)) /* CBTU */ diff --git a/cheri/sail_latex/sailfndecodeSomeCBZ.tex b/cheri/sail_latex/sailfndecodeSomeCBZ.tex deleted file mode 100644 index db46dbd2..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCBZ.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10001 @ cd : regno @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zCBZ]{CBZ}#(cd, imm, false)) /* CBEZ */ diff --git a/cheri/sail_latex/sailfndecodeSomeCBuildCap.tex b/cheri/sail_latex/sailfndecodeSomeCBuildCap.tex deleted file mode 100644 index c070e1be..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCBuildCap.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ ct : regno @ 0b011101) = #\hyperref[zSome]{Some}#(#\hyperref[zCBuildCap]{CBuildCap}#(cd, cb, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCCSeal.tex b/cheri/sail_latex/sailfndecodeSomeCCSeal.tex deleted file mode 100644 index 4703af82..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCCSeal.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ ct : regno @ 0b011111) = #\hyperref[zSome]{Some}#(#\hyperref[zCCSeal]{CCSeal}#(cd, cs, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCCall.tex b/cheri/sail_latex/sailfndecodeSomeCCall.tex deleted file mode 100644 index 32395a34..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCCall.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00101 @ cs : regno @ cb : regno @ selector : #\hyperref[zbits]{bits}#(11)) = #\hyperref[zSome]{Some}#(#\hyperref[zCCall]{CCall}#(cs, cb, selector)) diff --git a/cheri/sail_latex/sailfndecodeSomeCCheckPerm.tex b/cheri/sail_latex/sailfndecodeSomeCCheckPerm.tex deleted file mode 100644 index 1d293316..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCCheckPerm.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01011 @ cs : regno @ 0b00000 @ rt : regno @ 0b000@ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCCheckPerm]{CCheckPerm}#(cs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCCheckType.tex b/cheri/sail_latex/sailfndecodeSomeCCheckType.tex deleted file mode 100644 index 85b4f5ee..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCCheckType.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01011 @ cs : regno @ cb : regno @ 0b00000 @ 0b000@ 0b001) = #\hyperref[zSome]{Some}#(#\hyperref[zCCheckType]{CCheckType}#(cs, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCClearTag.tex b/cheri/sail_latex/sailfndecodeSomeCClearTag.tex deleted file mode 100644 index aad3e0e4..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCClearTag.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00100 @ cd : regno @ cb : regno @ 0b00000 @ 0b000@ 0b101) = #\hyperref[zSome]{Some}#(#\hyperref[zCClearTag]{CClearTag}#(cd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCCopyType.tex b/cheri/sail_latex/sailfndecodeSomeCCopyType.tex deleted file mode 100644 index 6c7a5fb8..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCCopyType.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ ct : regno @ 0b011110) = #\hyperref[zSome]{Some}#(#\hyperref[zCCopyType]{CCopyType}#(cd, cb, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCFromPtr.tex b/cheri/sail_latex/sailfndecodeSomeCFromPtr.tex deleted file mode 100644 index 9c992ac0..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCFromPtr.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00100 @ cd : regno @ cb : regno @ rt : regno @ 0b000@ 0b111) = #\hyperref[zSome]{Some}#(#\hyperref[zCFromPtr]{CFromPtr}#(cd, cb, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetAddr.tex b/cheri/sail_latex/sailfndecodeSomeCGetAddr.tex deleted file mode 100644 index 89672867..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetAddr.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cb : regno @ sel : regno @ 0b01111 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetAddr]{CGetAddr}#(cb, sel)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetBase.tex b/cheri/sail_latex/sailfndecodeSomeCGetBase.tex deleted file mode 100644 index 3ff0c663..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetBase.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b010) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetBase]{CGetBase}#(rd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetCauserd.tex b/cheri/sail_latex/sailfndecodeSomeCGetCauserd.tex deleted file mode 100644 index 4ffeb4ab..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetCauserd.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ 0b00000 @ 0b00000000 @ 0b100) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetCause]{CGetCause}#(rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetLen.tex b/cheri/sail_latex/sailfndecodeSomeCGetLen.tex deleted file mode 100644 index 2a39bae6..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetLen.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b011) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetLen]{CGetLen}#(rd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetOffset.tex b/cheri/sail_latex/sailfndecodeSomeCGetOffset.tex deleted file mode 100644 index 7ac298c2..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetOffset.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01101 @ rd : regno @ cb : regno @ 0b00000000 @ 0b010) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetOffset]{CGetOffset}#(rd, cb)) /* NB encoding does not follow pattern */ diff --git a/cheri/sail_latex/sailfndecodeSomeCGetPCCSetOffset.tex b/cheri/sail_latex/sailfndecodeSomeCGetPCCSetOffset.tex deleted file mode 100644 index dd92b2fd..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetPCCSetOffset.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ rs : regno @ 0b00111 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetPCCSetOffset]{CGetPCCSetOffset}#(cd, rs)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetPCCcd.tex b/cheri/sail_latex/sailfndecodeSomeCGetPCCcd.tex deleted file mode 100644 index 5357a1e4..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetPCCcd.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ 0b00000 @ 0b11111 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetPCC]{CGetPCC}#(cd)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetPerm.tex b/cheri/sail_latex/sailfndecodeSomeCGetPerm.tex deleted file mode 100644 index 0a14b6a1..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetPerm.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetPerm]{CGetPerm}#(rd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetSealed.tex b/cheri/sail_latex/sailfndecodeSomeCGetSealed.tex deleted file mode 100644 index c7511dfa..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetSealed.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b110) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetSealed]{CGetSealed}#(rd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetTag.tex b/cheri/sail_latex/sailfndecodeSomeCGetTag.tex deleted file mode 100644 index 794216a2..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetTag.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b101) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetTag]{CGetTag}#(rd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCGetType.tex b/cheri/sail_latex/sailfndecodeSomeCGetType.tex deleted file mode 100644 index 1568e5a4..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCGetType.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000000 @ 0b001) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetType]{CGetType}#(rd, cb)) diff --git a/cheri/sail_latex/sailfndecodeSomeCIncOffset.tex b/cheri/sail_latex/sailfndecodeSomeCIncOffset.tex deleted file mode 100644 index 893e774b..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCIncOffset.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01101 @ cd : regno @ cb : regno @ rt : regno @ 0b000 @ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCIncOffset]{CIncOffset}#(cd, cb, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCIncOffsetImmediate.tex b/cheri/sail_latex/sailfndecodeSomeCIncOffsetImmediate.tex deleted file mode 100644 index a0287341..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCIncOffsetImmediate.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10011 @ cd : regno @ cb : regno @ imm : #\hyperref[zbits]{bits}#(11)) = #\hyperref[zSome]{Some}#(#\hyperref[zCIncOffsetImmediate]{CIncOffsetImmediate}#(cd, cb, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeCJALR.tex b/cheri/sail_latex/sailfndecodeSomeCJALR.tex deleted file mode 100644 index 6d67580e..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCJALR.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00111 @ cd : regno @ cb : regno @ 0b00000 @ 0b000000) = #\hyperref[zSome]{Some}#(#\hyperref[zCJALR]{CJALR}#(cd, cb, true)) /* CJALR */ diff --git a/cheri/sail_latex/sailfndecodeSomeCLC.tex b/cheri/sail_latex/sailfndecodeSomeCLC.tex deleted file mode 100644 index ee20ffd2..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCLC.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110110 @ cd : regno @ cb : regno @ rt : regno @ offset : #\hyperref[zbits]{bits}#(11)) = #\hyperref[zSome]{Some}#(#\hyperref[zCLC]{CLC}#(cd, cb, rt, #\hyperref[zsignzyextend]{sign\_extend}#(offset), false)) /* CLC */ diff --git a/cheri/sail_latex/sailfndecodeSomeCLoad.tex b/cheri/sail_latex/sailfndecodeSomeCLoad.tex deleted file mode 100644 index 4f0e7692..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCLoad.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b00) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, false, B, false)) /* CLBU */ diff --git a/cheri/sail_latex/sailfndecodeSomeCMOVX.tex b/cheri/sail_latex/sailfndecodeSomeCMOVX.tex deleted file mode 100644 index 57f4de7c..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCMOVX.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ 0b01010 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCMOVX]{CMOVX}#(cd, cs, 0b00000, false)) /* CMOVE */ diff --git a/cheri/sail_latex/sailfndecodeSomeCPtrCmp.tex b/cheri/sail_latex/sailfndecodeSomeCPtrCmp.tex deleted file mode 100644 index 31f83677..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCPtrCmp.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CEQ)) diff --git a/cheri/sail_latex/sailfndecodeSomeCReadHwr.tex b/cheri/sail_latex/sailfndecodeSomeCReadHwr.tex deleted file mode 100644 index 0bacf907..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCReadHwr.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ sel : regno @ 0b01101 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCReadHwr]{CReadHwr}#(cd, sel)) diff --git a/cheri/sail_latex/sailfndecodeSomeCReturn.tex b/cheri/sail_latex/sailfndecodeSomeCReturn.tex deleted file mode 100644 index 9e773418..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCReturn.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00110 @ 0b000000000000000000000) = #\hyperref[zSome]{Some}#(#\hyperref[zCReturn]{CReturn}#()) diff --git a/cheri/sail_latex/sailfndecodeSomeCSC.tex b/cheri/sail_latex/sailfndecodeSomeCSC.tex deleted file mode 100644 index 1271b654..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSC.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111110 @ cs : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(11)) = #\hyperref[zSome]{Some}#(#\hyperref[zCSC]{CSC}#(cs, cb, rt, 0b00000, offset, false)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSeal.tex b/cheri/sail_latex/sailfndecodeSomeCSeal.tex deleted file mode 100644 index 91cad204..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSeal.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00010 @ cd : regno @ cs : regno @ ct : regno @ 0b000@ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCSeal]{CSeal}#(cd, cs, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSetBounds.tex b/cheri/sail_latex/sailfndecodeSomeCSetBounds.tex deleted file mode 100644 index 0675556f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSetBounds.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00001 @ cd : regno @ cb : regno @ rt : regno @ 0b000000) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetBounds]{CSetBounds}#(cd, cb, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSetBoundsExact.tex b/cheri/sail_latex/sailfndecodeSomeCSetBoundsExact.tex deleted file mode 100644 index 39caef88..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSetBoundsExact.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001001) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetBoundsExact]{CSetBoundsExact}#(cd, cs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSetBoundsImmediate.tex b/cheri/sail_latex/sailfndecodeSomeCSetBoundsImmediate.tex deleted file mode 100644 index ce53cb78..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSetBoundsImmediate.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10100 @ cd : regno @ cb : regno @ imm : #\hyperref[zbits]{bits}#(11)) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetBoundsImmediate]{CSetBoundsImmediate}#(cd, cb, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSetCausers.tex b/cheri/sail_latex/sailfndecodeSomeCSetCausers.tex deleted file mode 100644 index a775811b..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSetCausers.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rs : regno @ 0b00010 @ 0b11111 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetCause]{CSetCause}#(rs)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSetCausert.tex b/cheri/sail_latex/sailfndecodeSomeCSetCausert.tex deleted file mode 100644 index dc995af3..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSetCausert.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00100 @ 0b00000 @ 0b00000 @ rt : regno @ 0b000 @ 0b100) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetCause]{CSetCause}#(rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCSetOffset.tex b/cheri/sail_latex/sailfndecodeSomeCSetOffset.tex deleted file mode 100644 index f2b367c4..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSetOffset.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01101 @ cd : regno @ cb : regno @ rt : regno @ 0b000 @ 0b001) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetOffset]{CSetOffset}#(cd, cb, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeCStore.tex b/cheri/sail_latex/sailfndecodeSomeCStore.tex deleted file mode 100644 index e93884fc..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCStore.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b00) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, rt, 0b00000, offset, B, false)) /* CSB */ diff --git a/cheri/sail_latex/sailfndecodeSomeCSub.tex b/cheri/sail_latex/sailfndecodeSomeCSub.tex deleted file mode 100644 index bc2347e5..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCSub.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rt : regno @ cb : regno @ cs : regno @ 0b001010) = #\hyperref[zSome]{Some}#(#\hyperref[zCSub]{CSub}#(rt, cb, cs)) diff --git a/cheri/sail_latex/sailfndecodeSomeCTestSubset.tex b/cheri/sail_latex/sailfndecodeSomeCTestSubset.tex deleted file mode 100644 index 1f950ad8..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCTestSubset.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ ct : regno @ 0b100000) = #\hyperref[zSome]{Some}#(#\hyperref[zCTestSubset]{CTestSubset}#(rd, cb, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCToPtr.tex b/cheri/sail_latex/sailfndecodeSomeCToPtr.tex deleted file mode 100644 index aac23e6c..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCToPtr.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01100 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCToPtr]{CToPtr}#(rd, cb, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCUnseal.tex b/cheri/sail_latex/sailfndecodeSomeCUnseal.tex deleted file mode 100644 index 50de73da..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCUnseal.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00011 @ cd : regno @ cs : regno @ ct : regno @ 0b000@ 0b000) = #\hyperref[zSome]{Some}#(#\hyperref[zCUnseal]{CUnseal}#(cd, cs, ct)) diff --git a/cheri/sail_latex/sailfndecodeSomeCWriteHwr.tex b/cheri/sail_latex/sailfndecodeSomeCWriteHwr.tex deleted file mode 100644 index 663fa792..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCWriteHwr.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cb : regno @ sel : regno @ 0b01110 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCWriteHwr]{CWriteHwr}#(cb, sel)) diff --git a/cheri/sail_latex/sailfndecodeSomeClearRegs.tex b/cheri/sail_latex/sailfndecodeSomeClearRegs.tex deleted file mode 100644 index 37c28d29..00000000 --- a/cheri/sail_latex/sailfndecodeSomeClearRegs.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01111 @ 0b00000 @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zClearRegs]{ClearRegs}#(GPLo, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeCtwoDumprt.tex b/cheri/sail_latex/sailfndecodeSomeCtwoDumprt.tex deleted file mode 100644 index cccfa876..00000000 --- a/cheri/sail_latex/sailfndecodeSomeCtwoDumprt.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00100 @ rt : regno @ 0x0006) = #\hyperref[zSome]{Some}#(#\hyperref[zCtwoDump]{C2Dump}#(rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDADD.tex b/cheri/sail_latex/sailfndecodeSomeDADD.tex deleted file mode 100644 index 84d05d11..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDADD.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101100) = - #\hyperref[zSome]{Some}#(#\hyperref[zDADD]{DADD}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeDADDI.tex b/cheri/sail_latex/sailfndecodeSomeDADDI.tex deleted file mode 100644 index 27f4cab7..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDADDI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011000 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zDADDI]{DADDI}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeDADDIU.tex b/cheri/sail_latex/sailfndecodeSomeDADDIU.tex deleted file mode 100644 index 66ffc405..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDADDIU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011001 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zDADDIU]{DADDIU}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeDADDU.tex b/cheri/sail_latex/sailfndecodeSomeDADDU.tex deleted file mode 100644 index 558ebacf..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDADDU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101101) = - #\hyperref[zSome]{Some}#(#\hyperref[zDADDU]{DADDU}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeDDIV.tex b/cheri/sail_latex/sailfndecodeSomeDDIV.tex deleted file mode 100644 index 7e37f87d..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDDIV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011110) = - #\hyperref[zSome]{Some}#(#\hyperref[zDDIV]{DDIV}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDDIVU.tex b/cheri/sail_latex/sailfndecodeSomeDDIVU.tex deleted file mode 100644 index b34ce40f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDDIVU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011111) = - #\hyperref[zSome]{Some}#(#\hyperref[zDDIVU]{DDIVU}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDIV.tex b/cheri/sail_latex/sailfndecodeSomeDIV.tex deleted file mode 100644 index f9d47a4f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDIV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011010) = - #\hyperref[zSome]{Some}#(#\hyperref[zDIV]{DIV}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDIVU.tex b/cheri/sail_latex/sailfndecodeSomeDIVU.tex deleted file mode 100644 index 0e9c1385..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDIVU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011011) = - #\hyperref[zSome]{Some}#(#\hyperref[zDIVU]{DIVU}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDMULT.tex b/cheri/sail_latex/sailfndecodeSomeDMULT.tex deleted file mode 100644 index 0d2b12b5..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDMULT.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011100) = - #\hyperref[zSome]{Some}#(#\hyperref[zDMULT]{DMULT}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDMULTU.tex b/cheri/sail_latex/sailfndecodeSomeDMULTU.tex deleted file mode 100644 index 53be685e..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDMULTU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011101) = - #\hyperref[zSome]{Some}#(#\hyperref[zDMULTU]{DMULTU}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSLL.tex b/cheri/sail_latex/sailfndecodeSomeDSLL.tex deleted file mode 100644 index 824f4937..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSLL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : #\hyperref[zbits]{bits}#(5) @ 0b111000) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSLL]{DSLL}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSLLV.tex b/cheri/sail_latex/sailfndecodeSomeDSLLV.tex deleted file mode 100644 index 707e642c..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSLLV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b010100) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSLLV]{DSLLV}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSLLthreetwo.tex b/cheri/sail_latex/sailfndecodeSomeDSLLthreetwo.tex deleted file mode 100644 index 431ca9e7..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSLLthreetwo.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : #\hyperref[zbits]{bits}#(5) @ 0b111100) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSLLthreetwo]{DSLL32}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSRA.tex b/cheri/sail_latex/sailfndecodeSomeDSRA.tex deleted file mode 100644 index 25dfe705..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSRA.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : #\hyperref[zbits]{bits}#(5) @ 0b111011) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSRA]{DSRA}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSRAV.tex b/cheri/sail_latex/sailfndecodeSomeDSRAV.tex deleted file mode 100644 index b2b92bcb..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSRAV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b010111) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSRAV]{DSRAV}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSRAthreetwo.tex b/cheri/sail_latex/sailfndecodeSomeDSRAthreetwo.tex deleted file mode 100644 index a95f3995..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSRAthreetwo.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : #\hyperref[zbits]{bits}#(5) @ 0b111111) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSRAthreetwo]{DSRA32}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSRL.tex b/cheri/sail_latex/sailfndecodeSomeDSRL.tex deleted file mode 100644 index d13257d3..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSRL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : #\hyperref[zbits]{bits}#(5) @ 0b111010) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSRL]{DSRL}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSRLV.tex b/cheri/sail_latex/sailfndecodeSomeDSRLV.tex deleted file mode 100644 index 626895ac..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSRLV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b010110) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSRLV]{DSRLV}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSRLthreetwo.tex b/cheri/sail_latex/sailfndecodeSomeDSRLthreetwo.tex deleted file mode 100644 index edfd4ace..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSRLthreetwo.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : #\hyperref[zbits]{bits}#(5) @ 0b111110) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSRLthreetwo]{DSRL32}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSUB.tex b/cheri/sail_latex/sailfndecodeSomeDSUB.tex deleted file mode 100644 index 0a402a4f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSUB.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101110) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSUB]{DSUB}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeDSUBU.tex b/cheri/sail_latex/sailfndecodeSomeDSUBU.tex deleted file mode 100644 index 635c5d1f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeDSUBU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101111) = - #\hyperref[zSome]{Some}#(#\hyperref[zDSUBU]{DSUBU}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeERET.tex b/cheri/sail_latex/sailfndecodeSomeERET.tex deleted file mode 100644 index 95d4fa19..00000000 --- a/cheri/sail_latex/sailfndecodeSomeERET.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b1 @ 0b0000000000000000000 @ 0b011000) = - #\hyperref[zSome]{Some}#(#\hyperref[zERET]{ERET}#()) diff --git a/cheri/sail_latex/sailfndecodeSomeHCF.tex b/cheri/sail_latex/sailfndecodeSomeHCF.tex deleted file mode 100644 index 6f335350..00000000 --- a/cheri/sail_latex/sailfndecodeSomeHCF.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b00100 @ rt : regno @ 0b10111 @ 0b00000000000) = - #\hyperref[zSome]{Some}#(#\hyperref[zHCF]{HCF}#()) diff --git a/cheri/sail_latex/sailfndecodeSomeJALR.tex b/cheri/sail_latex/sailfndecodeSomeJALR.tex deleted file mode 100644 index 9d31119a..00000000 --- a/cheri/sail_latex/sailfndecodeSomeJALR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ 0b00000 @ rd : regno @ hint : regno @ 0b001001) = - #\hyperref[zSome]{Some}#(#\hyperref[zJALR]{JALR}#(rs, rd)) /* hint is ignored */ diff --git a/cheri/sail_latex/sailfndecodeSomeJALoffset.tex b/cheri/sail_latex/sailfndecodeSomeJALoffset.tex deleted file mode 100644 index 6f89b7a2..00000000 --- a/cheri/sail_latex/sailfndecodeSomeJALoffset.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000011 @ offset : #\hyperref[zbits]{bits}#(26)) = - #\hyperref[zSome]{Some}#(#\hyperref[zJAL]{JAL}#(offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeJRrs.tex b/cheri/sail_latex/sailfndecodeSomeJRrs.tex deleted file mode 100644 index 11f38614..00000000 --- a/cheri/sail_latex/sailfndecodeSomeJRrs.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ 0b00000 @ 0b00000 @ hint : regno @ 0b001000) = - #\hyperref[zSome]{Some}#(#\hyperref[zJR]{JR}#(rs)) /* hint is ignored */ diff --git a/cheri/sail_latex/sailfndecodeSomeJoffset.tex b/cheri/sail_latex/sailfndecodeSomeJoffset.tex deleted file mode 100644 index b7fe0c10..00000000 --- a/cheri/sail_latex/sailfndecodeSomeJoffset.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000010 @ offset : #\hyperref[zbits]{bits}#(26)) = - #\hyperref[zSome]{Some}#(#\hyperref[zJ]{J}#(offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeLDL.tex b/cheri/sail_latex/sailfndecodeSomeLDL.tex deleted file mode 100644 index d0aa03e7..00000000 --- a/cheri/sail_latex/sailfndecodeSomeLDL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b011010 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLDL]{LDL}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeLDR.tex b/cheri/sail_latex/sailfndecodeSomeLDR.tex deleted file mode 100644 index e2587245..00000000 --- a/cheri/sail_latex/sailfndecodeSomeLDR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b011011 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLDR]{LDR}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeLUI.tex b/cheri/sail_latex/sailfndecodeSomeLUI.tex deleted file mode 100644 index e26f924d..00000000 --- a/cheri/sail_latex/sailfndecodeSomeLUI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001111 @ 0b00000 @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLUI]{LUI}#(rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeLWL.tex b/cheri/sail_latex/sailfndecodeSomeLWL.tex deleted file mode 100644 index 12e0398d..00000000 --- a/cheri/sail_latex/sailfndecodeSomeLWL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b100010 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLWL]{LWL}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeLWR.tex b/cheri/sail_latex/sailfndecodeSomeLWR.tex deleted file mode 100644 index fbbe2a6c..00000000 --- a/cheri/sail_latex/sailfndecodeSomeLWR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b100110 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLWR]{LWR}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeLoad.tex b/cheri/sail_latex/sailfndecodeSomeLoad.tex deleted file mode 100644 index b9376877..00000000 --- a/cheri/sail_latex/sailfndecodeSomeLoad.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b100000 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(B, true, false, base, rt, offset)) /* LB */ diff --git a/cheri/sail_latex/sailfndecodeSomeMADD.tex b/cheri/sail_latex/sailfndecodeSomeMADD.tex deleted file mode 100644 index 3b8b9d75..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMADD.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000000) = - #\hyperref[zSome]{Some}#(#\hyperref[zMADD]{MADD}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeMADDU.tex b/cheri/sail_latex/sailfndecodeSomeMADDU.tex deleted file mode 100644 index a1b46968..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMADDU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000001) = - #\hyperref[zSome]{Some}#(#\hyperref[zMADDU]{MADDU}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeMFCzero.tex b/cheri/sail_latex/sailfndecodeSomeMFCzero.tex deleted file mode 100644 index 67608b6d..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMFCzero.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b00000 @ rt : regno @ rd : regno @ 0b00000000 @ sel : #\hyperref[zbits]{bits}#(3)) = - #\hyperref[zSome]{Some}#(#\hyperref[zMFCzero]{MFC0}#(rt, rd, sel, false)) /* MFC0 */ diff --git a/cheri/sail_latex/sailfndecodeSomeMFHIrd.tex b/cheri/sail_latex/sailfndecodeSomeMFHIrd.tex deleted file mode 100644 index 9f48db83..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMFHIrd.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b0000000000 @ rd : regno @ 0b00000 @ 0b010000) = - #\hyperref[zSome]{Some}#(#\hyperref[zMFHI]{MFHI}#(rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeMFLOrd.tex b/cheri/sail_latex/sailfndecodeSomeMFLOrd.tex deleted file mode 100644 index 6ea47d5b..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMFLOrd.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b0000000000 @ rd : regno @ 0b00000 @ 0b010010) = - #\hyperref[zSome]{Some}#(#\hyperref[zMFLO]{MFLO}#(rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeMOVN.tex b/cheri/sail_latex/sailfndecodeSomeMOVN.tex deleted file mode 100644 index e975a85c..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMOVN.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b001011) = - #\hyperref[zSome]{Some}#(#\hyperref[zMOVN]{MOVN}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeMOVZ.tex b/cheri/sail_latex/sailfndecodeSomeMOVZ.tex deleted file mode 100644 index a503217a..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMOVZ.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b001010) = - #\hyperref[zSome]{Some}#(#\hyperref[zMOVZ]{MOVZ}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeMSUB.tex b/cheri/sail_latex/sailfndecodeSomeMSUB.tex deleted file mode 100644 index bfc18834..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMSUB.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000100) = - #\hyperref[zSome]{Some}#(#\hyperref[zMSUB]{MSUB}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeMSUBU.tex b/cheri/sail_latex/sailfndecodeSomeMSUBU.tex deleted file mode 100644 index 07efaff8..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMSUBU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000101) = - #\hyperref[zSome]{Some}#(#\hyperref[zMSUBU]{MSUBU}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeMTCzero.tex b/cheri/sail_latex/sailfndecodeSomeMTCzero.tex deleted file mode 100644 index 890984a6..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMTCzero.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b00100 @ rt : regno @ rd : regno @ 0b00000000 @ sel : #\hyperref[zbits]{bits}#(3)) = - #\hyperref[zSome]{Some}#(#\hyperref[zMTCzero]{MTC0}#(rt, rd, sel, false)) /* MTC0 */ diff --git a/cheri/sail_latex/sailfndecodeSomeMTHIrs.tex b/cheri/sail_latex/sailfndecodeSomeMTHIrs.tex deleted file mode 100644 index bbe47eeb..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMTHIrs.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ 0b000000000000000 @ 0b010001) = - #\hyperref[zSome]{Some}#(#\hyperref[zMTHI]{MTHI}#(rs)) diff --git a/cheri/sail_latex/sailfndecodeSomeMTLOrs.tex b/cheri/sail_latex/sailfndecodeSomeMTLOrs.tex deleted file mode 100644 index b6e4f81a..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMTLOrs.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ 0b000000000000000 @ 0b010011) = - #\hyperref[zSome]{Some}#(#\hyperref[zMTLO]{MTLO}#(rs)) diff --git a/cheri/sail_latex/sailfndecodeSomeMUL.tex b/cheri/sail_latex/sailfndecodeSomeMUL.tex deleted file mode 100644 index 806554c1..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMUL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011100 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000010) = - #\hyperref[zSome]{Some}#(#\hyperref[zMUL]{MUL}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeMULT.tex b/cheri/sail_latex/sailfndecodeSomeMULT.tex deleted file mode 100644 index 3358669f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMULT.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011000) = - #\hyperref[zSome]{Some}#(#\hyperref[zMULT]{MULT}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeMULTU.tex b/cheri/sail_latex/sailfndecodeSomeMULTU.tex deleted file mode 100644 index 1de82a86..00000000 --- a/cheri/sail_latex/sailfndecodeSomeMULTU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011001) = - #\hyperref[zSome]{Some}#(#\hyperref[zMULTU]{MULTU}#(rs, rt)) diff --git a/cheri/sail_latex/sailfndecodeSomeNOR.tex b/cheri/sail_latex/sailfndecodeSomeNOR.tex deleted file mode 100644 index 591bd681..00000000 --- a/cheri/sail_latex/sailfndecodeSomeNOR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100111) = - #\hyperref[zSome]{Some}#(#\hyperref[zNOR]{NOR}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeOR.tex b/cheri/sail_latex/sailfndecodeSomeOR.tex deleted file mode 100644 index 4e4c898a..00000000 --- a/cheri/sail_latex/sailfndecodeSomeOR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100101) = - #\hyperref[zSome]{Some}#(#\hyperref[zOR]{OR}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeORI.tex b/cheri/sail_latex/sailfndecodeSomeORI.tex deleted file mode 100644 index ab0e3590..00000000 --- a/cheri/sail_latex/sailfndecodeSomeORI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001101 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zORI]{ORI}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeRDHWR.tex b/cheri/sail_latex/sailfndecodeSomeRDHWR.tex deleted file mode 100644 index ea58d589..00000000 --- a/cheri/sail_latex/sailfndecodeSomeRDHWR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011111 @ 0b00000 @ rt : regno @ rd : regno @ 0b00000 @ 0b111011) = - #\hyperref[zSome]{Some}#(#\hyperref[zRDHWR]{RDHWR}#(rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeRI.tex b/cheri/sail_latex/sailfndecodeSomeRI.tex deleted file mode 100644 index 33607cfb..00000000 --- a/cheri/sail_latex/sailfndecodeSomeRI.tex +++ /dev/null @@ -1 +0,0 @@ -function clause decode _ = #\hyperref[zSome]{Some}#(#\hyperref[zRI]{RI}#()) diff --git a/cheri/sail_latex/sailfndecodeSomeSDL.tex b/cheri/sail_latex/sailfndecodeSomeSDL.tex deleted file mode 100644 index bf001ec3..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSDL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b101100 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zSDL]{SDL}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeSDR.tex b/cheri/sail_latex/sailfndecodeSomeSDR.tex deleted file mode 100644 index 437d09b0..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSDR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b101101 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zSDR]{SDR}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeSLL.tex b/cheri/sail_latex/sailfndecodeSomeSLL.tex deleted file mode 100644 index 2d130736..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSLL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : regno @ 0b000000) = - #\hyperref[zSome]{Some}#(#\hyperref[zSLL]{SLL}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeSLLV.tex b/cheri/sail_latex/sailfndecodeSomeSLLV.tex deleted file mode 100644 index b06ee12d..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSLLV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000100) = - #\hyperref[zSome]{Some}#(#\hyperref[zSLLV]{SLLV}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSLT.tex b/cheri/sail_latex/sailfndecodeSomeSLT.tex deleted file mode 100644 index b6651698..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSLT.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101010) = - #\hyperref[zSome]{Some}#(#\hyperref[zSLT]{SLT}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSLTI.tex b/cheri/sail_latex/sailfndecodeSomeSLTI.tex deleted file mode 100644 index c1240f5b..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSLTI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001010 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zSLTI]{SLTI}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeSLTIU.tex b/cheri/sail_latex/sailfndecodeSomeSLTIU.tex deleted file mode 100644 index 72d15602..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSLTIU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001011 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zSLTIU]{SLTIU}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodeSomeSLTU.tex b/cheri/sail_latex/sailfndecodeSomeSLTU.tex deleted file mode 100644 index c735877d..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSLTU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101011) = - #\hyperref[zSome]{Some}#(#\hyperref[zSLTU]{SLTU}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSRA.tex b/cheri/sail_latex/sailfndecodeSomeSRA.tex deleted file mode 100644 index 2050a307..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSRA.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : regno @ 0b000011) = - #\hyperref[zSome]{Some}#(#\hyperref[zSRA]{SRA}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeSRAV.tex b/cheri/sail_latex/sailfndecodeSomeSRAV.tex deleted file mode 100644 index a198a715..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSRAV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000111) = - #\hyperref[zSome]{Some}#(#\hyperref[zSRAV]{SRAV}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSRL.tex b/cheri/sail_latex/sailfndecodeSomeSRL.tex deleted file mode 100644 index 80c0dd7a..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSRL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : regno @ 0b000010) = - #\hyperref[zSome]{Some}#(#\hyperref[zSRL]{SRL}#(rt, rd, sa)) diff --git a/cheri/sail_latex/sailfndecodeSomeSRLV.tex b/cheri/sail_latex/sailfndecodeSomeSRLV.tex deleted file mode 100644 index b06e51d9..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSRLV.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000110) = - #\hyperref[zSome]{Some}#(#\hyperref[zSRLV]{SRLV}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSUB.tex b/cheri/sail_latex/sailfndecodeSomeSUB.tex deleted file mode 100644 index 2ee4e29f..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSUB.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100010) = - #\hyperref[zSome]{Some}#(#\hyperref[zSUB]{SUB}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSUBU.tex b/cheri/sail_latex/sailfndecodeSomeSUBU.tex deleted file mode 100644 index 4f00e98b..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSUBU.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100011) = - #\hyperref[zSome]{Some}#(#\hyperref[zSUBU]{SUBU}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeSWL.tex b/cheri/sail_latex/sailfndecodeSomeSWL.tex deleted file mode 100644 index 208f2397..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSWL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b101010 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zSWL]{SWL}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeSWR.tex b/cheri/sail_latex/sailfndecodeSomeSWR.tex deleted file mode 100644 index 41ef1162..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSWR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}#(0b101110 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zSWR]{SWR}#(base, rt, offset)) diff --git a/cheri/sail_latex/sailfndecodeSomeSYNC.tex b/cheri/sail_latex/sailfndecodeSomeSYNC.tex deleted file mode 100644 index 12f85118..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSYNC.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ 0b00000 @ 0b00000 @ 0b00000 @ stype : regno @ 0b001111) = - #\hyperref[zSome]{Some}#(#\hyperref[zSYNC]{SYNC}#()) /* stype is currently ignored */ diff --git a/cheri/sail_latex/sailfndecodeSomeSYSCALL.tex b/cheri/sail_latex/sailfndecodeSomeSYSCALL.tex deleted file mode 100644 index bace77fa..00000000 --- a/cheri/sail_latex/sailfndecodeSomeSYSCALL.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ code : #\hyperref[zbits]{bits}#(20) @ 0b001100) = - #\hyperref[zSome]{Some}#(#\hyperref[zSYSCALL]{SYSCALL}#()) /* code is ignored */ diff --git a/cheri/sail_latex/sailfndecodeSomeStore.tex b/cheri/sail_latex/sailfndecodeSomeStore.tex deleted file mode 100644 index 1a291fbd..00000000 --- a/cheri/sail_latex/sailfndecodeSomeStore.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b101000 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zStore]{Store}#(B, false, base, rt, offset)) /* SB */ diff --git a/cheri/sail_latex/sailfndecodeSomeTRAPIMM.tex b/cheri/sail_latex/sailfndecodeSomeTRAPIMM.tex deleted file mode 100644 index 90ed1745..00000000 --- a/cheri/sail_latex/sailfndecodeSomeTRAPIMM.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b01100 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, EQ)) /* TEQI */ diff --git a/cheri/sail_latex/sailfndecodeSomeTRAPREG.tex b/cheri/sail_latex/sailfndecodeSomeTRAPREG.tex deleted file mode 100644 index 66126500..00000000 --- a/cheri/sail_latex/sailfndecodeSomeTRAPREG.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ code : #\hyperref[zbits]{bits}#(10) @ 0b110000) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, GE)) /* TGE */ diff --git a/cheri/sail_latex/sailfndecodeSomeWAIT.tex b/cheri/sail_latex/sailfndecodeSomeWAIT.tex deleted file mode 100644 index 443840f8..00000000 --- a/cheri/sail_latex/sailfndecodeSomeWAIT.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0x80000 @ 0b100000) = - #\hyperref[zSome]{Some}#(#\hyperref[zWAIT]{WAIT}#()) /* we only accept code == 0 */ diff --git a/cheri/sail_latex/sailfndecodeSomeXOR.tex b/cheri/sail_latex/sailfndecodeSomeXOR.tex deleted file mode 100644 index f25d968e..00000000 --- a/cheri/sail_latex/sailfndecodeSomeXOR.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100110) = - #\hyperref[zSome]{Some}#(#\hyperref[zXOR]{XOR}#(rs, rt, rd)) diff --git a/cheri/sail_latex/sailfndecodeSomeXORI.tex b/cheri/sail_latex/sailfndecodeSomeXORI.tex deleted file mode 100644 index 018ca5d7..00000000 --- a/cheri/sail_latex/sailfndecodeSomeXORI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b001110 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zXORI]{XORI}#(rs, rt, imm)) diff --git a/cheri/sail_latex/sailfndecodefailureofnum.tex b/cheri/sail_latex/sailfndecodefailureofnum.tex deleted file mode 100644 index 2ad9ff6d..00000000 --- a/cheri/sail_latex/sailfndecodefailureofnum.tex +++ /dev/null @@ -1,6 +0,0 @@ -function decode_failure_of_num arg# = match arg# { - 0 => no_matching_pattern, - 1 => unsupported_instruction, - 2 => illegal_instruction, - _ => internal_error -} diff --git a/cheri/sail_latex/sailfndumpcptwostate.tex b/cheri/sail_latex/sailfndumpcptwostate.tex deleted file mode 100644 index 53ab717e..00000000 --- a/cheri/sail_latex/sailfndumpcptwostate.tex +++ /dev/null @@ -1,17 +0,0 @@ -function #\hyperref[zdumpzycptwozystate]{dump\_cp2\_state}# () = { - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP PCC", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC)))); - foreach(i from 0 to 31) { - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP REG ", #\hyperref[zconcatzystr]{concat\_str}#(#\hyperref[zstringzyofzyint]{string\_of\_int}#(i), #\hyperref[zcapToString]{capToString}#(#\hyperref[zreadCapReg]{readCapReg}#(#\hyperref[ztozybits]{to\_bits}#(5, i)))))) - }; - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 00", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(DDC)))); - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 01", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(CTLSU)))); - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 08", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(CTLSP)))); - /* TODO: these two should not be mirrored to match the FPGA */ - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 22", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KR1C)))); - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 23", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KR2C)))); - /* KCC, KDC, EPCC */ - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 29", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KCC)))); - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 30", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KDC)))); - #\hyperref[zprint]{print}#(#\hyperref[zconcatzystr]{concat\_str}#("DEBUG CAP HWREG 31", #\hyperref[zcapToString]{capToString}#(#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(EPCC)))); - -} diff --git a/cheri/sail_latex/sailfnexecuteADD.tex b/cheri/sail_latex/sailfnexecuteADD.tex deleted file mode 100644 index 2ad9da32..00000000 --- a/cheri/sail_latex/sailfnexecuteADD.tex +++ /dev/null @@ -1,13 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zADD]{ADD}#(rs, rt, rd)) = - { - opA : #\hyperref[zbits]{bits}#(64) = #\hyperref[zrGPR]{rGPR}#(rs); - opB : #\hyperref[zbits]{bits}#(64) = #\hyperref[zrGPR]{rGPR}#(rt); - if #\hyperref[zNotWordVal]{NotWordVal}#(opA) | #\hyperref[zNotWordVal]{NotWordVal}#(opB) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined /* XXX could exit instead */ - else - let sum33 : #\hyperref[zbits]{bits}#(33) = #\hyperref[zsignzyextend]{sign\_extend}#(opA[31 .. 0]) + #\hyperref[zsignzyextend]{sign\_extend}#(opB[31 .. 0])in - if sum33[32] != sum33[31] then - (#\hyperref[zSignalException]{SignalException}#(Ov)) - else - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(sum33[31..0]) - } diff --git a/cheri/sail_latex/sailfnexecuteADDI.tex b/cheri/sail_latex/sailfnexecuteADDI.tex deleted file mode 100644 index 07076225..00000000 --- a/cheri/sail_latex/sailfnexecuteADDI.tex +++ /dev/null @@ -1,12 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zADDI]{ADDI}#(rs, rt, imm)) = - { - opA = #\hyperref[zrGPR]{rGPR}#(rs); - if #\hyperref[zNotWordVal]{NotWordVal}#(opA) then - #\hyperref[zwGPR]{wGPR}#(rt) = undefined /* XXX could exit instead */ - else - let sum33 : #\hyperref[zbits]{bits}#(33) = #\hyperref[zsignzyextend]{sign\_extend}#(opA[31 .. 0]) + #\hyperref[zsignzyextend]{sign\_extend}#(imm) in - if sum33[32] != sum33[31] then - (#\hyperref[zSignalException]{SignalException}#(Ov)) - else - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zsignzyextend]{sign\_extend}#(sum33[31..0]) - } diff --git a/cheri/sail_latex/sailfnexecuteADDIU.tex b/cheri/sail_latex/sailfnexecuteADDIU.tex deleted file mode 100644 index 5be7b646..00000000 --- a/cheri/sail_latex/sailfnexecuteADDIU.tex +++ /dev/null @@ -1,8 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zADDIU]{ADDIU}#(rs, rt, imm)) = - { - opA = #\hyperref[zrGPR]{rGPR}#(rs); - if #\hyperref[zNotWordVal]{NotWordVal}#(opA) then - #\hyperref[zwGPR]{wGPR}#(rt) = undefined /* XXX could exit instead */ - else - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zsignzyextend]{sign\_extend}#((opA[31 .. 0]) + #\hyperref[zsignzyextend]{sign\_extend}#(imm)) - } diff --git a/cheri/sail_latex/sailfnexecuteADDU.tex b/cheri/sail_latex/sailfnexecuteADDU.tex deleted file mode 100644 index ec253078..00000000 --- a/cheri/sail_latex/sailfnexecuteADDU.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zADDU]{ADDU}#(rs, rt, rd)) = - { - opA = #\hyperref[zrGPR]{rGPR}#(rs); - opB = #\hyperref[zrGPR]{rGPR}#(rt); - if #\hyperref[zNotWordVal]{NotWordVal}#(opA) | #\hyperref[zNotWordVal]{NotWordVal}#(opB) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined - else - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(opA[31..0] + opB[31..0]) - } diff --git a/cheri/sail_latex/sailfnexecuteAND.tex b/cheri/sail_latex/sailfnexecuteAND.tex deleted file mode 100644 index f24435e8..00000000 --- a/cheri/sail_latex/sailfnexecuteAND.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zAND]{AND}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = (#\hyperref[zrGPR]{rGPR}#(rs) & #\hyperref[zrGPR]{rGPR}#(rt)) - } diff --git a/cheri/sail_latex/sailfnexecuteANDI.tex b/cheri/sail_latex/sailfnexecuteANDI.tex deleted file mode 100644 index 03305987..00000000 --- a/cheri/sail_latex/sailfnexecuteANDI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zANDI]{ANDI}# (rs, rt, imm)) = - { - #\hyperref[zwGPR]{wGPR}#(rt) = (#\hyperref[zrGPR]{rGPR}#(rs) & #\hyperref[zzzerozyextend]{zero\_extend}#(imm)) - } diff --git a/cheri/sail_latex/sailfnexecuteBCMPZ.tex b/cheri/sail_latex/sailfnexecuteBCMPZ.tex deleted file mode 100644 index ffaa5df3..00000000 --- a/cheri/sail_latex/sailfnexecuteBCMPZ.tex +++ /dev/null @@ -1,17 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, cmp, link, likely)) = - { - linkVal = PC + 8; - regVal = #\hyperref[zrGPR]{rGPR}#(rs); - condition = #\hyperref[zcompare]{compare}#(cmp, regVal, #\hyperref[zzzerozyextend]{zero\_extend}#(0b0)); - if (condition) then - { - let offset : #\hyperref[zbits]{bits}#(64) = (#\hyperref[zsignzyextend]{sign\_extend}#(imm @ 0b00) + 4) in - #\hyperref[zexecutezybranch]{execute\_branch}#(PC + offset); - } - else if (likely) then - { - nextPC = PC + 8 /* skip branch delay */ - }; - if (link) then - #\hyperref[zwGPR]{wGPR}#(0b11111) = linkVal - } diff --git a/cheri/sail_latex/sailfnexecuteBEQ.tex b/cheri/sail_latex/sailfnexecuteBEQ.tex deleted file mode 100644 index 348c1c0e..00000000 --- a/cheri/sail_latex/sailfnexecuteBEQ.tex +++ /dev/null @@ -1,13 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zBEQ]{BEQ}#(rs, rd, imm, ne, likely)) = - { - if ((#\hyperref[zrGPR]{rGPR}#(rs) == #\hyperref[zrGPR]{rGPR}#(rd)) ^ ne) then - { - let offset : #\hyperref[zbits]{bits}#(64) = (#\hyperref[zsignzyextend]{sign\_extend}#(imm @ 0b00) + 4) in - #\hyperref[zexecutezybranch]{execute\_branch}#(PC + offset); - } - else - { - if (likely) then - nextPC = PC + 8; /* skip branch delay */ - } - } diff --git a/cheri/sail_latex/sailfnexecuteBREAK.tex b/cheri/sail_latex/sailfnexecuteBREAK.tex deleted file mode 100644 index 06f15ea9..00000000 --- a/cheri/sail_latex/sailfnexecuteBREAK.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zBREAK]{BREAK}#()) = - { - (#\hyperref[zSignalException]{SignalException}#(Bp)) - } diff --git a/cheri/sail_latex/sailfnexecuteCACHE.tex b/cheri/sail_latex/sailfnexecuteCACHE.tex deleted file mode 100644 index 14ecf045..00000000 --- a/cheri/sail_latex/sailfnexecuteCACHE.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCACHE]{CACHE}#(base, op, imm)) = - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}# () /* pretty much a NOP because no caches */ diff --git a/cheri/sail_latex/sailfnexecuteCAndPerm.tex b/cheri/sail_latex/sailfnexecuteCAndPerm.tex deleted file mode 100644 index b2cc7bc3..00000000 --- a/cheri/sail_latex/sailfnexecuteCAndPerm.tex +++ /dev/null @@ -1,18 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zCAndPerm]{CAndPerm}#(cd, cb, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - let rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else - let perms = #\hyperref[zgetCapPerms]{getCapPerms}#(cb_val) in - let newCap = #\hyperref[zsetCapPerms]{setCapPerms}#(cb_val, (perms & rt_val[30..0])) in - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap); -} diff --git a/cheri/sail_latex/sailfnexecuteCBX.tex b/cheri/sail_latex/sailfnexecuteCBX.tex deleted file mode 100644 index 47463a93..00000000 --- a/cheri/sail_latex/sailfnexecuteCBX.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCBX]{CBX}#(cb, imm, notset)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (((#\hyperref[zreadCapReg]{readCapReg}#(cb)).tag) ^ notset) then - { - let offset : #\hyperref[zbits]{bits}#(64) = (#\hyperref[zsignzyextend]{sign\_extend}#(imm @ 0b00) + 4) in - #\hyperref[zexecutezybranch]{execute\_branch}#(PC + offset); - } -} diff --git a/cheri/sail_latex/sailfnexecuteCBZ.tex b/cheri/sail_latex/sailfnexecuteCBZ.tex deleted file mode 100644 index 99a6be08..00000000 --- a/cheri/sail_latex/sailfnexecuteCBZ.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCBZ]{CBZ}#(cb, imm, notzero)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (((#\hyperref[zreadCapReg]{readCapReg}#(cb)) == null_cap) ^ notzero) then - { - let offset : #\hyperref[zbits]{bits}#(64) = (#\hyperref[zsignzyextend]{sign\_extend}#(imm @ 0b00) + 4) in - #\hyperref[zexecutezybranch]{execute\_branch}#(PC + offset); - } -} diff --git a/cheri/sail_latex/sailfnexecuteCBuildCap.tex b/cheri/sail_latex/sailfnexecuteCBuildCap.tex deleted file mode 100644 index cff66cc3..00000000 --- a/cheri/sail_latex/sailfnexecuteCBuildCap.tex +++ /dev/null @@ -1,40 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCBuildCap]{CBuildCap}#(cd, cb, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - cb_base = #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - ct_base = #\hyperref[zgetCapBase]{getCapBase}#(ct_val); - cb_top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - ct_top = #\hyperref[zgetCapTop]{getCapTop}#(ct_val); - cb_perms = #\hyperref[zgetCapPerms]{getCapPerms}#(cb_val); - ct_perms = #\hyperref[zgetCapPerms]{getCapPerms}#(ct_val); - ct_offset = #\hyperref[zgetCapOffset]{getCapOffset}#(ct_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if ct_base < cb_base then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ct_top > cb_top then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ct_base > ct_top then /* check for length < 0 - possible because ct might be untagged */ - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else if (ct_perms & cb_perms) != ct_perms then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_UserDefViolation, cb) - else - let (exact, cd1) = #\hyperref[zsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[ztozybits]{to\_bits}#(64, ct_base), #\hyperref[ztozybits]{to\_bits}#(65, ct_top)) in - let (representable, cd2) = #\hyperref[zsetCapOffset]{setCapOffset}#(cd1, #\hyperref[ztozybits]{to\_bits}#(64, ct_offset)) in - let cd3 = #\hyperref[zsetCapPerms]{setCapPerms}#(cd2, ct_perms) in - { - assert(exact, ""); /* base and top came from ct originally so will be exact */ - assert(representable, ""); /* similarly offset should be representable XXX except for fastRepCheck */ - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, cd3); - } -} diff --git a/cheri/sail_latex/sailfnexecuteCCSeal.tex b/cheri/sail_latex/sailfnexecuteCCSeal.tex deleted file mode 100644 index 7a1bc402..00000000 --- a/cheri/sail_latex/sailfnexecuteCCSeal.tex +++ /dev/null @@ -1,37 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCCSeal]{CCSeal}#(cd, cs, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - ct_cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(ct_val); - ct_top = #\hyperref[zgetCapTop]{getCapTop}#(ct_val); - ct_base = #\hyperref[zgetCapBase]{getCapBase}#(ct_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if (#\hyperref[znot]{not}# (ct_val.tag)) | (#\hyperref[zgetCapCursor]{getCapCursor}#(ct_val) == #\hyperref[zunsigned]{unsigned}#(bitone ^^ 64)) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, cs_val) - else if (cs_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) - else if (ct_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, ct) - else if #\hyperref[znot]{not}# (ct_val.permit_seal) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitSealViolation, ct) - else if (ct_cursor < ct_base) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else if (ct_cursor >= ct_top) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else if (ct_cursor > max_otype) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else - let (success, newCap) = #\hyperref[zsealCap]{sealCap}#(cs_val, #\hyperref[ztozybits]{to\_bits}#(24, ct_cursor)) in - if #\hyperref[znot]{not}# (success) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cs) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) -} diff --git a/cheri/sail_latex/sailfnexecuteCCall.tex b/cheri/sail_latex/sailfnexecuteCCall.tex deleted file mode 100644 index 1cae71b0..00000000 --- a/cheri/sail_latex/sailfnexecuteCCall.tex +++ /dev/null @@ -1,32 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCCall]{CCall}#(cs, cb, 0b00000000000)) = /* selector=0 */ -{ - /* Partial implementation of CCall with checks in hardware, but raising a trap to perform trusted stack manipulation */ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - cs_cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cs_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if ((cs_val.otype) != (cb_val.otype)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) - else if #\hyperref[znot]{not}# (cs_val.permit_execute) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cs) - else if (cb_val.permit_execute) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cb) - else if (cs_cursor < #\hyperref[zgetCapBase]{getCapBase}#(cs_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) - else if (cs_cursor >= #\hyperref[zgetCapTop]{getCapTop}#(cs_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) - else - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_CallTrap, cs); -} diff --git a/cheri/sail_latex/sailfnexecuteCCheckPerm.tex b/cheri/sail_latex/sailfnexecuteCCheckPerm.tex deleted file mode 100644 index 1a4ac93c..00000000 --- a/cheri/sail_latex/sailfnexecuteCCheckPerm.tex +++ /dev/null @@ -1,13 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCCheckPerm]{CCheckPerm}#(cs, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - cs_perms : #\hyperref[zbits]{bits}#(64) = #\hyperref[zzzerozyextend]{zero\_extend}#(#\hyperref[zgetCapPerms]{getCapPerms}#(cs_val)); - rt_perms = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if ((cs_perms & rt_perms) != rt_perms) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_UserDefViolation, cs) -} diff --git a/cheri/sail_latex/sailfnexecuteCCheckType.tex b/cheri/sail_latex/sailfnexecuteCCheckType.tex deleted file mode 100644 index fa9da35a..00000000 --- a/cheri/sail_latex/sailfnexecuteCCheckType.tex +++ /dev/null @@ -1,20 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCCheckType]{CCheckType}#(cs, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if ((cs_val.otype) != (cb_val.otype)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) -} diff --git a/cheri/sail_latex/sailfnexecuteCClearTag.tex b/cheri/sail_latex/sailfnexecuteCClearTag.tex deleted file mode 100644 index 54863f96..00000000 --- a/cheri/sail_latex/sailfnexecuteCClearTag.tex +++ /dev/null @@ -1,13 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCClearTag]{CClearTag}#(cd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - { - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, {cb_val with tag=false}); - } -} diff --git a/cheri/sail_latex/sailfnexecuteCCopyType.tex b/cheri/sail_latex/sailfnexecuteCCopyType.tex deleted file mode 100644 index dd34a178..00000000 --- a/cheri/sail_latex/sailfnexecuteCCopyType.tex +++ /dev/null @@ -1,31 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCCopyType]{CCopyType}#(cd, cb, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - cb_base = #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - cb_top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - ct_otype = #\hyperref[zunsigned]{unsigned}#(ct_val.otype); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if (ct_val.sealed) then { - if ct_otype < cb_base then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ct_otype >= cb_top then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else - let (success, cap) = #\hyperref[zsetCapOffset]{setCapOffset}#(cb_val, #\hyperref[ztozybits]{to\_bits}#(64, ct_otype - cb_base)) in { - assert(success, ""); /* offset is in bounds so must succeed */ - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, cap); - } - } else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, #\hyperref[zintzytozycap]{int\_to\_cap}#(bitone ^^ 64)) -} diff --git a/cheri/sail_latex/sailfnexecuteCFromPtr.tex b/cheri/sail_latex/sailfnexecuteCFromPtr.tex deleted file mode 100644 index eeb1fdc6..00000000 --- a/cheri/sail_latex/sailfnexecuteCFromPtr.tex +++ /dev/null @@ -1,22 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCFromPtr]{CFromPtr}#(cd, cb, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (rt_val == 0x0000000000000000) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, null_cap) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else - let (success, newCap) = #\hyperref[zsetCapOffset]{setCapOffset}#(cb_val, rt_val) in - if (success) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, #\hyperref[zintzytozycap]{int\_to\_cap}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) + rt_val)) -} diff --git a/cheri/sail_latex/sailfnexecuteCGetAddr.tex b/cheri/sail_latex/sailfnexecuteCGetAddr.tex deleted file mode 100644 index dd35b2ce..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetAddr.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetAddr]{CGetAddr}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapCursor]{getCapCursor}#(capVal)); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetBase.tex b/cheri/sail_latex/sailfnexecuteCGetBase.tex deleted file mode 100644 index 305762b9..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetBase.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetBase]{CGetBase}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(capVal)); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetCause.tex b/cheri/sail_latex/sailfnexecuteCGetCause.tex deleted file mode 100644 index 1753022e..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetCause.tex +++ /dev/null @@ -1,8 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetCause]{CGetCause}#(rd)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if #\hyperref[znot]{not}# (#\hyperref[zpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# ()) then - #\hyperref[zraisezyctwozyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_AccessSystemRegsViolation) - else - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(CapCause.#\hyperref[zbits]{bits}#()) -} diff --git a/cheri/sail_latex/sailfnexecuteCGetLen.tex b/cheri/sail_latex/sailfnexecuteCGetLen.tex deleted file mode 100644 index 53450720..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetLen.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetLen]{CGetLen}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - let len65 = #\hyperref[zgetCapLength]{getCapLength}#(capVal) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[ztozybits]{to\_bits}#(64, if len65 > MAX_U64 then MAX_U64 else len65); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetOffset.tex b/cheri/sail_latex/sailfnexecuteCGetOffset.tex deleted file mode 100644 index de2e8e6c..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetOffset.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetOffset]{CGetOffset}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapOffset]{getCapOffset}#(capVal)); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetPCC.tex b/cheri/sail_latex/sailfnexecuteCGetPCC.tex deleted file mode 100644 index 08b9aa67..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetPCC.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetPCC]{CGetPCC}#(cd)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else - let pcc = (#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC)) in - let (success, pcc2) = #\hyperref[zsetCapOffset]{setCapOffset}#(pcc, PC) in - {assert (success, ""); /* guaranteed to be in-bounds */ - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, pcc2)}; -} diff --git a/cheri/sail_latex/sailfnexecuteCGetPCCSetOffset.tex b/cheri/sail_latex/sailfnexecuteCGetPCCSetOffset.tex deleted file mode 100644 index b9af822e..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetPCCSetOffset.tex +++ /dev/null @@ -1,14 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetPCCSetOffset]{CGetPCCSetOffset}#(cd, rs)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else - let pcc = (#\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC)) in - let rs_val = #\hyperref[zrGPR]{rGPR}#(rs) in - let (success, newPCC) = #\hyperref[zsetCapOffset]{setCapOffset}#(pcc, rs_val) in - if (success) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newPCC) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, #\hyperref[zintzytozycap]{int\_to\_cap}#(rs_val)); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetPerm.tex b/cheri/sail_latex/sailfnexecuteCGetPerm.tex deleted file mode 100644 index 8bde1b68..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetPerm.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetPerm]{CGetPerm}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(#\hyperref[zgetCapPerms]{getCapPerms}#(capVal)); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetSealed.tex b/cheri/sail_latex/sailfnexecuteCGetSealed.tex deleted file mode 100644 index fb51d742..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetSealed.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetSealed]{CGetSealed}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(capVal.sealed); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetTag.tex b/cheri/sail_latex/sailfnexecuteCGetTag.tex deleted file mode 100644 index 827aed6e..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetTag.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetTag]{CGetTag}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(capVal.tag); -} diff --git a/cheri/sail_latex/sailfnexecuteCGetType.tex b/cheri/sail_latex/sailfnexecuteCGetType.tex deleted file mode 100644 index abd4490d..00000000 --- a/cheri/sail_latex/sailfnexecuteCGetType.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCGetType]{CGetType}#(rd, cb)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else - let capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb) in - #\hyperref[zwGPR]{wGPR}#(rd) = if (capVal.sealed) - then #\hyperref[zzzerozyextend]{zero\_extend}#(capVal.otype) - else (bitone ^^ 64) -} diff --git a/cheri/sail_latex/sailfnexecuteCIncOffset.tex b/cheri/sail_latex/sailfnexecuteCIncOffset.tex deleted file mode 100644 index 4b4b1888..00000000 --- a/cheri/sail_latex/sailfnexecuteCIncOffset.tex +++ /dev/null @@ -1,18 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCIncOffset]{CIncOffset}#(cd, cb, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if ((cb_val.tag) & (cb_val.sealed) & (rt_val != 0x0000000000000000)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else - let (success, newCap) = #\hyperref[zincCapOffset]{incCapOffset}#(cb_val, rt_val) in - if (success) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, #\hyperref[zintzytozycap]{int\_to\_cap}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) + rt_val)) -} diff --git a/cheri/sail_latex/sailfnexecuteCIncOffsetImmediate.tex b/cheri/sail_latex/sailfnexecuteCIncOffsetImmediate.tex deleted file mode 100644 index d82f66c9..00000000 --- a/cheri/sail_latex/sailfnexecuteCIncOffsetImmediate.tex +++ /dev/null @@ -1,18 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCIncOffsetImmediate]{CIncOffsetImmediate}#(cd, cb, imm)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - let imm64 : #\hyperref[zbits]{bits}#(64) = #\hyperref[zsignzyextend]{sign\_extend}#(imm) in - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if ((cb_val.tag) & (cb_val.sealed)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else - let (success, newCap) = #\hyperref[zincCapOffset]{incCapOffset}#(cb_val, imm64) in - if (success) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, #\hyperref[zintzytozycap]{int\_to\_cap}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) + imm64)) -} diff --git a/cheri/sail_latex/sailfnexecuteCJALR.tex b/cheri/sail_latex/sailfnexecuteCJALR.tex deleted file mode 100644 index 76a5aa86..00000000 --- a/cheri/sail_latex/sailfnexecuteCJALR.tex +++ /dev/null @@ -1,35 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zCJALR]{CJALR}#(cd, cb, link)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - cb_ptr = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - cb_top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - cb_base= #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - if (link & #\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_execute) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cb) - else if (cb_ptr < cb_base) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ((cb_ptr + 4) > cb_top) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ((cb_ptr % 4) != 0) then - #\hyperref[zSignalException]{SignalException}#(AdEL) - else - { - if (link) then - let pcc = #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC) in - let (success, linkCap) = #\hyperref[zsetCapOffset]{setCapOffset}#(pcc, PC+8) in - if (success) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, linkCap) - else - assert(false, ""); - #\hyperref[zexecutezybranchzypcc]{execute\_branch\_pcc}#(cb_val); - } -} diff --git a/cheri/sail_latex/sailfnexecuteCLC.tex b/cheri/sail_latex/sailfnexecuteCLC.tex deleted file mode 100644 index a128ee88..00000000 --- a/cheri/sail_latex/sailfnexecuteCLC.tex +++ /dev/null @@ -1,44 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCLC]{CLC}#(cd, cb, rt, offset, linked)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_load) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) - else - { - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - vAddr = (cursor + #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)) + 16 * #\hyperref[zsigned]{signed}#(offset)) % #\hyperref[zpowtwo]{pow2}#(64); - vAddr64= #\hyperref[ztozybits]{to\_bits}#(64, vAddr); - if ((vAddr + cap_size) > #\hyperref[zgetCapTop]{getCapTop}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (vAddr < #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ((vAddr % cap_size) != 0) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) - else - { - let (pAddr, suppressTag) = #\hyperref[zTLBTranslateC]{TLBTranslateC}#(vAddr64, LoadData) in - let 'cd = #\hyperref[zunsigned]{unsigned}#(cd) in - if (linked) then - { - CP0LLBit = 0b1; - CP0LLAddr = pAddr; - let (tag, mem) = #\hyperref[zMEMrzytaggedzyreserve]{MEMr\_tagged\_reserve}#(pAddr) in - (*CapRegs[cd]) = #\hyperref[zmemBitsToCapBits]{memBitsToCapBits}#(tag & (cb_val.permit_load_cap) & (#\hyperref[znot]{not}# (suppressTag)), mem); - } - else - { - let (tag, mem) = #\hyperref[zMEMrzytagged]{MEMr\_tagged}#(pAddr) in - (*CapRegs[cd]) = #\hyperref[zmemBitsToCapBits]{memBitsToCapBits}#(tag & (cb_val.permit_load_cap) & (#\hyperref[znot]{not}# (suppressTag)), mem); - } - } - } -} diff --git a/cheri/sail_latex/sailfnexecuteCLoad.tex b/cheri/sail_latex/sailfnexecuteCLoad.tex deleted file mode 100644 index 399e63f0..00000000 --- a/cheri/sail_latex/sailfnexecuteCLoad.tex +++ /dev/null @@ -1,39 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, signext, width, linked)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_load) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) - else - { - let 'size = #\hyperref[zwordWidthBytes]{wordWidthBytes}#(width); - let cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - let vAddr = (cursor + #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)) + size*#\hyperref[zsigned]{signed}#(offset)) % #\hyperref[zpowtwo]{pow2}#(64); - let vAddr64 = #\hyperref[ztozybits]{to\_bits}#(64, vAddr); - if ((vAddr + size) > #\hyperref[zgetCapTop]{getCapTop}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (vAddr < #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if #\hyperref[znot]{not}# (#\hyperref[zisAddressAligned]{isAddressAligned}#(vAddr64, width)) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) - else - { - pAddr = (#\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr64, LoadData)); - memResult : #\hyperref[zbits]{bits}#(64) = if (linked) then - { - CP0LLBit = 0b1; - CP0LLAddr = pAddr; - #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzyreservezywrapper]{MEMr\_reserve\_wrapper}#(pAddr, size), signext) - } - else - #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr, size), signext); - #\hyperref[zwGPR]{wGPR}#(rd) = memResult; - } - } -} diff --git a/cheri/sail_latex/sailfnexecuteCMOVX.tex b/cheri/sail_latex/sailfnexecuteCMOVX.tex deleted file mode 100644 index 94039992..00000000 --- a/cheri/sail_latex/sailfnexecuteCMOVX.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCMOVX]{CMOVX}#(cd, cb, rt, ismovn)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if ((#\hyperref[zrGPR]{rGPR}#(rt) == #\hyperref[zzzeros]{zeros}#()) ^ ismovn) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd) = #\hyperref[zreadCapReg]{readCapReg}#(cb); -} diff --git a/cheri/sail_latex/sailfnexecuteCPtrCmp.tex b/cheri/sail_latex/sailfnexecuteCPtrCmp.tex deleted file mode 100644 index fc0f7c54..00000000 --- a/cheri/sail_latex/sailfnexecuteCPtrCmp.tex +++ /dev/null @@ -1,43 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, op)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else - { - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - let ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - equal = false; - ltu = false; - lts = false; - if (cb_val.tag != ct_val.tag) then - { - if #\hyperref[znot]{not}# (cb_val.tag) then - { - ltu = true; - lts = true; - } - } - else - { - cursor1 = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - cursor2 = #\hyperref[zgetCapCursor]{getCapCursor}#(ct_val); - equal = (cursor1 == cursor2); - ltu = (cursor1 < cursor2); - lts = #\hyperref[ztozybits]{to\_bits}#(64, cursor1) <_s #\hyperref[ztozybits]{to\_bits}#(64, cursor2); - }; - let cmp : bool = match op { - CEQ => equal, - CNE => #\hyperref[znot]{not}# (equal), - CLT => lts, - CLE => lts | equal, - CLTU => ltu, - CLEU => ltu | equal, - CEXEQ => cb_val == ct_val, - CNEXEQ => cb_val != ct_val - }; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}# (cmp) - } -} diff --git a/cheri/sail_latex/sailfnexecuteCReadHwr.tex b/cheri/sail_latex/sailfnexecuteCReadHwr.tex deleted file mode 100644 index cc347d08..00000000 --- a/cheri/sail_latex/sailfnexecuteCReadHwr.tex +++ /dev/null @@ -1,35 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCReadHwr]{CReadHwr}#(cd, sel)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let (needSup, needAccessSys) : (bool, bool) = match #\hyperref[zunsigned]{unsigned}#(sel) { - 0 => (false, false), /* DDC -- no access control */ - 1 => (false, false), /* CTLSU -- no access control */ - 8 => (false, true), /* CTLSP -- privileged TLS */ - 22 => (true, false), /* KR1C */ - 23 => (true, false), /* KR2C */ - 29 => (true, true), /* KCC */ - 30 => (true, true), /* KDC */ - 31 => (true, true), /* EPCC */ - _ => #\hyperref[zSignalException]{SignalException}#(ResI) - }; - if #\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if needAccessSys & #\hyperref[znot]{not}#(#\hyperref[zpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#()) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) - else if needSup & #\hyperref[znot]{not}#(#\hyperref[zgrantsAccess]{grantsAccess}#(#\hyperref[zgetAccessLevel]{getAccessLevel}#(), Supervisor)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) - else { - capVal : CapStruct = match #\hyperref[zunsigned]{unsigned}#(sel) { - 0 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(DDC), - 1 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(CTLSU), - 8 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(CTLSP), - 22 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KR1C), - 23 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KR2C), - 29 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KCC), - 30 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(KDC), - 31 => #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(EPCC), - _ => {assert(false, "should be unreachable code"); undefined} - }; - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, capVal); - }; -} diff --git a/cheri/sail_latex/sailfnexecuteCReturn.tex b/cheri/sail_latex/sailfnexecuteCReturn.tex deleted file mode 100644 index 67f07815..00000000 --- a/cheri/sail_latex/sailfnexecuteCReturn.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCReturn]{CReturn}#()) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - #\hyperref[zraisezyctwozyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_ReturnTrap) -} diff --git a/cheri/sail_latex/sailfnexecuteCSC.tex b/cheri/sail_latex/sailfnexecuteCSC.tex deleted file mode 100644 index cd89dcdf..00000000 --- a/cheri/sail_latex/sailfnexecuteCSC.tex +++ /dev/null @@ -1,48 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSC]{CSC}#(cs, cb, rt, rd, offset, conditional)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_store) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_store_cap) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitStoreCapViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_store_local_cap) & (cs_val.tag) & #\hyperref[znot]{not}# (cs_val.global) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitStoreLocalCapViolation, cb) - else - { - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - vAddr = (cursor + #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)) + 16 * #\hyperref[zsigned]{signed}#(offset)) % #\hyperref[zpowtwo]{pow2}#(64); - vAddr64= #\hyperref[ztozybits]{to\_bits}#(64, vAddr); - if ((vAddr + cap_size) > #\hyperref[zgetCapTop]{getCapTop}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (vAddr < #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if ((vAddr % cap_size) != 0) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr64) - else - { - let (pAddr, noStoreCap) = #\hyperref[zTLBTranslateC]{TLBTranslateC}#(vAddr64, StoreData) in - if (cs_val.tag & noStoreCap) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TLBNoStoreCap, cs) - else if (conditional) then - { - success = if (CP0LLBit[0]) then - #\hyperref[zMEMwzytaggedzyconditional]{MEMw\_tagged\_conditional}#(pAddr, cs_val.tag, #\hyperref[zcapStructToMemBits]{capStructToMemBits}#(cs_val)) - else - false; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(success); - } - else - #\hyperref[zMEMwzytagged]{MEMw\_tagged}#(pAddr, cs_val.tag, #\hyperref[zcapStructToMemBits]{capStructToMemBits}#(cs_val)); - } - } -} diff --git a/cheri/sail_latex/sailfnexecuteCSeal.tex b/cheri/sail_latex/sailfnexecuteCSeal.tex deleted file mode 100644 index bf062276..00000000 --- a/cheri/sail_latex/sailfnexecuteCSeal.tex +++ /dev/null @@ -1,37 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSeal]{CSeal}#(cd, cs, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - ct_cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(ct_val); - ct_top = #\hyperref[zgetCapTop]{getCapTop}#(ct_val); - ct_base = #\hyperref[zgetCapBase]{getCapBase}#(ct_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if #\hyperref[znot]{not}# (ct_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, ct) - else if (cs_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) - else if (ct_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, ct) - else if #\hyperref[znot]{not}# (ct_val.permit_seal) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitSealViolation, ct) - else if (ct_cursor < ct_base) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else if (ct_cursor >= ct_top) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else if (ct_cursor > max_otype) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else - let (success, newCap) = #\hyperref[zsealCap]{sealCap}#(cs_val, #\hyperref[ztozybits]{to\_bits}#(24, ct_cursor)) in - if #\hyperref[znot]{not}# (success) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cs) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) -} diff --git a/cheri/sail_latex/sailfnexecuteCSetBounds.tex b/cheri/sail_latex/sailfnexecuteCSetBounds.tex deleted file mode 100644 index b193425d..00000000 --- a/cheri/sail_latex/sailfnexecuteCSetBounds.tex +++ /dev/null @@ -1,25 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSetBounds]{CSetBounds}#(cd, cb, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - let rt_val = #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)); - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - base = #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - newTop = cursor + rt_val; - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if (cursor < base) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (newTop > top) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else - let (_, newCap) = #\hyperref[zsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[ztozybits]{to\_bits}#(64, cursor), #\hyperref[ztozybits]{to\_bits}#(65, newTop)) in - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) /* ignore exact */ -} diff --git a/cheri/sail_latex/sailfnexecuteCSetBoundsExact.tex b/cheri/sail_latex/sailfnexecuteCSetBoundsExact.tex deleted file mode 100644 index 29d049b1..00000000 --- a/cheri/sail_latex/sailfnexecuteCSetBoundsExact.tex +++ /dev/null @@ -1,28 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSetBoundsExact]{CSetBoundsExact}#(cd, cb, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - rt_val = #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)); - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - base = #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - newTop = cursor + rt_val; - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if (cursor < base) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (newTop > top) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else - let (exact, newCap) = #\hyperref[zsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[ztozybits]{to\_bits}#(64, cursor), #\hyperref[ztozybits]{to\_bits}#(65, newTop)) in - if #\hyperref[znot]{not}# (exact) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cb) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) -} diff --git a/cheri/sail_latex/sailfnexecuteCSetBoundsImmediate.tex b/cheri/sail_latex/sailfnexecuteCSetBoundsImmediate.tex deleted file mode 100644 index 2d3cfb44..00000000 --- a/cheri/sail_latex/sailfnexecuteCSetBoundsImmediate.tex +++ /dev/null @@ -1,25 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSetBoundsImmediate]{CSetBoundsImmediate}#(cd, cb, imm)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - immU = #\hyperref[zunsigned]{unsigned}#(imm); - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - base = #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - newTop = cursor + immU; - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if (cursor < base) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (newTop > top) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else - let (_, newCap) = #\hyperref[zsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[ztozybits]{to\_bits}#(64, cursor), #\hyperref[ztozybits]{to\_bits}#(65, newTop)) in - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) /* ignore exact */ -} diff --git a/cheri/sail_latex/sailfnexecuteCSetCause.tex b/cheri/sail_latex/sailfnexecuteCSetCause.tex deleted file mode 100644 index b6b9ca15..00000000 --- a/cheri/sail_latex/sailfnexecuteCSetCause.tex +++ /dev/null @@ -1,12 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSetCause]{CSetCause}#(rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if #\hyperref[znot]{not}# (#\hyperref[zpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# ()) then - #\hyperref[zraisezyctwozyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_AccessSystemRegsViolation) - else - { - let rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - CapCause->#\hyperref[zExcCode]{ExcCode}#() = rt_val[15..8]; - CapCause->#\hyperref[zRegNum]{RegNum}#() = rt_val[7..0]; - } -} diff --git a/cheri/sail_latex/sailfnexecuteCSetOffset.tex b/cheri/sail_latex/sailfnexecuteCSetOffset.tex deleted file mode 100644 index 6973667a..00000000 --- a/cheri/sail_latex/sailfnexecuteCSetOffset.tex +++ /dev/null @@ -1,18 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCSetOffset]{CSetOffset}#(cd, cb, rt)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - let rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if ((cb_val.tag) & (cb_val.sealed)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else - let (success, newCap) = #\hyperref[zsetCapOffset]{setCapOffset}#(cb_val, rt_val) in - if (success) then - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, newCap) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, #\hyperref[zintzytozycap]{int\_to\_cap}#(#\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) + rt_val)) -} diff --git a/cheri/sail_latex/sailfnexecuteCStore.tex b/cheri/sail_latex/sailfnexecuteCStore.tex deleted file mode 100644 index 6ab40e18..00000000 --- a/cheri/sail_latex/sailfnexecuteCStore.tex +++ /dev/null @@ -1,53 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCStore]{CStore}#(rs, cb, rt, rd, offset, width, conditional)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if #\hyperref[znot]{not}# (cb_val.permit_store) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) - else - { - size = #\hyperref[zwordWidthBytes]{wordWidthBytes}#(width); - cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val); - vAddr = (cursor + #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)) + size * #\hyperref[zsigned]{signed}#(offset)) % #\hyperref[zpowtwo]{pow2}#(64); - vAddr64= #\hyperref[ztozybits]{to\_bits}#(64, vAddr); - if ((vAddr + size) > #\hyperref[zgetCapTop]{getCapTop}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if (vAddr < #\hyperref[zgetCapBase]{getCapBase}#(cb_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) - else if #\hyperref[znot]{not}# (#\hyperref[zisAddressAligned]{isAddressAligned}#(vAddr64, width)) then - #\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr64) - else - { - pAddr = (#\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr64, StoreData)); - rs_val = #\hyperref[zrGPR]{rGPR}#(rs); - if (conditional) then - { - success : bool = if (CP0LLBit[0]) then - match width - { - B => #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 1, rs_val[7..0]), - H => #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 2, rs_val[15..0]), - W => #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 4, rs_val[31..0]), - D => #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 8, rs_val) - } - else - false; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(success); - } - else - match width - { - B => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 1) = rs_val[7..0], - H => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 2) = rs_val[15..0], - W => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 4) = rs_val[31..0], - D => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 8) = rs_val - } - } - } -} diff --git a/cheri/sail_latex/sailfnexecuteCSub.tex b/cheri/sail_latex/sailfnexecuteCSub.tex deleted file mode 100644 index 957b645f..00000000 --- a/cheri/sail_latex/sailfnexecuteCSub.tex +++ /dev/null @@ -1,14 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zCSub]{CSub}#(rd, cb, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else - { - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val) - #\hyperref[zgetCapCursor]{getCapCursor}#(ct_val)) - } -} diff --git a/cheri/sail_latex/sailfnexecuteCTestSubset.tex b/cheri/sail_latex/sailfnexecuteCTestSubset.tex deleted file mode 100644 index a339dff7..00000000 --- a/cheri/sail_latex/sailfnexecuteCTestSubset.tex +++ /dev/null @@ -1,29 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCTestSubset]{CTestSubset}#(rd, cb, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cb_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(cb); - ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - ct_top = #\hyperref[zgetCapTop]{getCapTop}#(ct_val); - ct_base = #\hyperref[zgetCapBase]{getCapBase}#(ct_val); - ct_perms = #\hyperref[zgetCapPerms]{getCapPerms}#(ct_val); - cb_top = #\hyperref[zgetCapTop]{getCapTop}#(cb_val); - cb_base = #\hyperref[zgetCapBase]{getCapBase}#(cb_val); - cb_perms = #\hyperref[zgetCapPerms]{getCapPerms}#(cb_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else { - result : #\hyperref[zbits]{bits}#(1) = if (cb_val.tag != ct_val.tag) then - 0b0 - else if (ct_base < cb_base) then - 0b0 - else if (ct_top > cb_top) then - 0b0 - else if ((ct_perms & cb_perms) != ct_perms) then - 0b0 - else - 0b1; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(result); - } -} diff --git a/cheri/sail_latex/sailfnexecuteCToPtr.tex b/cheri/sail_latex/sailfnexecuteCToPtr.tex deleted file mode 100644 index f37d7ac3..00000000 --- a/cheri/sail_latex/sailfnexecuteCToPtr.tex +++ /dev/null @@ -1,27 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zCToPtr]{CToPtr}#(rd, cb, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let ct_val = #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(ct); - let cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else if #\hyperref[znot]{not}# (ct_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, ct) - else if (cb_val.tag) & (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else - { - let cbBase = #\hyperref[zgetCapBase]{getCapBase}#(cb_val) in - let cbTop = #\hyperref[zgetCapTop]{getCapTop}#(cb_val) in - let ctBase = #\hyperref[zgetCapBase]{getCapBase}#(ct_val) in - let ctTop = #\hyperref[zgetCapTop]{getCapTop}#(ct_val) in - #\hyperref[zwGPR]{wGPR}#(rd) = if (#\hyperref[znot]{not}# (cb_val.tag)) | - (cbBase < ctBase) | - (cbTop > ctTop) then - #\hyperref[zzzeros]{zeros}#() - else - #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapCursor]{getCapCursor}#(cb_val) - ctBase) - } -} diff --git a/cheri/sail_latex/sailfnexecuteCUnseal.tex b/cheri/sail_latex/sailfnexecuteCUnseal.tex deleted file mode 100644 index 48b529ef..00000000 --- a/cheri/sail_latex/sailfnexecuteCUnseal.tex +++ /dev/null @@ -1,35 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCUnseal]{CUnseal}#(cd, cs, ct)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - ct_val = #\hyperref[zreadCapReg]{readCapReg}#(ct); - ct_cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(ct_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cd)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cd) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(ct)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, ct) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if #\hyperref[znot]{not}# (ct_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, ct) - else if #\hyperref[znot]{not}# (cs_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) - else if (ct_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, ct) - else if (ct_cursor != #\hyperref[zunsigned]{unsigned}#(cs_val.otype)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, ct) - else if #\hyperref[znot]{not}# (ct_val.permit_unseal) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitUnsealViolation, ct) - else if (ct_cursor < #\hyperref[zgetCapBase]{getCapBase}#(ct_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else if (ct_cursor >= #\hyperref[zgetCapTop]{getCapTop}#(ct_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(cd, {cs_val with - sealed=false, - otype=#\hyperref[zzzeros]{zeros}#(), - global=(cs_val.global & ct_val.global) - }) -} diff --git a/cheri/sail_latex/sailfnexecuteCWriteHwr.tex b/cheri/sail_latex/sailfnexecuteCWriteHwr.tex deleted file mode 100644 index 586efb38..00000000 --- a/cheri/sail_latex/sailfnexecuteCWriteHwr.tex +++ /dev/null @@ -1,35 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCWriteHwr]{CWriteHwr}#(cb, sel)) = -{ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - let (needSup, needAccessSys) : (bool, bool) = match #\hyperref[zunsigned]{unsigned}#(sel) { - 0 => (false, false), /* DDC -- no access control */ - 1 => (false, false), /* CTLSU -- no access control */ - 8 => (false, true), /* CTLSP -- privileged TLS */ - 22 => (true, false), /* KR1C */ - 23 => (true, false), /* KR2C */ - 29 => (true, true), /* KCC */ - 30 => (true, true), /* KDC */ - 31 => (true, true), /* EPCC */ - _ => #\hyperref[zSignalException]{SignalException}#(ResI) - }; - if #\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if needAccessSys & #\hyperref[znot]{not}#(#\hyperref[zpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#()) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) - else if needSup & #\hyperref[znot]{not}#(#\hyperref[zgrantsAccess]{grantsAccess}#(#\hyperref[zgetAccessLevel]{getAccessLevel}#(), Supervisor)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) - else { - capVal = #\hyperref[zreadCapReg]{readCapReg}#(cb); - match #\hyperref[zunsigned]{unsigned}#(sel) { - 0 => DDC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 1 => CTLSU = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 8 => CTLSP = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 22 => KR1C = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 23 => KR2C = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 29 => KCC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 30 => KDC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - 31 => EPCC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(capVal), - _ => assert(false, "should be unreachable code") - }; - }; -} diff --git a/cheri/sail_latex/sailfnexecuteClearRegs.tex b/cheri/sail_latex/sailfnexecuteClearRegs.tex deleted file mode 100644 index 5283918f..00000000 --- a/cheri/sail_latex/sailfnexecuteClearRegs.tex +++ /dev/null @@ -1,21 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zClearRegs]{ClearRegs}#(regset, m)) = -{ - if ((regset == CLo) | (regset == CHi)) then - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - if (regset == CHi) then - foreach (i from 0 to 15) - let r = #\hyperref[ztozybits]{to\_bits}#(5, i+16) in - if (m[i] & #\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(r)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, r); - foreach (i from 0 to 15) - if (m[i]) then - match regset { - GPLo => #\hyperref[zwGPR]{wGPR}#(#\hyperref[ztozybits]{to\_bits}#(5, i)) = #\hyperref[zzzeros]{zeros}#(), - GPHi => #\hyperref[zwGPR]{wGPR}#(#\hyperref[ztozybits]{to\_bits}#(5, i+16)) = #\hyperref[zzzeros]{zeros}#(), - CLo => if i == 0 then - DDC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(null_cap) - else - #\hyperref[zwriteCapReg]{writeCapReg}#(#\hyperref[ztozybits]{to\_bits}#(5, i)) = null_cap, - CHi => #\hyperref[zwriteCapReg]{writeCapReg}#(#\hyperref[ztozybits]{to\_bits}#(5, i+16)) = null_cap - } -} diff --git a/cheri/sail_latex/sailfnexecuteCtwoDump.tex b/cheri/sail_latex/sailfnexecuteCtwoDump.tex deleted file mode 100644 index d4986ec2..00000000 --- a/cheri/sail_latex/sailfnexecuteCtwoDump.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCtwoDump]{C2Dump}# (rt)) = - () /* Currently a NOP */ diff --git a/cheri/sail_latex/sailfnexecuteDADD.tex b/cheri/sail_latex/sailfnexecuteDADD.tex deleted file mode 100644 index 8a3c2f76..00000000 --- a/cheri/sail_latex/sailfnexecuteDADD.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDADD]{DADD}# (rs, rt, rd)) = - { - let sum65 : #\hyperref[zbits]{bits}#(65) = #\hyperref[zsignzyextend]{sign\_extend}#(#\hyperref[zrGPR]{rGPR}#(rs)) + #\hyperref[zsignzyextend]{sign\_extend}#(#\hyperref[zrGPR]{rGPR}#(rt)) in - { - if sum65[64] != sum65[63] then - (#\hyperref[zSignalException]{SignalException}#(Ov)) - else - #\hyperref[zwGPR]{wGPR}#(rd) = sum65[63..0] - } - } diff --git a/cheri/sail_latex/sailfnexecuteDADDI.tex b/cheri/sail_latex/sailfnexecuteDADDI.tex deleted file mode 100644 index c03260b8..00000000 --- a/cheri/sail_latex/sailfnexecuteDADDI.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDADDI]{DADDI}# (rs, rt, imm)) = - { - let sum65 : #\hyperref[zbits]{bits}#(65) = #\hyperref[zsignzyextend]{sign\_extend}#(#\hyperref[zrGPR]{rGPR}#(rs)) + #\hyperref[zsignzyextend]{sign\_extend}#(imm) in - { - if (sum65[64] != sum65[63]) then - (#\hyperref[zSignalException]{SignalException}#(Ov)) - else - #\hyperref[zwGPR]{wGPR}#(rt) = sum65[63..0] - } - } diff --git a/cheri/sail_latex/sailfnexecuteDADDIU.tex b/cheri/sail_latex/sailfnexecuteDADDIU.tex deleted file mode 100644 index 028190a0..00000000 --- a/cheri/sail_latex/sailfnexecuteDADDIU.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDADDIU]{DADDIU}# (rs, rt, imm)) = - { - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zrGPR]{rGPR}#(rs) + #\hyperref[zsignzyextend]{sign\_extend}#(imm) - } diff --git a/cheri/sail_latex/sailfnexecuteDADDU.tex b/cheri/sail_latex/sailfnexecuteDADDU.tex deleted file mode 100644 index 610deeef..00000000 --- a/cheri/sail_latex/sailfnexecuteDADDU.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDADDU]{DADDU}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zrGPR]{rGPR}#(rs) + #\hyperref[zrGPR]{rGPR}#(rt) - } diff --git a/cheri/sail_latex/sailfnexecuteDDIV.tex b/cheri/sail_latex/sailfnexecuteDDIV.tex deleted file mode 100644 index 9e16d758..00000000 --- a/cheri/sail_latex/sailfnexecuteDDIV.tex +++ /dev/null @@ -1,16 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDDIV]{DDIV}#(rs, rt)) = - { - rsVal = #\hyperref[zsigned]{signed}#(#\hyperref[zrGPR]{rGPR}#(rs)); - rtVal = #\hyperref[zsigned]{signed}#(#\hyperref[zrGPR]{rGPR}#(rt)); - let (q , r) = - if (rtVal == 0) - then (undefined : #\hyperref[zbits]{bits}#(64), undefined : #\hyperref[zbits]{bits}#(64)) - else - let qi = #\hyperref[zquotzyroundzyzzero]{quot\_round\_zero}#(rsVal, rtVal) in - let ri = (rsVal - (qi * rtVal)) in - (#\hyperref[ztozybits]{to\_bits}#(64, qi), #\hyperref[ztozybits]{to\_bits}#(64, ri)) in - { - LO = q; - HI = r; - } - } diff --git a/cheri/sail_latex/sailfnexecuteDDIVU.tex b/cheri/sail_latex/sailfnexecuteDDIVU.tex deleted file mode 100644 index af83d644..00000000 --- a/cheri/sail_latex/sailfnexecuteDDIVU.tex +++ /dev/null @@ -1,16 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDDIVU]{DDIVU}#(rs, rt)) = - { - rsVal = #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rs)); - rtVal = #\hyperref[zunsigned]{unsigned}#(#\hyperref[zrGPR]{rGPR}#(rt)); - let (q, r) = - if (rtVal == 0) - then (undefined : #\hyperref[zbits]{bits}#(64), undefined : #\hyperref[zbits]{bits}#(64)) - else - let qi = #\hyperref[zquotzyroundzyzzero]{quot\_round\_zero}#(rsVal, rtVal) in - let ri = #\hyperref[zremzyroundzyzzero]{rem\_round\_zero}#(rsVal, rtVal) in - (#\hyperref[ztozybits]{to\_bits}#(64, qi), #\hyperref[ztozybits]{to\_bits}#(64, ri)) in - { - LO = q; - HI = r; - } - } diff --git a/cheri/sail_latex/sailfnexecuteDIV.tex b/cheri/sail_latex/sailfnexecuteDIV.tex deleted file mode 100644 index 8bebe43f..00000000 --- a/cheri/sail_latex/sailfnexecuteDIV.tex +++ /dev/null @@ -1,19 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDIV]{DIV}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - let (q, r) = - if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal) | (rtVal == 0x0000000000000000)) then - (undefined : #\hyperref[zbits]{bits}#(32), undefined : #\hyperref[zbits]{bits}#(32)) - else - let si = #\hyperref[zsigned]{signed}#((rsVal[31..0])) in - let ti = #\hyperref[zsigned]{signed}#((rtVal[31..0])) in - let qi = #\hyperref[zquotzyroundzyzzero]{quot\_round\_zero}#(si, ti) in - let ri = si - (ti*qi) in - (#\hyperref[ztozybits]{to\_bits}#(32, qi), #\hyperref[ztozybits]{to\_bits}#(32, ri)) - in - { - HI = #\hyperref[zsignzyextend]{sign\_extend}#(r); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(q); - } - } diff --git a/cheri/sail_latex/sailfnexecuteDIVU.tex b/cheri/sail_latex/sailfnexecuteDIVU.tex deleted file mode 100644 index a6e54b6a..00000000 --- a/cheri/sail_latex/sailfnexecuteDIVU.tex +++ /dev/null @@ -1,19 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDIVU]{DIVU}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - let (q, r) = - if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal) | rtVal == 0x0000000000000000) then - (undefined : #\hyperref[zbits]{bits}#(32), undefined : #\hyperref[zbits]{bits}#(32)) - else - let si = #\hyperref[zunsigned]{unsigned}#(rsVal[31..0]) in - let ti = #\hyperref[zunsigned]{unsigned}#(rtVal[31..0]) in - let qi = #\hyperref[zquotzyroundzyzzero]{quot\_round\_zero}#(si, ti) in - let ri = #\hyperref[zremzyroundzyzzero]{rem\_round\_zero}#(si, ti) in - (#\hyperref[ztozybits]{to\_bits}#(32, qi), #\hyperref[ztozybits]{to\_bits}#(32, ri)) - in - { - HI = #\hyperref[zsignzyextend]{sign\_extend}#(r); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(q); - } - } diff --git a/cheri/sail_latex/sailfnexecuteDMULT.tex b/cheri/sail_latex/sailfnexecuteDMULT.tex deleted file mode 100644 index 595fdc74..00000000 --- a/cheri/sail_latex/sailfnexecuteDMULT.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDMULT]{DMULT}#(rs, rt)) = - { - result = #\hyperref[zrGPR]{rGPR}#(rs) *_s #\hyperref[zrGPR]{rGPR}#(rt); - HI = (result[127..64]); - LO = (result[63..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteDMULTU.tex b/cheri/sail_latex/sailfnexecuteDMULTU.tex deleted file mode 100644 index cb23f01f..00000000 --- a/cheri/sail_latex/sailfnexecuteDMULTU.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDMULTU]{DMULTU}#(rs, rt)) = - { - result = #\hyperref[zrGPR]{rGPR}#(rs) *_u #\hyperref[zrGPR]{rGPR}#(rt); - HI = (result[127..64]); - LO = (result[63..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteDSLL.tex b/cheri/sail_latex/sailfnexecuteDSLL.tex deleted file mode 100644 index d470bb23..00000000 --- a/cheri/sail_latex/sailfnexecuteDSLL.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSLL]{DSLL}# (rt, rd, sa)) = - { - - #\hyperref[zwGPR]{wGPR}#(rd) = (#\hyperref[zrGPR]{rGPR}#(rt) << sa) - } diff --git a/cheri/sail_latex/sailfnexecuteDSLLV.tex b/cheri/sail_latex/sailfnexecuteDSLLV.tex deleted file mode 100644 index 87270292..00000000 --- a/cheri/sail_latex/sailfnexecuteDSLLV.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSLLV]{DSLLV}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = (#\hyperref[zrGPR]{rGPR}#(rt) << ((#\hyperref[zrGPR]{rGPR}#(rs))[5 .. 0])) - } diff --git a/cheri/sail_latex/sailfnexecuteDSLLthreetwo.tex b/cheri/sail_latex/sailfnexecuteDSLLthreetwo.tex deleted file mode 100644 index 0af771cf..00000000 --- a/cheri/sail_latex/sailfnexecuteDSLLthreetwo.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSLLthreetwo]{DSLL32}# (rt, rd, sa)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = (#\hyperref[zrGPR]{rGPR}#(rt) << (0b1 @ sa)) - } diff --git a/cheri/sail_latex/sailfnexecuteDSRA.tex b/cheri/sail_latex/sailfnexecuteDSRA.tex deleted file mode 100644 index 119d7e4d..00000000 --- a/cheri/sail_latex/sailfnexecuteDSRA.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSRA]{DSRA}# (rt, rd, sa)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - #\hyperref[zwGPR]{wGPR}#(rd) = temp >>_s sa - } diff --git a/cheri/sail_latex/sailfnexecuteDSRAV.tex b/cheri/sail_latex/sailfnexecuteDSRAV.tex deleted file mode 100644 index 35f4a18c..00000000 --- a/cheri/sail_latex/sailfnexecuteDSRAV.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSRAV]{DSRAV}# (rs, rt, rd)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - sa = #\hyperref[zrGPR]{rGPR}#(rs)[5..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = temp >>_s sa - } diff --git a/cheri/sail_latex/sailfnexecuteDSRAthreetwo.tex b/cheri/sail_latex/sailfnexecuteDSRAthreetwo.tex deleted file mode 100644 index 9a0380a5..00000000 --- a/cheri/sail_latex/sailfnexecuteDSRAthreetwo.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSRAthreetwo]{DSRA32}# (rt, rd, sa)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - sa32 = 0b1 @ sa; /* sa+32 */ - #\hyperref[zwGPR]{wGPR}#(rd) = temp >>_s sa32 - } diff --git a/cheri/sail_latex/sailfnexecuteDSRL.tex b/cheri/sail_latex/sailfnexecuteDSRL.tex deleted file mode 100644 index bebaebba..00000000 --- a/cheri/sail_latex/sailfnexecuteDSRL.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSRL]{DSRL}# (rt, rd, sa)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - #\hyperref[zwGPR]{wGPR}#(rd) = temp >> sa; - } diff --git a/cheri/sail_latex/sailfnexecuteDSRLV.tex b/cheri/sail_latex/sailfnexecuteDSRLV.tex deleted file mode 100644 index d0dc368c..00000000 --- a/cheri/sail_latex/sailfnexecuteDSRLV.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSRLV]{DSRLV}# (rs, rt, rd)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - sa = #\hyperref[zrGPR]{rGPR}#(rs)[5..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = temp >> sa; - } diff --git a/cheri/sail_latex/sailfnexecuteDSRLthreetwo.tex b/cheri/sail_latex/sailfnexecuteDSRLthreetwo.tex deleted file mode 100644 index 155fe058..00000000 --- a/cheri/sail_latex/sailfnexecuteDSRLthreetwo.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSRLthreetwo]{DSRL32}# (rt, rd, sa)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - sa32 = 0b1 @ sa; /* sa+32 */ - #\hyperref[zwGPR]{wGPR}#(rd) = temp >> sa32; - } diff --git a/cheri/sail_latex/sailfnexecuteDSUB.tex b/cheri/sail_latex/sailfnexecuteDSUB.tex deleted file mode 100644 index b4021172..00000000 --- a/cheri/sail_latex/sailfnexecuteDSUB.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSUB]{DSUB}# (rs, rt, rd)) = - { - let temp65 : #\hyperref[zbits]{bits}#(65) = #\hyperref[zsignzyextend]{sign\_extend}#(#\hyperref[zrGPR]{rGPR}#(rs)) - #\hyperref[zsignzyextend]{sign\_extend}#(#\hyperref[zrGPR]{rGPR}#(rt)) in - { - if temp65[64] != temp65[63] then - (#\hyperref[zSignalException]{SignalException}#(Ov)) - else - #\hyperref[zwGPR]{wGPR}#(rd) = temp65[63..0] - } - } diff --git a/cheri/sail_latex/sailfnexecuteDSUBU.tex b/cheri/sail_latex/sailfnexecuteDSUBU.tex deleted file mode 100644 index 1f0f28ec..00000000 --- a/cheri/sail_latex/sailfnexecuteDSUBU.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zDSUBU]{DSUBU}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zrGPR]{rGPR}#(rs) - #\hyperref[zrGPR]{rGPR}#(rt) - } diff --git a/cheri/sail_latex/sailfnexecuteERET.tex b/cheri/sail_latex/sailfnexecuteERET.tex deleted file mode 100644 index 1517ff7d..00000000 --- a/cheri/sail_latex/sailfnexecuteERET.tex +++ /dev/null @@ -1,16 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zERET]{ERET}#()) = - { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - #\hyperref[zERETHook]{ERETHook}#(); - CP0LLBit = 0b0; - if (CP0Status.#\hyperref[zERL]{ERL}#() == bitone) then - { - nextPC = CP0ErrorEPC; - CP0Status->#\hyperref[zERL]{ERL}#() = 0b0; - } - else - { - nextPC = CP0EPC; - CP0Status->#\hyperref[zEXL]{EXL}#() = 0b0; - } - } diff --git a/cheri/sail_latex/sailfnexecuteHCF.tex b/cheri/sail_latex/sailfnexecuteHCF.tex deleted file mode 100644 index 29eef4b5..00000000 --- a/cheri/sail_latex/sailfnexecuteHCF.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zHCF]{HCF}#()) = - () /* halt instruction actually executed by interpreter framework */ diff --git a/cheri/sail_latex/sailfnexecuteJ.tex b/cheri/sail_latex/sailfnexecuteJ.tex deleted file mode 100644 index b671d406..00000000 --- a/cheri/sail_latex/sailfnexecuteJ.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zJ]{J}#(offset)) = - { - #\hyperref[zexecutezybranch]{execute\_branch}#((PC + 4)[63..28] @ offset @ 0b00); - } diff --git a/cheri/sail_latex/sailfnexecuteJAL.tex b/cheri/sail_latex/sailfnexecuteJAL.tex deleted file mode 100644 index 3aa4dbf4..00000000 --- a/cheri/sail_latex/sailfnexecuteJAL.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zJAL]{JAL}#(offset)) = - { - #\hyperref[zexecutezybranch]{execute\_branch}#((PC + 4)[63..28] @ offset @ 0b00); - #\hyperref[zwGPR]{wGPR}#(0b11111) = PC + 8; - } diff --git a/cheri/sail_latex/sailfnexecuteJALR.tex b/cheri/sail_latex/sailfnexecuteJALR.tex deleted file mode 100644 index 41415ba8..00000000 --- a/cheri/sail_latex/sailfnexecuteJALR.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zJALR]{JALR}#(rs, rd)) = - { - #\hyperref[zexecutezybranch]{execute\_branch}#(#\hyperref[zrGPR]{rGPR}#(rs)); - #\hyperref[zwGPR]{wGPR}#(rd) = PC + 8; - } diff --git a/cheri/sail_latex/sailfnexecuteJR.tex b/cheri/sail_latex/sailfnexecuteJR.tex deleted file mode 100644 index ab19bbfb..00000000 --- a/cheri/sail_latex/sailfnexecuteJR.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zJR]{JR}#(rs)) = - { - #\hyperref[zexecutezybranch]{execute\_branch}#(#\hyperref[zrGPR]{rGPR}#(rs)); - } diff --git a/cheri/sail_latex/sailfnexecuteLDL.tex b/cheri/sail_latex/sailfnexecuteLDL.tex deleted file mode 100644 index c7df3f65..00000000 --- a/cheri/sail_latex/sailfnexecuteLDL.tex +++ /dev/null @@ -1,20 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zLDL]{LDL}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), LoadData, DL); - let pAddr = #\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, LoadData) in - { - mem_val = #\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr[63..3] @ 0b000, 8); /* read double of interest */ - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - #\hyperref[zwGPR]{wGPR}#(rt) = match vAddr[2..0] - { - 0b000 => mem_val, - 0b001 => mem_val[55..0] @ reg_val[7..0], - 0b010 => mem_val[47..0] @ reg_val[15..0], - 0b011 => mem_val[39..0] @ reg_val[23..0], - 0b100 => mem_val[31..0] @ reg_val[31..0], - 0b101 => mem_val[23..0] @ reg_val[39..0], - 0b110 => mem_val[15..0] @ reg_val[47..0], - 0b111 => mem_val[07..0] @ reg_val[55..0] - }; - } - } diff --git a/cheri/sail_latex/sailfnexecuteLDR.tex b/cheri/sail_latex/sailfnexecuteLDR.tex deleted file mode 100644 index a66114b2..00000000 --- a/cheri/sail_latex/sailfnexecuteLDR.tex +++ /dev/null @@ -1,20 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zLDR]{LDR}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), LoadData, DR); - let pAddr = #\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, LoadData) in - { - mem_val = #\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr[63..3] @ 0b000, 8); /* read double of interest */ - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - #\hyperref[zwGPR]{wGPR}#(rt) = match vAddr[2..0] - { - 0b000 => reg_val[63..08] @ mem_val[63..56], - 0b001 => reg_val[63..16] @ mem_val[63..48], - 0b010 => reg_val[63..24] @ mem_val[63..40], - 0b011 => reg_val[63..32] @ mem_val[63..32], - 0b100 => reg_val[63..40] @ mem_val[63..24], - 0b101 => reg_val[63..48] @ mem_val[63..16], - 0b110 => reg_val[63..56] @ mem_val[63..08], - 0b111 => mem_val - }; - } - } diff --git a/cheri/sail_latex/sailfnexecuteLUI.tex b/cheri/sail_latex/sailfnexecuteLUI.tex deleted file mode 100644 index 9c3f8089..00000000 --- a/cheri/sail_latex/sailfnexecuteLUI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zLUI]{LUI}# (rt, imm)) = - { - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zsignzyextend]{sign\_extend}#(imm @ 0x0000) - } diff --git a/cheri/sail_latex/sailfnexecuteLWL.tex b/cheri/sail_latex/sailfnexecuteLWL.tex deleted file mode 100644 index 46fd760d..00000000 --- a/cheri/sail_latex/sailfnexecuteLWL.tex +++ /dev/null @@ -1,17 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zLWL]{LWL}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), LoadData, WL); - let pAddr = (#\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, LoadData)) in - { - mem_val = #\hyperref[zMEMrzywrapper]{MEMr\_wrapper}# (pAddr[63..2] @ 0b00, 4); /* read word of interest */ - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - result : #\hyperref[zbits]{bits}#(32) = match vAddr[1..0] - { - 0b00 => mem_val, - 0b01 => mem_val[23..0] @ reg_val[07..0], - 0b10 => mem_val[15..0] @ reg_val[15..0], - 0b11 => mem_val[07..0] @ reg_val[23..0] - }; - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zsignzyextend]{sign\_extend}#(result); - } - } diff --git a/cheri/sail_latex/sailfnexecuteLWR.tex b/cheri/sail_latex/sailfnexecuteLWR.tex deleted file mode 100644 index c72d81e0..00000000 --- a/cheri/sail_latex/sailfnexecuteLWR.tex +++ /dev/null @@ -1,17 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zLWR]{LWR}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), LoadData, WR); - let pAddr = (#\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, LoadData)) in - { - mem_val = #\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr[63..2] @ 0b00, 4); /* read word of interest */ - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - result : #\hyperref[zbits]{bits}#(32) = match vAddr[1..0] - { - 0b00 => reg_val[31..8] @ mem_val[31..24], - 0b01 => reg_val[31..16] @ mem_val[31..16], - 0b10 => reg_val[31..24] @ mem_val[31..8], - 0b11 => mem_val - }; - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zsignzyextend]{sign\_extend}#(result) - } - } diff --git a/cheri/sail_latex/sailfnexecuteLoad.tex b/cheri/sail_latex/sailfnexecuteLoad.tex deleted file mode 100644 index 2db4a73b..00000000 --- a/cheri/sail_latex/sailfnexecuteLoad.tex +++ /dev/null @@ -1,30 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zLoad]{Load}#(width, sign, linked, base, rt, offset)) = - { - vAddr : #\hyperref[zbits]{bits}#(64) = #\hyperref[zaddrWrapper]{addrWrapper}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), LoadData, width); - if ~ (#\hyperref[zisAddressAligned]{isAddressAligned}#(vAddr, width)) then - (#\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr)) /* unaligned access */ - else - let pAddr = (#\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, LoadData)) in - { - memResult : #\hyperref[zbits]{bits}#(64) = if (linked) then - { - CP0LLBit = 0b1; - CP0LLAddr = pAddr; - match width { - W => #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzyreservezywrapper]{MEMr\_reserve\_wrapper}#(pAddr, 4), sign), - D => #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzyreservezywrapper]{MEMr\_reserve\_wrapper}#(pAddr, 8), sign), - _ => throw(#\hyperref[zErrorzyinternalzyerror]{Error\_internal\_error}#()) /* there is no llbc or llhc */ - } - } - else - { - match width { - B => #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr, 1), sign), - H => #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr, 2), sign), - W => #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr, 4), sign), - D => #\hyperref[zextendLoad]{extendLoad}#(#\hyperref[zMEMrzywrapper]{MEMr\_wrapper}#(pAddr, 8), sign) - } - }; - #\hyperref[zwGPR]{wGPR}#(rt) = memResult - } - } diff --git a/cheri/sail_latex/sailfnexecuteMADD.tex b/cheri/sail_latex/sailfnexecuteMADD.tex deleted file mode 100644 index 77d54494..00000000 --- a/cheri/sail_latex/sailfnexecuteMADD.tex +++ /dev/null @@ -1,12 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMADD]{MADD}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - mul_result : #\hyperref[zbits]{bits}#(64) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - rsVal[31..0] *_s rtVal[31..0]; - result = mul_result + (HI[31..0] @ LO[31..0]); - HI = #\hyperref[zsignzyextend]{sign\_extend}#(result[63..32]); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteMADDU.tex b/cheri/sail_latex/sailfnexecuteMADDU.tex deleted file mode 100644 index 67f95457..00000000 --- a/cheri/sail_latex/sailfnexecuteMADDU.tex +++ /dev/null @@ -1,12 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMADDU]{MADDU}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - mul_result : #\hyperref[zbits]{bits}#(64) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - rsVal[31..0] *_u rtVal[31..0]; - result = mul_result + (HI[31..0] @ LO[31..0]); - HI = #\hyperref[zsignzyextend]{sign\_extend}#(result[63..32]); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteMFCzero.tex b/cheri/sail_latex/sailfnexecuteMFCzero.tex deleted file mode 100644 index c15ef9f8..00000000 --- a/cheri/sail_latex/sailfnexecuteMFCzero.tex +++ /dev/null @@ -1,70 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMFCzero]{MFC0}#(rt, rd, sel, double)) = { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - let result : #\hyperref[zbits]{bits}#(64) = match (rd, sel) - { - (0b00000,0b000) => let idx : #\hyperref[zbits]{bits}#(31) = #\hyperref[zzzerozyextend]{zero\_extend}#(TLBIndex) in - (0x00000000 @ TLBProbe @ idx), /* 0, TLB Index */ - (0b00001,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(TLBRandom), /* 1, TLB Random */ - (0b00010,0b000) => TLBEntryLo0.#\hyperref[zbits]{bits}#(), /* 2, TLB EntryLo0 */ - (0b00011,0b000) => TLBEntryLo1.#\hyperref[zbits]{bits}#(), /* 3, TLB EntryLo1 */ - (0b00100,0b000) => TLBContext.#\hyperref[zbits]{bits}#(), /* 4, TLB Context */ - (0b00100,0b010) => CP0UserLocal, - (0b00101,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(TLBPageMask @ 0x000), /* 5, TLB PageMask */ - (0b00110,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(TLBWired), /* 6, TLB Wired */ - (0b00111,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(CP0HWREna), /* 7, HWREna */ - (0b01000,0b000) => CP0BadVAddr, /* 8, BadVAddr reg */ - (0b01000,0b001) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b0), /* 8, BadInstr reg XXX TODO */ - (0b01001,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(CP0Count), /* 9, Count reg */ - (0b01010,0b000) => TLBEntryHi.#\hyperref[zbits]{bits}#(),/* 10, TLB EntryHi */ - (0b01011,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(CP0Compare), /* 11, Compare reg */ - (0b01100,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(CP0Status.#\hyperref[zbits]{bits}#()), /* 12, Status reg */ - (0b01101,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(CP0Cause.#\hyperref[zbits]{bits}#()), /* 13, Cause reg */ - (0b01110,0b000) => CP0EPC, /* 14, EPC */ - (0b01111,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(0x00000400), /* 15, sel 0: PrID processor ID */ - (0b01111,0b110) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b0), /* 15, sel 6: CHERI core ID */ - (0b01111,0b111) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b0), /* 15, sel 7: CHERI thread ID */ - (0b10000,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b1 /* M */ /* 16, sel 0: Config0 */ - @ 0b000000000000000 /* Impl */ - @ 0b1 /* BE */ - @ 0b10 /* AT */ - @ 0b000 /* AR */ - @ 0b001 /* MT standard TLB */ - @ 0b0000 /* zero */ - @ CP0ConfigK0), - (0b10000,0b001) => #\hyperref[zzzerozyextend]{zero\_extend}#( /* 16, sel 1: Config1 */ - 0b1 /* M */ - @ TLBIndexMax /* MMU size-1 */ - @ 0b000 /* IS icache sets */ - @ 0b000 /* IL icache lines */ - @ 0b000 /* IA icache assoc. */ - @ 0b000 /* DS dcache sets */ - @ 0b000 /* DL dcache lines */ - @ 0b000 /* DA dcache assoc. */ - @ #\hyperref[zboolzytozybits]{bool\_to\_bits}#(have_cp2) /* C2 CP2 presence */ - @ 0b0 /* MD MDMX implemented */ - @ 0b0 /* PC performance counters */ - @ 0b0 /* WR watch registers */ - @ 0b0 /* CA 16e code compression */ - @ 0b0 /* EP EJTAG */ - @ 0b0), /* FP FPU present */ - (0b10000,0b010) => #\hyperref[zzzerozyextend]{zero\_extend}#( /* 16, sel 2: Config2 */ - 0b1 /* M */ - @ 0b000 /* TU L3 control */ - @ 0b0000 /* TS L3 sets */ - @ 0b0000 /* TL L3 lines */ - @ 0b0000 /* TA L3 assoc. */ - @ 0b0000 /* SU L2 control */ - @ 0b0000 /* SS L2 sets */ - @ 0b0000 /* SL L2 lines */ - @ 0b0000), /* SA L2 assoc. */ - (0b10000,0b011) => 0x0000000000002000, /* 16, sel 3: Config3 zero except for bit 13 == ulri */ - (0b10000,0b101) => 0x0000000000000000, /* 16, sel 5: Config5 beri specific -- no extended TLB */ - (0b10001,0b000) => CP0LLAddr, /* 17, sel 0: LLAddr */ - (0b10010,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b0), /* 18, WatchLo */ - (0b10011,0b000) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b0), /* 19, WatchHi */ - (0b10100,0b000) => TLBXContext.#\hyperref[zbits]{bits}#(), /* 20, XContext */ - (0b11110,0b000) => CP0ErrorEPC, /* 30, ErrorEPC */ - _ => (#\hyperref[zSignalException]{SignalException}#(ResI)) - } in - #\hyperref[zwGPR]{wGPR}#(rt) = if (double) then result else #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]) -} diff --git a/cheri/sail_latex/sailfnexecuteMFHI.tex b/cheri/sail_latex/sailfnexecuteMFHI.tex deleted file mode 100644 index ff0aadba..00000000 --- a/cheri/sail_latex/sailfnexecuteMFHI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMFHI]{MFHI}#(rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = HI - } diff --git a/cheri/sail_latex/sailfnexecuteMFLO.tex b/cheri/sail_latex/sailfnexecuteMFLO.tex deleted file mode 100644 index 69ad3a35..00000000 --- a/cheri/sail_latex/sailfnexecuteMFLO.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMFLO]{MFLO}#(rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = LO - } diff --git a/cheri/sail_latex/sailfnexecuteMOVN.tex b/cheri/sail_latex/sailfnexecuteMOVN.tex deleted file mode 100644 index 9802ef3d..00000000 --- a/cheri/sail_latex/sailfnexecuteMOVN.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMOVN]{MOVN}#(rs, rt, rd)) = - { - if (#\hyperref[zrGPR]{rGPR}#(rt) != 0x0000000000000000) then - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zrGPR]{rGPR}#(rs) - } diff --git a/cheri/sail_latex/sailfnexecuteMOVZ.tex b/cheri/sail_latex/sailfnexecuteMOVZ.tex deleted file mode 100644 index 0c09e058..00000000 --- a/cheri/sail_latex/sailfnexecuteMOVZ.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMOVZ]{MOVZ}#(rs, rt, rd)) = - { - if (#\hyperref[zrGPR]{rGPR}#(rt) == 0x0000000000000000) then - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zrGPR]{rGPR}#(rs) - } diff --git a/cheri/sail_latex/sailfnexecuteMSUB.tex b/cheri/sail_latex/sailfnexecuteMSUB.tex deleted file mode 100644 index 7d796f26..00000000 --- a/cheri/sail_latex/sailfnexecuteMSUB.tex +++ /dev/null @@ -1,12 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMSUB]{MSUB}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - mul_result : #\hyperref[zbits]{bits}#(64) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - rsVal[31..0] *_s rtVal[31..0]; - result = (HI[31..0] @ LO[31..0]) - mul_result; - HI = #\hyperref[zsignzyextend]{sign\_extend}#(result[63..32]); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteMSUBU.tex b/cheri/sail_latex/sailfnexecuteMSUBU.tex deleted file mode 100644 index f501e5c5..00000000 --- a/cheri/sail_latex/sailfnexecuteMSUBU.tex +++ /dev/null @@ -1,12 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMSUBU]{MSUBU}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - mul_result : #\hyperref[zbits]{bits}#(64) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - rsVal[31..0] *_u rtVal[31..0]; - result = (HI[31..0] @ LO[31..0]) - mul_result; - HI = #\hyperref[zsignzyextend]{sign\_extend}#(result[63..32]); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteMTCzero.tex b/cheri/sail_latex/sailfnexecuteMTCzero.tex deleted file mode 100644 index 61c6703e..00000000 --- a/cheri/sail_latex/sailfnexecuteMTCzero.tex +++ /dev/null @@ -1,52 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMTCzero]{MTC0}#(rt, rd, sel, double)) = { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - let reg_val = #\hyperref[zrGPR]{rGPR}#(rt) in - match (rd, sel) - { - (0b00000,0b000) => TLBIndex = #\hyperref[zmask]{mask}#(reg_val), /* NB no write to TLBProbe */ - (0b00001,0b000) => (), /* TLBRandom is read only */ - (0b00010,0b000) => TLBEntryLo0->#\hyperref[zbits]{bits}#() = reg_val, - (0b00011,0b000) => TLBEntryLo1->#\hyperref[zbits]{bits}#() = reg_val, - (0b00100,0b000) => TLBContext->#\hyperref[zPTEBase]{PTEBase}#() = reg_val[63..23], - (0b00100,0b010) => CP0UserLocal = reg_val, - (0b00101,0b000) => TLBPageMask = reg_val[28..13], - (0b00110,0b000) => { - TLBWired = #\hyperref[zmask]{mask}#(reg_val); - TLBRandom = TLBIndexMax; - }, - (0b00111,0b000) => CP0HWREna = (reg_val[31..29] @ 0b0000000000000000000000000 @ reg_val[3..0]), - (0b01000,0b000) => (), /* BadVAddr read only */ - (0b01001,0b000) => CP0Count = reg_val[31..0], - (0b01010,0b000) => { - TLBEntryHi->#\hyperref[zR]{R}#() = reg_val[63..62]; - TLBEntryHi->#\hyperref[zVPNtwo]{VPN2}#() = reg_val[39..13]; - TLBEntryHi->#\hyperref[zASID]{ASID}#() = reg_val[7..0]; - }, - (0b01011,0b000) => { /* 11, sel 0: Compare reg */ - CP0Compare = reg_val[31..0]; - CP0Cause->#\hyperref[zIP]{IP}#() = CP0Cause.#\hyperref[zIP]{IP}#() & 0x7f; /* clear IP7 */ - }, - (0b01100,0b000) => { /* 12 Status */ - CP0Status->#\hyperref[zCU]{CU}#() = reg_val[31..28]; - CP0Status->#\hyperref[zBEV]{BEV}#() = reg_val[22]; - CP0Status->#\hyperref[zIM]{IM}#() = reg_val[15..8]; - CP0Status->#\hyperref[zKX]{KX}#() = reg_val[7]; - CP0Status->#\hyperref[zSX]{SX}#() = reg_val[6]; - CP0Status->#\hyperref[zUX]{UX}#() = reg_val[5]; - CP0Status->#\hyperref[zKSU]{KSU}#() = reg_val[4..3]; - CP0Status->#\hyperref[zERL]{ERL}#() = reg_val[2]; - CP0Status->#\hyperref[zEXL]{EXL}#() = reg_val[1]; - CP0Status->#\hyperref[zIE]{IE}#() = reg_val[0]; - }, - (0b01101,0b000) => { /* 13 Cause */ - CP0Cause->#\hyperref[zIV]{IV}#() = reg_val[23]; /* TODO special interrupt vector not implemeneted */ - let ip = CP0Cause.#\hyperref[zIP]{IP}#() in - CP0Cause->#\hyperref[zIP]{IP}#() = ((ip[7..2]) @ (reg_val[9..8])); - }, - (0b01110,0b000) => CP0EPC = reg_val, /* 14, EPC */ - (0b10000,0b000) => CP0ConfigK0 = reg_val[2..0], /* K0 cache config 16: Config0 */ - (0b10100,0b000) => TLBXContext->#\hyperref[zXPTEBase]{XPTEBase}#() = reg_val[63..33], - (0b11110,0b000) => CP0ErrorEPC = reg_val, /* 30, ErrorEPC */ - _ => (#\hyperref[zSignalException]{SignalException}#(ResI)) - } -} diff --git a/cheri/sail_latex/sailfnexecuteMTHI.tex b/cheri/sail_latex/sailfnexecuteMTHI.tex deleted file mode 100644 index e221477e..00000000 --- a/cheri/sail_latex/sailfnexecuteMTHI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMTHI]{MTHI}#(rs)) = - { - HI = #\hyperref[zrGPR]{rGPR}#(rs) - } diff --git a/cheri/sail_latex/sailfnexecuteMTLO.tex b/cheri/sail_latex/sailfnexecuteMTLO.tex deleted file mode 100644 index af9f9aae..00000000 --- a/cheri/sail_latex/sailfnexecuteMTLO.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMTLO]{MTLO}#(rs)) = - { - LO = #\hyperref[zrGPR]{rGPR}#(rs) - } diff --git a/cheri/sail_latex/sailfnexecuteMUL.tex b/cheri/sail_latex/sailfnexecuteMUL.tex deleted file mode 100644 index 385f4433..00000000 --- a/cheri/sail_latex/sailfnexecuteMUL.tex +++ /dev/null @@ -1,15 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMUL]{MUL}#(rs, rt, rd)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - result : #\hyperref[zbits]{bits}#(64) = #\hyperref[zsignzyextend]{sign\_extend}#((rsVal[31..0]) *#\hyperref[zzys]{\_s}# (rtVal[31..0])); - #\hyperref[zwGPR]{wGPR}#(rd) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - /* HI and LO are technically undefined after MUL, but this causes problems with tests and - (potentially) context switch so just leave them alone - HI = undefined; - LO = undefined; - */ - } diff --git a/cheri/sail_latex/sailfnexecuteMULT.tex b/cheri/sail_latex/sailfnexecuteMULT.tex deleted file mode 100644 index b8de983f..00000000 --- a/cheri/sail_latex/sailfnexecuteMULT.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMULT]{MULT}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - result : #\hyperref[zbits]{bits}#(64) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - (rsVal[31..0]) *#\hyperref[zzys]{\_s}# (rtVal[31..0]); - HI = #\hyperref[zsignzyextend]{sign\_extend}#(result[63..32]); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteMULTU.tex b/cheri/sail_latex/sailfnexecuteMULTU.tex deleted file mode 100644 index 0095e387..00000000 --- a/cheri/sail_latex/sailfnexecuteMULTU.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zMULTU]{MULTU}#(rs, rt)) = - { - rsVal = #\hyperref[zrGPR]{rGPR}#(rs); - rtVal = #\hyperref[zrGPR]{rGPR}#(rt); - result : #\hyperref[zbits]{bits}#(64) = if (#\hyperref[zNotWordVal]{NotWordVal}#(rsVal) | #\hyperref[zNotWordVal]{NotWordVal}#(rtVal)) then - undefined - else - (rsVal[31..0]) *#\hyperref[zzyu]{\_u}# (rtVal[31..0]); - HI = #\hyperref[zsignzyextend]{sign\_extend}#(result[63..32]); - LO = #\hyperref[zsignzyextend]{sign\_extend}#(result[31..0]); - } diff --git a/cheri/sail_latex/sailfnexecuteNOR.tex b/cheri/sail_latex/sailfnexecuteNOR.tex deleted file mode 100644 index a1cfa14b..00000000 --- a/cheri/sail_latex/sailfnexecuteNOR.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zNOR]{NOR}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = ~(#\hyperref[zrGPR]{rGPR}#(rs) | #\hyperref[zrGPR]{rGPR}#(rt)) - } diff --git a/cheri/sail_latex/sailfnexecuteOR.tex b/cheri/sail_latex/sailfnexecuteOR.tex deleted file mode 100644 index 01c0fcf6..00000000 --- a/cheri/sail_latex/sailfnexecuteOR.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zOR]{OR}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = (#\hyperref[zrGPR]{rGPR}#(rs) | #\hyperref[zrGPR]{rGPR}#(rt)) - } diff --git a/cheri/sail_latex/sailfnexecuteORI.tex b/cheri/sail_latex/sailfnexecuteORI.tex deleted file mode 100644 index 0a3f9d15..00000000 --- a/cheri/sail_latex/sailfnexecuteORI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zORI]{ORI}# (rs, rt, imm)) = - { - #\hyperref[zwGPR]{wGPR}#(rt) = (#\hyperref[zrGPR]{rGPR}#(rs) | #\hyperref[zzzerozyextend]{zero\_extend}#(imm)) - } diff --git a/cheri/sail_latex/sailfnexecuteRDHWR.tex b/cheri/sail_latex/sailfnexecuteRDHWR.tex deleted file mode 100644 index e64fff25..00000000 --- a/cheri/sail_latex/sailfnexecuteRDHWR.tex +++ /dev/null @@ -1,18 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zRDHWR]{RDHWR}#(rt, rd)) = { - let accessLevel = #\hyperref[zgetAccessLevel]{getAccessLevel}#() in - let haveAccessLevel : bool = accessLevel == Kernel in - let haveCU0 : bool = bitone == (CP0Status.#\hyperref[zCU]{CU}#()[0]) in - let rdi as atom(_) = #\hyperref[zunsigned]{unsigned}#(rd) in - let haveHWREna : bool = bitone == (CP0HWREna[rdi]) in - if ~(haveAccessLevel | haveCU0 | haveHWREna) then - (#\hyperref[zSignalException]{SignalException}#(ResI)); - let temp : #\hyperref[zbits]{bits}#(64) = match rd { - 0b00000 => #\hyperref[zzzerozyextend]{zero\_extend}#([bitzero]), /* CPUNum */ - 0b00001 => #\hyperref[zzzerozyextend]{zero\_extend}#([bitzero]), /* SYNCI_step */ - 0b00010 => #\hyperref[zzzerozyextend]{zero\_extend}#(CP0Count), /* Count */ - 0b00011 => #\hyperref[zzzerozyextend]{zero\_extend}#([bitone]), /* Count resolution */ - 0b11101 => CP0UserLocal, /* User local register */ - _ => (#\hyperref[zSignalException]{SignalException}#(ResI)) - } in - #\hyperref[zwGPR]{wGPR}#(rt) = temp; -} diff --git a/cheri/sail_latex/sailfnexecuteRI.tex b/cheri/sail_latex/sailfnexecuteRI.tex deleted file mode 100644 index 6206c8e3..00000000 --- a/cheri/sail_latex/sailfnexecuteRI.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zRI]{RI}#()) = - #\hyperref[zSignalException]{SignalException}# (ResI) diff --git a/cheri/sail_latex/sailfnexecuteSDL.tex b/cheri/sail_latex/sailfnexecuteSDL.tex deleted file mode 100644 index 0e8e78b4..00000000 --- a/cheri/sail_latex/sailfnexecuteSDL.tex +++ /dev/null @@ -1,19 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zSDL]{SDL}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), StoreData, DL); - let pAddr = #\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, StoreData) in - { - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - match vAddr[2..0] - { - 0b000 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 8) = reg_val[63..00]), - 0b001 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 7) = reg_val[63..08]), - 0b010 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 6) = reg_val[63..16]), - 0b011 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 5) = reg_val[63..24]), - 0b100 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 4) = reg_val[63..32]), - 0b101 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 3) = reg_val[63..40]), - 0b110 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 2) = reg_val[63..48]), - 0b111 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 1) = reg_val[63..56]) - } - } - } diff --git a/cheri/sail_latex/sailfnexecuteSDR.tex b/cheri/sail_latex/sailfnexecuteSDR.tex deleted file mode 100644 index 98f7a8a7..00000000 --- a/cheri/sail_latex/sailfnexecuteSDR.tex +++ /dev/null @@ -1,20 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zSDR]{SDR}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), StoreData, DR); - let pAddr = #\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, StoreData) in - { - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - wordAddr = pAddr[63..3] @ 0b000; - match vAddr[2..0] - { - 0b000 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 1) = reg_val[07..0]), - 0b001 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 2) = reg_val[15..0]), - 0b010 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 3) = reg_val[23..0]), - 0b011 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 4) = reg_val[31..0]), - 0b100 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 5) = reg_val[39..0]), - 0b101 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 6) = reg_val[47..0]), - 0b110 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 7) = reg_val[55..0]), - 0b111 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 8) = reg_val[63..0]) - } - } - } diff --git a/cheri/sail_latex/sailfnexecuteSLL.tex b/cheri/sail_latex/sailfnexecuteSLL.tex deleted file mode 100644 index 31f5399a..00000000 --- a/cheri/sail_latex/sailfnexecuteSLL.tex +++ /dev/null @@ -1,5 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSLL]{SLL}#(rt, rd, sa)) = - { - rt32 = #\hyperref[zrGPR]{rGPR}#(rt)[31..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(rt32 << sa); - } diff --git a/cheri/sail_latex/sailfnexecuteSLLV.tex b/cheri/sail_latex/sailfnexecuteSLLV.tex deleted file mode 100644 index 41598e6d..00000000 --- a/cheri/sail_latex/sailfnexecuteSLLV.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSLLV]{SLLV}#(rs, rt, rd)) = - { - sa = #\hyperref[zrGPR]{rGPR}#(rs)[4..0]; - rt32 = #\hyperref[zrGPR]{rGPR}#(rt)[31..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(rt32 << sa) - } diff --git a/cheri/sail_latex/sailfnexecuteSLT.tex b/cheri/sail_latex/sailfnexecuteSLT.tex deleted file mode 100644 index 8e625945..00000000 --- a/cheri/sail_latex/sailfnexecuteSLT.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSLT]{SLT}#(rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(if (#\hyperref[zrGPR]{rGPR}#(rs) <_s #\hyperref[zrGPR]{rGPR}#(rt)) then 0b1 else 0b0) - } diff --git a/cheri/sail_latex/sailfnexecuteSLTI.tex b/cheri/sail_latex/sailfnexecuteSLTI.tex deleted file mode 100644 index 32582b6f..00000000 --- a/cheri/sail_latex/sailfnexecuteSLTI.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSLTI]{SLTI}#(rs, rt, imm)) = - { - let imm_val = #\hyperref[zsigned]{signed}#(imm) in - let rs_val = #\hyperref[zsigned]{signed}#(#\hyperref[zrGPR]{rGPR}#(rs)) in - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zzzerozyextend]{zero\_extend}#(if (rs_val < imm_val) then 0b1 else 0b0) - } diff --git a/cheri/sail_latex/sailfnexecuteSLTIU.tex b/cheri/sail_latex/sailfnexecuteSLTIU.tex deleted file mode 100644 index e232aa07..00000000 --- a/cheri/sail_latex/sailfnexecuteSLTIU.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSLTIU]{SLTIU}#(rs, rt, imm)) = - { - let rs_val = #\hyperref[zrGPR]{rGPR}#(rs) in - let immext : #\hyperref[zbits]{bits}#(64) = #\hyperref[zsignzyextend]{sign\_extend}#(imm) in /* NB defined to sign extend here even though comparison is unsigned! */ - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zzzerozyextend]{zero\_extend}#(if (rs_val <_u immext) then 0b1 else 0b0) - } diff --git a/cheri/sail_latex/sailfnexecuteSLTU.tex b/cheri/sail_latex/sailfnexecuteSLTU.tex deleted file mode 100644 index 38b71b30..00000000 --- a/cheri/sail_latex/sailfnexecuteSLTU.tex +++ /dev/null @@ -1,6 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSLTU]{SLTU}#(rs, rt, rd)) = - { - let rs_val = #\hyperref[zrGPR]{rGPR}#(rs) in - let rt_val = #\hyperref[zrGPR]{rGPR}#(rt) in - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zzzerozyextend]{zero\_extend}#(if (rs_val <_u rt_val) then 0b1 else 0b0) - } diff --git a/cheri/sail_latex/sailfnexecuteSRA.tex b/cheri/sail_latex/sailfnexecuteSRA.tex deleted file mode 100644 index 3d881120..00000000 --- a/cheri/sail_latex/sailfnexecuteSRA.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSRA]{SRA}#(rt, rd, sa)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zNotWordVal]{NotWordVal}#(temp)) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined - else { - rt32 = temp[31..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(rt32 >>_s sa); - } - } diff --git a/cheri/sail_latex/sailfnexecuteSRAV.tex b/cheri/sail_latex/sailfnexecuteSRAV.tex deleted file mode 100644 index 54d3bd1e..00000000 --- a/cheri/sail_latex/sailfnexecuteSRAV.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSRAV]{SRAV}#(rs, rt, rd)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - sa = #\hyperref[zrGPR]{rGPR}#(rs)[4..0]; - if (#\hyperref[zNotWordVal]{NotWordVal}#(temp)) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined - else { - rt32 = temp[31..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(rt32 >>_s sa) - } - } diff --git a/cheri/sail_latex/sailfnexecuteSRL.tex b/cheri/sail_latex/sailfnexecuteSRL.tex deleted file mode 100644 index 961ea82f..00000000 --- a/cheri/sail_latex/sailfnexecuteSRL.tex +++ /dev/null @@ -1,10 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSRL]{SRL}#(rt, rd, sa)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - if (#\hyperref[zNotWordVal]{NotWordVal}#(temp)) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined - else { - rt32 = temp[31..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(rt32 >> sa); - } - } diff --git a/cheri/sail_latex/sailfnexecuteSRLV.tex b/cheri/sail_latex/sailfnexecuteSRLV.tex deleted file mode 100644 index 9b859a85..00000000 --- a/cheri/sail_latex/sailfnexecuteSRLV.tex +++ /dev/null @@ -1,11 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSRLV]{SRLV}#(rs, rt, rd)) = - { - temp = #\hyperref[zrGPR]{rGPR}#(rt); - sa = (#\hyperref[zrGPR]{rGPR}#(rs))[4..0]; - if (#\hyperref[zNotWordVal]{NotWordVal}#(temp)) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined - else { - rt32 = temp[31..0]; - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(rt32 >> sa); - } - } diff --git a/cheri/sail_latex/sailfnexecuteSUB.tex b/cheri/sail_latex/sailfnexecuteSUB.tex deleted file mode 100644 index 8a7b9d61..00000000 --- a/cheri/sail_latex/sailfnexecuteSUB.tex +++ /dev/null @@ -1,13 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSUB]{SUB}#(rs, rt, rd)) = - { - opA = #\hyperref[zrGPR]{rGPR}#(rs); - opB = #\hyperref[zrGPR]{rGPR}#(rt); - if #\hyperref[zNotWordVal]{NotWordVal}#(opA) | #\hyperref[zNotWordVal]{NotWordVal}#(opB) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined /* XXX could instead */ - else - let temp33 : #\hyperref[zbits]{bits}#(33) = #\hyperref[zsignzyextend]{sign\_extend}#(opA[31..0]) - #\hyperref[zsignzyextend]{sign\_extend}#(opB[31..0]) in - if temp33[32] != temp33[31] then - (#\hyperref[zSignalException]{SignalException}#(Ov)) - else - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(temp33[31..0]) - } diff --git a/cheri/sail_latex/sailfnexecuteSUBU.tex b/cheri/sail_latex/sailfnexecuteSUBU.tex deleted file mode 100644 index 65b106e1..00000000 --- a/cheri/sail_latex/sailfnexecuteSUBU.tex +++ /dev/null @@ -1,9 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSUBU]{SUBU}#(rs, rt, rd)) = - { - opA = #\hyperref[zrGPR]{rGPR}#(rs); - opB = #\hyperref[zrGPR]{rGPR}#(rt); - if #\hyperref[zNotWordVal]{NotWordVal}#(opA) | #\hyperref[zNotWordVal]{NotWordVal}#(opB) then - #\hyperref[zwGPR]{wGPR}#(rd) = undefined - else - #\hyperref[zwGPR]{wGPR}#(rd) = #\hyperref[zsignzyextend]{sign\_extend}#(opA[31..0] - opB[31..0]) - } diff --git a/cheri/sail_latex/sailfnexecuteSWL.tex b/cheri/sail_latex/sailfnexecuteSWL.tex deleted file mode 100644 index 56ed19a6..00000000 --- a/cheri/sail_latex/sailfnexecuteSWL.tex +++ /dev/null @@ -1,15 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zSWL]{SWL}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), StoreData, WL); - let pAddr = #\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, StoreData) in - { - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - match vAddr[1..0] - { - 0b00 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 4) = reg_val[31..0]), - 0b01 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 3) = reg_val[31..8]), - 0b10 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 2) = reg_val[31..16]), - 0b11 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 1) = reg_val[31..24]) - } - } - } diff --git a/cheri/sail_latex/sailfnexecuteSWR.tex b/cheri/sail_latex/sailfnexecuteSWR.tex deleted file mode 100644 index 9b0815e9..00000000 --- a/cheri/sail_latex/sailfnexecuteSWR.tex +++ /dev/null @@ -1,16 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zSWR]{SWR}#(base, rt, offset)) = - { - vAddr = #\hyperref[zaddrWrapperUnaligned]{addrWrapperUnaligned}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), StoreData, WR); - let pAddr = #\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, StoreData) in - { - wordAddr = pAddr[63..2] @ 0b00; - reg_val = #\hyperref[zrGPR]{rGPR}#(rt); - match vAddr[1..0] - { - 0b00 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 1) = reg_val[7..0]), - 0b01 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 2) = reg_val[15..0]), - 0b10 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 3) = reg_val[23..0]), - 0b11 => (#\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(wordAddr, 4) = reg_val[31..0]) - } - } - } diff --git a/cheri/sail_latex/sailfnexecuteSYNC.tex b/cheri/sail_latex/sailfnexecuteSYNC.tex deleted file mode 100644 index e5d5a25e..00000000 --- a/cheri/sail_latex/sailfnexecuteSYNC.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zexecute]{execute}#(#\hyperref[zSYNC]{SYNC}#()) = - #\hyperref[zMEMzysync]{MEM\_sync}#() diff --git a/cheri/sail_latex/sailfnexecuteSYSCALL.tex b/cheri/sail_latex/sailfnexecuteSYSCALL.tex deleted file mode 100644 index 35fc0371..00000000 --- a/cheri/sail_latex/sailfnexecuteSYSCALL.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zSYSCALL]{SYSCALL}#()) = - { - (#\hyperref[zSignalException]{SignalException}#(Sys)) - } diff --git a/cheri/sail_latex/sailfnexecuteStore.tex b/cheri/sail_latex/sailfnexecuteStore.tex deleted file mode 100644 index 1030fdd2..00000000 --- a/cheri/sail_latex/sailfnexecuteStore.tex +++ /dev/null @@ -1,29 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zStore]{Store}#(width, conditional, base, rt, offset)) = - { - vAddr : #\hyperref[zbits]{bits}#(64) = #\hyperref[zaddrWrapper]{addrWrapper}#(#\hyperref[zsignzyextend]{sign\_extend}#(offset) + #\hyperref[zrGPR]{rGPR}#(base), StoreData, width); - rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - if ~ (#\hyperref[zisAddressAligned]{isAddressAligned}#(vAddr, width)) then - (#\hyperref[zSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr)) /* unaligned access */ - else - let pAddr = (#\hyperref[zTLBTranslate]{TLBTranslate}#(vAddr, StoreData)) in - { - if (conditional) then - { - success : bool = if (CP0LLBit[0]) then match width - { - W => #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 4, rt_val[31..0]), - D => #\hyperref[zMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 8, rt_val), - _ => throw(#\hyperref[zErrorzyinternalzyerror]{Error\_internal\_error}#()) /* there is no sbc or shc */ - } else false; - #\hyperref[zwGPR]{wGPR}#(rt) = #\hyperref[zzzerozyextend]{zero\_extend}#(success) - } - else - match width - { - B => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 1) = rt_val[7..0], - H => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 2) = rt_val[15..0], - W => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 4) = rt_val[31..0], - D => #\hyperref[zMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 8) = rt_val - } - } - } diff --git a/cheri/sail_latex/sailfnexecuteTLBP.tex b/cheri/sail_latex/sailfnexecuteTLBP.tex deleted file mode 100644 index 1c781dda..00000000 --- a/cheri/sail_latex/sailfnexecuteTLBP.tex +++ /dev/null @@ -1,14 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zTLBP]{TLBP}#()) = { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - let result = #\hyperref[ztlbSearch]{tlbSearch}#(TLBEntryHi.#\hyperref[zbits]{bits}#()) in - match result { - (#\hyperref[zSome]{Some}#(idx)) => { - TLBProbe = [bitzero]; - TLBIndex = idx; - }, - #\hyperref[zNone]{None}#() => { - TLBProbe = [bitone]; - TLBIndex = 0b000000; - } - } -} diff --git a/cheri/sail_latex/sailfnexecuteTLBR.tex b/cheri/sail_latex/sailfnexecuteTLBR.tex deleted file mode 100644 index fd7aefd2..00000000 --- a/cheri/sail_latex/sailfnexecuteTLBR.tex +++ /dev/null @@ -1,24 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zTLBR]{TLBR}#()) = { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - let i as atom(_) = #\hyperref[zunsigned]{unsigned}#(TLBIndex) in - let entry = #\hyperref[zregzyderef]{reg\_deref}#(TLBEntries[i]) in { - TLBPageMask = entry.#\hyperref[zpagemask]{pagemask}#(); - TLBEntryHi->#\hyperref[zR]{R}#() = entry.#\hyperref[zr]{r}#(); - TLBEntryHi->#\hyperref[zVPNtwo]{VPN2}#() = entry.#\hyperref[zvpntwo]{vpn2}#(); - TLBEntryHi->#\hyperref[zASID]{ASID}#() = entry.#\hyperref[zasid]{asid}#(); - TLBEntryLo0->#\hyperref[zCapS]{CapS}#()= entry.#\hyperref[zcapszero]{caps0}#(); - TLBEntryLo0->#\hyperref[zCapL]{CapL}#()= entry.#\hyperref[zcaplzero]{capl0}#(); - TLBEntryLo0->#\hyperref[zPFN]{PFN}#() = entry.#\hyperref[zpfnzero]{pfn0}#(); - TLBEntryLo0->#\hyperref[zC]{C}#() = entry.#\hyperref[zczero]{c0}#(); - TLBEntryLo0->#\hyperref[zD]{D}#() = entry.#\hyperref[zdzero]{d0}#(); - TLBEntryLo0->#\hyperref[zV]{V}#() = entry.#\hyperref[zvzero]{v0}#(); - TLBEntryLo0->#\hyperref[zG]{G}#() = entry.#\hyperref[zg]{g}#(); - TLBEntryLo1->#\hyperref[zCapS]{CapS}#()= entry.#\hyperref[zcapsone]{caps1}#(); - TLBEntryLo1->#\hyperref[zCapL]{CapL}#()= entry.#\hyperref[zcaplone]{capl1}#(); - TLBEntryLo1->#\hyperref[zPFN]{PFN}#() = entry.#\hyperref[zpfnone]{pfn1}#(); - TLBEntryLo1->#\hyperref[zC]{C}#() = entry.#\hyperref[zcone]{c1}#(); - TLBEntryLo1->#\hyperref[zD]{D}#() = entry.#\hyperref[zdone]{d1}#(); - TLBEntryLo1->#\hyperref[zV]{V}#() = entry.#\hyperref[zvone]{v1}#(); - TLBEntryLo1->#\hyperref[zG]{G}#() = entry.#\hyperref[zg]{g}#(); - } -} diff --git a/cheri/sail_latex/sailfnexecuteTLBWI.tex b/cheri/sail_latex/sailfnexecuteTLBWI.tex deleted file mode 100644 index 2b32342e..00000000 --- a/cheri/sail_latex/sailfnexecuteTLBWI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zTLBWI]{TLBWI}#()) = { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - #\hyperref[zTLBWriteEntry]{TLBWriteEntry}#(TLBIndex); -} diff --git a/cheri/sail_latex/sailfnexecuteTLBWR.tex b/cheri/sail_latex/sailfnexecuteTLBWR.tex deleted file mode 100644 index df582e88..00000000 --- a/cheri/sail_latex/sailfnexecuteTLBWR.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zTLBWR]{TLBWR}#()) = { - #\hyperref[zcheckCPzeroAccess]{checkCP0Access}#(); - #\hyperref[zTLBWriteEntry]{TLBWriteEntry}#(TLBRandom); -} diff --git a/cheri/sail_latex/sailfnexecuteTRAPIMM.tex b/cheri/sail_latex/sailfnexecuteTRAPIMM.tex deleted file mode 100644 index 9fa187e9..00000000 --- a/cheri/sail_latex/sailfnexecuteTRAPIMM.tex +++ /dev/null @@ -1,8 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, cmp)) = - { - rs_val = #\hyperref[zrGPR]{rGPR}#(rs); - imm_val : #\hyperref[zbits]{bits}#(64) = #\hyperref[zsignzyextend]{sign\_extend}#(imm); - condition = #\hyperref[zcompare]{compare}#(cmp, rs_val, imm_val); - if (condition) then - (#\hyperref[zSignalException]{SignalException}#(Tr)) - } diff --git a/cheri/sail_latex/sailfnexecuteTRAPREG.tex b/cheri/sail_latex/sailfnexecuteTRAPREG.tex deleted file mode 100644 index 9d3d759c..00000000 --- a/cheri/sail_latex/sailfnexecuteTRAPREG.tex +++ /dev/null @@ -1,8 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, cmp)) = - { - rs_val = #\hyperref[zrGPR]{rGPR}#(rs); - rt_val = #\hyperref[zrGPR]{rGPR}#(rt); - condition = #\hyperref[zcompare]{compare}#(cmp, rs_val, rt_val); - if (condition) then - (#\hyperref[zSignalException]{SignalException}#(Tr)) - } diff --git a/cheri/sail_latex/sailfnexecuteWAIT.tex b/cheri/sail_latex/sailfnexecuteWAIT.tex deleted file mode 100644 index 9ef8ce0e..00000000 --- a/cheri/sail_latex/sailfnexecuteWAIT.tex +++ /dev/null @@ -1,3 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zWAIT]{WAIT}#()) = { - nextPC = PC; -} diff --git a/cheri/sail_latex/sailfnexecuteXOR.tex b/cheri/sail_latex/sailfnexecuteXOR.tex deleted file mode 100644 index 79e89bc5..00000000 --- a/cheri/sail_latex/sailfnexecuteXOR.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zXOR]{XOR}# (rs, rt, rd)) = - { - #\hyperref[zwGPR]{wGPR}#(rd) = (#\hyperref[zrGPR]{rGPR}#(rs) ^ #\hyperref[zrGPR]{rGPR}#(rt)) - } diff --git a/cheri/sail_latex/sailfnexecuteXORI.tex b/cheri/sail_latex/sailfnexecuteXORI.tex deleted file mode 100644 index 1310c125..00000000 --- a/cheri/sail_latex/sailfnexecuteXORI.tex +++ /dev/null @@ -1,4 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zXORI]{XORI}# (rs, rt, imm)) = - { - #\hyperref[zwGPR]{wGPR}#(rt) = (#\hyperref[zrGPR]{rGPR}#(rs) ^ #\hyperref[zzzerozyextend]{zero\_extend}#(imm)) - } diff --git a/cheri/sail_latex/sailfnexecutebranch.tex b/cheri/sail_latex/sailfnexecutebranch.tex deleted file mode 100644 index 9f2f03fc..00000000 --- a/cheri/sail_latex/sailfnexecutebranch.tex +++ /dev/null @@ -1,4 +0,0 @@ -function #\hyperref[zexecutezybranch]{execute\_branch}#(pc) = { - delayedPC = pc; - branchPending = 0b1; -} diff --git a/cheri/sail_latex/sailfnexecutebranchpcc.tex b/cheri/sail_latex/sailfnexecutebranchpcc.tex deleted file mode 100644 index 8c803ce2..00000000 --- a/cheri/sail_latex/sailfnexecutebranchpcc.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zexecutezybranchzypcc]{execute\_branch\_pcc}#(newPCC) = { - delayedPC = #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapOffset]{getCapOffset}#(newPCC)); - delayedPCC = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(newPCC); - branchPending = 0b1; -} diff --git a/cheri/sail_latex/sailfnextendLoad.tex b/cheri/sail_latex/sailfnextendLoad.tex deleted file mode 100644 index 08d1f9a4..00000000 --- a/cheri/sail_latex/sailfnextendLoad.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zextendLoad]{extendLoad}#(memResult, sign) = { - if (sign) then - #\hyperref[zsignzyextend]{sign\_extend}#(memResult) - else - #\hyperref[zzzerozyextend]{zero\_extend}#(memResult) -} diff --git a/cheri/sail_latex/sailfngetAccessLevel.tex b/cheri/sail_latex/sailfngetAccessLevel.tex deleted file mode 100644 index c37a672e..00000000 --- a/cheri/sail_latex/sailfngetAccessLevel.tex +++ /dev/null @@ -1,10 +0,0 @@ -function #\hyperref[zgetAccessLevel]{getAccessLevel}#() = - if ((CP0Status.#\hyperref[zEXL]{EXL}#()) | (CP0Status.#\hyperref[zERL]{ERL}#())) then - Kernel - else match CP0Status.#\hyperref[zKSU]{KSU}#() - { - 0b00 => Kernel, - 0b01 => Supervisor, - 0b10 => User, - _ => User /* behaviour undefined, assume user */ - } diff --git a/cheri/sail_latex/sailfngetCapBase.tex b/cheri/sail_latex/sailfngetCapBase.tex deleted file mode 100644 index 92f7963b..00000000 --- a/cheri/sail_latex/sailfngetCapBase.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zgetCapBase]{getCapBase}#(c) : CapStruct -> uint64 = #\hyperref[zunsigned]{unsigned}#(c.base) diff --git a/cheri/sail_latex/sailfngetCapCauseRegExcCode.tex b/cheri/sail_latex/sailfngetCapCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCapCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCapCauseRegRegNum.tex b/cheri/sail_latex/sailfngetCapCauseRegRegNum.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCapCauseRegRegNum.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCapCauseRegbits.tex b/cheri/sail_latex/sailfngetCapCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCapCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCapCursor.tex b/cheri/sail_latex/sailfngetCapCursor.tex deleted file mode 100644 index 06750973..00000000 --- a/cheri/sail_latex/sailfngetCapCursor.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zgetCapCursor]{getCapCursor}#(c) : CapStruct -> uint64 = #\hyperref[zunsigned]{unsigned}#(c.address) diff --git a/cheri/sail_latex/sailfngetCapLength.tex b/cheri/sail_latex/sailfngetCapLength.tex deleted file mode 100644 index 501ed940..00000000 --- a/cheri/sail_latex/sailfngetCapLength.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zgetCapLength]{getCapLength}#(c) : CapStruct -> CapLen = #\hyperref[zunsigned]{unsigned}#(c.length) diff --git a/cheri/sail_latex/sailfngetCapOffset.tex b/cheri/sail_latex/sailfngetCapOffset.tex deleted file mode 100644 index d1dc5f8d..00000000 --- a/cheri/sail_latex/sailfngetCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zgetCapOffset]{getCapOffset}#(c) : CapStruct -> uint64 = (#\hyperref[zunsigned]{unsigned}#(c.address) - #\hyperref[zunsigned]{unsigned}#(c.base)) % (#\hyperref[zpowtwo]{pow2}#(64)) diff --git a/cheri/sail_latex/sailfngetCapPerms.tex b/cheri/sail_latex/sailfngetCapPerms.tex deleted file mode 100644 index 932930ae..00000000 --- a/cheri/sail_latex/sailfngetCapPerms.tex +++ /dev/null @@ -1,16 +0,0 @@ -function #\hyperref[zgetCapPerms]{getCapPerms}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(31) = - ( - cap.uperms - @ cap.perm_reserved11_14 - @ cap.access_system_regs - @ cap.permit_unseal - @ cap.permit_ccall - @ cap.permit_seal - @ cap.permit_store_local_cap - @ cap.permit_store_cap - @ cap.permit_load_cap - @ cap.permit_store - @ cap.permit_load - @ cap.permit_execute - @ cap.global - ) diff --git a/cheri/sail_latex/sailfngetCapTop.tex b/cheri/sail_latex/sailfngetCapTop.tex deleted file mode 100644 index 3a3c74d5..00000000 --- a/cheri/sail_latex/sailfngetCapTop.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zgetCapTop]{getCapTop}#(c) : CapStruct -> CapLen = #\hyperref[zunsigned]{unsigned}#(c.base) + #\hyperref[zunsigned]{unsigned}#(c.length) /* XXX bug here? -- should be mod 2^64 */ diff --git a/cheri/sail_latex/sailfngetCauseRegBD.tex b/cheri/sail_latex/sailfngetCauseRegBD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegBD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCauseRegCE.tex b/cheri/sail_latex/sailfngetCauseRegCE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegCE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCauseRegExcCode.tex b/cheri/sail_latex/sailfngetCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCauseRegIP.tex b/cheri/sail_latex/sailfngetCauseRegIP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegIP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCauseRegIV.tex b/cheri/sail_latex/sailfngetCauseRegIV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegIV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCauseRegWP.tex b/cheri/sail_latex/sailfngetCauseRegWP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegWP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetCauseRegbits.tex b/cheri/sail_latex/sailfngetCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetContextRegBadVPNtwo.tex b/cheri/sail_latex/sailfngetContextRegBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetContextRegBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetContextRegPTEBase.tex b/cheri/sail_latex/sailfngetContextRegPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetContextRegPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetContextRegbits.tex b/cheri/sail_latex/sailfngetContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegBEV.tex b/cheri/sail_latex/sailfngetStatusRegBEV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegBEV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegCU.tex b/cheri/sail_latex/sailfngetStatusRegCU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegCU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegERL.tex b/cheri/sail_latex/sailfngetStatusRegERL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegERL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegEXL.tex b/cheri/sail_latex/sailfngetStatusRegEXL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegEXL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegIE.tex b/cheri/sail_latex/sailfngetStatusRegIE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegIE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegIM.tex b/cheri/sail_latex/sailfngetStatusRegIM.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegIM.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegKSU.tex b/cheri/sail_latex/sailfngetStatusRegKSU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegKSU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegKX.tex b/cheri/sail_latex/sailfngetStatusRegKX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegKX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegSX.tex b/cheri/sail_latex/sailfngetStatusRegSX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegSX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegUX.tex b/cheri/sail_latex/sailfngetStatusRegUX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegUX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetStatusRegbits.tex b/cheri/sail_latex/sailfngetStatusRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetStatusRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryHiRegASID.tex b/cheri/sail_latex/sailfngetTLBEntryHiRegASID.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryHiRegASID.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryHiRegR.tex b/cheri/sail_latex/sailfngetTLBEntryHiRegR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryHiRegR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryHiRegVPNtwo.tex b/cheri/sail_latex/sailfngetTLBEntryHiRegVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryHiRegVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryHiRegbits.tex b/cheri/sail_latex/sailfngetTLBEntryHiRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryHiRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegC.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegC.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegC.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegCapL.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegCapL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegCapL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegCapS.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegCapS.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegCapS.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegD.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegG.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegG.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegG.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegPFN.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegPFN.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegPFN.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegV.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryLoRegbits.tex b/cheri/sail_latex/sailfngetTLBEntryLoRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryLoRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryasid.tex b/cheri/sail_latex/sailfngetTLBEntryasid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryasid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrybits.tex b/cheri/sail_latex/sailfngetTLBEntrybits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrybits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrycaplone.tex b/cheri/sail_latex/sailfngetTLBEntrycaplone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrycaplone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrycaplzero.tex b/cheri/sail_latex/sailfngetTLBEntrycaplzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrycaplzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrycapsone.tex b/cheri/sail_latex/sailfngetTLBEntrycapsone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrycapsone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrycapszero.tex b/cheri/sail_latex/sailfngetTLBEntrycapszero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrycapszero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrycone.tex b/cheri/sail_latex/sailfngetTLBEntrycone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrycone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryczero.tex b/cheri/sail_latex/sailfngetTLBEntryczero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryczero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrydone.tex b/cheri/sail_latex/sailfngetTLBEntrydone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrydone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrydzero.tex b/cheri/sail_latex/sailfngetTLBEntrydzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrydzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryg.tex b/cheri/sail_latex/sailfngetTLBEntryg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrypagemask.tex b/cheri/sail_latex/sailfngetTLBEntrypagemask.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrypagemask.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrypfnone.tex b/cheri/sail_latex/sailfngetTLBEntrypfnone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrypfnone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntrypfnzero.tex b/cheri/sail_latex/sailfngetTLBEntrypfnzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntrypfnzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryr.tex b/cheri/sail_latex/sailfngetTLBEntryr.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryr.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryvalid.tex b/cheri/sail_latex/sailfngetTLBEntryvalid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryvalid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryvone.tex b/cheri/sail_latex/sailfngetTLBEntryvone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryvone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryvpntwo.tex b/cheri/sail_latex/sailfngetTLBEntryvpntwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetTLBEntryvzero.tex b/cheri/sail_latex/sailfngetTLBEntryvzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetTLBEntryvzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetXContextRegXBadVPNtwo.tex b/cheri/sail_latex/sailfngetXContextRegXBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetXContextRegXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetXContextRegXPTEBase.tex b/cheri/sail_latex/sailfngetXContextRegXPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetXContextRegXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetXContextRegXR.tex b/cheri/sail_latex/sailfngetXContextRegXR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetXContextRegXR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngetXContextRegbits.tex b/cheri/sail_latex/sailfngetXContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfngetXContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfngrantsAccess.tex b/cheri/sail_latex/sailfngrantsAccess.tex deleted file mode 100644 index 0840683d..00000000 --- a/cheri/sail_latex/sailfngrantsAccess.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zgrantsAccess]{grantsAccess}# (currentLevel, requiredLevel) = - #\hyperref[zintzyofzyAccessLevel]{int\_of\_AccessLevel}#(currentLevel) >= #\hyperref[zintzyofzyAccessLevel]{int\_of\_AccessLevel}#(requiredLevel) diff --git a/cheri/sail_latex/sailfnincCapOffset.tex b/cheri/sail_latex/sailfnincCapOffset.tex deleted file mode 100644 index 134bc1fd..00000000 --- a/cheri/sail_latex/sailfnincCapOffset.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zincCapOffset]{incCapOffset}#(c, delta) = - let newAddr : #\hyperref[zbits]{bits}#(64) = c.address + delta in - (true, {c with address = newAddr}) diff --git a/cheri/sail_latex/sailfnincrementCPzeroCount.tex b/cheri/sail_latex/sailfnincrementCPzeroCount.tex deleted file mode 100644 index 71ca2e51..00000000 --- a/cheri/sail_latex/sailfnincrementCPzeroCount.tex +++ /dev/null @@ -1,17 +0,0 @@ -function #\hyperref[zincrementCPzeroCount]{incrementCP0Count}#() = { - TLBRandom = (if (TLBRandom == TLBWired) - then (TLBIndexMax) else (TLBRandom - 1)); - - CP0Count = (CP0Count + 1); - if (CP0Count == CP0Compare) then { - CP0Cause->#\hyperref[zIP]{IP}#() = CP0Cause.#\hyperref[zIP]{IP}#() | 0x80; /* IP7 is timer interrupt */ - }; - - let ims = CP0Status.#\hyperref[zIM]{IM}#() in - let ips = CP0Cause.#\hyperref[zIP]{IP}#() in - let ie = CP0Status.#\hyperref[zIE]{IE}#() in - let exl = CP0Status.#\hyperref[zEXL]{EXL}#() in - let erl = CP0Status.#\hyperref[zERL]{ERL}#() in - if ((~(exl)) & (~(erl)) & ie & ((ips & ims) != 0x00)) then - #\hyperref[zSignalException]{SignalException}#(Interrupt); -} diff --git a/cheri/sail_latex/sailfninitcptwostate.tex b/cheri/sail_latex/sailfninitcptwostate.tex deleted file mode 100644 index ea9e07b5..00000000 --- a/cheri/sail_latex/sailfninitcptwostate.tex +++ /dev/null @@ -1,19 +0,0 @@ -function #\hyperref[zinitzycptwozystate]{init\_cp2\_state}# () = { - let defaultBits = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(default_cap); - let nullBits = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(null_cap); - PCC = defaultBits; - nextPCC = defaultBits; - delayedPCC = defaultBits; - DDC = defaultBits; - KCC = defaultBits; - EPCC = defaultBits; - KDC = nullBits; - KR1C = nullBits; - KR2C = nullBits; - CTLSP = nullBits; - CTLSU = nullBits; - foreach(i from 1 to 31) { - let idx = #\hyperref[ztozybits]{to\_bits}#(5, i) in - #\hyperref[zwriteCapReg]{writeCapReg}#(idx, null_cap) - } -} diff --git a/cheri/sail_latex/sailfninitcpzerostate.tex b/cheri/sail_latex/sailfninitcpzerostate.tex deleted file mode 100644 index be4ebee2..00000000 --- a/cheri/sail_latex/sailfninitcpzerostate.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zinitzycpzerozystate]{init\_cp0\_state}# () : unit -> unit = { - CP0Status->#\hyperref[zBEV]{BEV}#() = bitone; -} diff --git a/cheri/sail_latex/sailfnintofAccessLevel.tex b/cheri/sail_latex/sailfnintofAccessLevel.tex deleted file mode 100644 index 0a5bb3c6..00000000 --- a/cheri/sail_latex/sailfnintofAccessLevel.tex +++ /dev/null @@ -1,6 +0,0 @@ -function int_of_AccessLevel level = - match level { - User => 0, - Supervisor => 1, - Kernel => 2 - } diff --git a/cheri/sail_latex/sailfninttocap.tex b/cheri/sail_latex/sailfninttocap.tex deleted file mode 100644 index a10d10c1..00000000 --- a/cheri/sail_latex/sailfninttocap.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zintzytozycap]{int\_to\_cap}# (address) : #\hyperref[zbits]{bits}#(64) -> CapStruct = - {null_cap with address = address} diff --git a/cheri/sail_latex/sailfnisAddressAligned.tex b/cheri/sail_latex/sailfnisAddressAligned.tex deleted file mode 100644 index 212605ce..00000000 --- a/cheri/sail_latex/sailfnisAddressAligned.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zisAddressAligned]{isAddressAligned}# (addr, wordType) = - let a = #\hyperref[zunsigned]{unsigned}#(addr) in - a / alignment_width == (a + #\hyperref[zwordWidthBytes]{wordWidthBytes}#(wordType) - 1) / alignment_width diff --git a/cheri/sail_latex/sailfnisnone.tex b/cheri/sail_latex/sailfnisnone.tex deleted file mode 100644 index 877cc2a0..00000000 --- a/cheri/sail_latex/sailfnisnone.tex +++ /dev/null @@ -1,4 +0,0 @@ -function is_none opt = match opt { - #\hyperref[zSome]{Some}#(_) => false, - #\hyperref[zNone]{None}#() => true -} diff --git a/cheri/sail_latex/sailfnissome.tex b/cheri/sail_latex/sailfnissome.tex deleted file mode 100644 index f1f5f655..00000000 --- a/cheri/sail_latex/sailfnissome.tex +++ /dev/null @@ -1,4 +0,0 @@ -function is_some opt = match opt { - #\hyperref[zSome]{Some}#(_) => true, - #\hyperref[zNone]{None}#() => false -} diff --git a/cheri/sail_latex/sailfnmask.tex b/cheri/sail_latex/sailfnmask.tex deleted file mode 100644 index e62ea529..00000000 --- a/cheri/sail_latex/sailfnmask.tex +++ /dev/null @@ -1 +0,0 @@ -function mask bs = bs['n - 1 .. 0] diff --git a/cheri/sail_latex/sailfnmemBitsToCapBits.tex b/cheri/sail_latex/sailfnmemBitsToCapBits.tex deleted file mode 100644 index f5dc7a3b..00000000 --- a/cheri/sail_latex/sailfnmemBitsToCapBits.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zmemBitsToCapBits]{memBitsToCapBits}#(tag, b) : (bool, #\hyperref[zbits]{bits}#(256)) -> #\hyperref[zbits]{bits}#(257) = - tag @ (b ^ null_cap_bits) diff --git a/cheri/sail_latex/sailfnmipssignextend.tex b/cheri/sail_latex/sailfnmipssignextend.tex deleted file mode 100644 index 80945b61..00000000 --- a/cheri/sail_latex/sailfnmipssignextend.tex +++ /dev/null @@ -1 +0,0 @@ -function mips_sign_extend v = #\hyperref[zsailzysignzyextend]{sail\_sign\_extend}#(v, sizeof('m)) diff --git a/cheri/sail_latex/sailfnmipszzeroextend.tex b/cheri/sail_latex/sailfnmipszzeroextend.tex deleted file mode 100644 index 6c9914d9..00000000 --- a/cheri/sail_latex/sailfnmipszzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -function mips_zero_extend v = #\hyperref[zsailzyzzerozyextend]{sail\_zero\_extend}#(v, sizeof('m)) diff --git a/cheri/sail_latex/sailfnneqanything.tex b/cheri/sail_latex/sailfnneqanything.tex deleted file mode 100644 index 1605ed05..00000000 --- a/cheri/sail_latex/sailfnneqanything.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyanything]{neq\_anything}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(x == y) diff --git a/cheri/sail_latex/sailfnneqatom.tex b/cheri/sail_latex/sailfnneqatom.tex deleted file mode 100644 index e9a9f93f..00000000 --- a/cheri/sail_latex/sailfnneqatom.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyatom]{neq\_atom}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzyatom]{eq\_atom}#(x, y)) diff --git a/cheri/sail_latex/sailfnneqbool.tex b/cheri/sail_latex/sailfnneqbool.tex deleted file mode 100644 index 65007b8e..00000000 --- a/cheri/sail_latex/sailfnneqbool.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzybool]{neq\_bool}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzybool]{eq\_bool}#(x, y)) diff --git a/cheri/sail_latex/sailfnneqint.tex b/cheri/sail_latex/sailfnneqint.tex deleted file mode 100644 index 952a7735..00000000 --- a/cheri/sail_latex/sailfnneqint.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyint]{neq\_int}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzyint]{eq\_int}#(x, y)) diff --git a/cheri/sail_latex/sailfnneqrange.tex b/cheri/sail_latex/sailfnneqrange.tex deleted file mode 100644 index 43f49e9e..00000000 --- a/cheri/sail_latex/sailfnneqrange.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyrange]{neq\_range}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzyrange]{eq\_range}#(x, y)) diff --git a/cheri/sail_latex/sailfnneqvec.tex b/cheri/sail_latex/sailfnneqvec.tex deleted file mode 100644 index c446df08..00000000 --- a/cheri/sail_latex/sailfnneqvec.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyvec]{neq\_vec}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzybits]{eq\_bits}#(x, y)) diff --git a/cheri/sail_latex/sailfnnumofAccessLevel.tex b/cheri/sail_latex/sailfnnumofAccessLevel.tex deleted file mode 100644 index a5a1d8af..00000000 --- a/cheri/sail_latex/sailfnnumofAccessLevel.tex +++ /dev/null @@ -1,5 +0,0 @@ -function num_of_AccessLevel arg# = match arg# { - User => 0, - Supervisor => 1, - Kernel => 2 -} diff --git a/cheri/sail_latex/sailfnnumofCPtrCmpOp.tex b/cheri/sail_latex/sailfnnumofCPtrCmpOp.tex deleted file mode 100644 index 4d20546b..00000000 --- a/cheri/sail_latex/sailfnnumofCPtrCmpOp.tex +++ /dev/null @@ -1,10 +0,0 @@ -function num_of_CPtrCmpOp arg# = match arg# { - CEQ => 0, - CNE => 1, - CLT => 2, - CLE => 3, - CLTU => 4, - CLEU => 5, - CEXEQ => 6, - CNEXEQ => 7 -} diff --git a/cheri/sail_latex/sailfnnumofCapEx.tex b/cheri/sail_latex/sailfnnumofCapEx.tex deleted file mode 100644 index d2ee7b0f..00000000 --- a/cheri/sail_latex/sailfnnumofCapEx.tex +++ /dev/null @@ -1,25 +0,0 @@ -function num_of_CapEx arg# = match arg# { - CapEx_None => 0, - CapEx_LengthViolation => 1, - CapEx_TagViolation => 2, - CapEx_SealViolation => 3, - CapEx_TypeViolation => 4, - CapEx_CallTrap => 5, - CapEx_ReturnTrap => 6, - CapEx_TSSUnderFlow => 7, - CapEx_UserDefViolation => 8, - CapEx_TLBNoStoreCap => 9, - CapEx_InexactBounds => 10, - CapEx_GlobalViolation => 11, - CapEx_PermitExecuteViolation => 12, - CapEx_PermitLoadViolation => 13, - CapEx_PermitStoreViolation => 14, - CapEx_PermitLoadCapViolation => 15, - CapEx_PermitStoreCapViolation => 16, - CapEx_PermitStoreLocalCapViolation => 17, - CapEx_PermitSealViolation => 18, - CapEx_AccessSystemRegsViolation => 19, - CapEx_PermitCCallViolation => 20, - CapEx_AccessCCallIDCViolation => 21, - CapEx_PermitUnsealViolation => 22 -} diff --git a/cheri/sail_latex/sailfnnumofClearRegSet.tex b/cheri/sail_latex/sailfnnumofClearRegSet.tex deleted file mode 100644 index 3dd58b89..00000000 --- a/cheri/sail_latex/sailfnnumofClearRegSet.tex +++ /dev/null @@ -1,6 +0,0 @@ -function num_of_ClearRegSet arg# = match arg# { - GPLo => 0, - GPHi => 1, - CLo => 2, - CHi => 3 -} diff --git a/cheri/sail_latex/sailfnnumofComparison.tex b/cheri/sail_latex/sailfnnumofComparison.tex deleted file mode 100644 index d98bebc2..00000000 --- a/cheri/sail_latex/sailfnnumofComparison.tex +++ /dev/null @@ -1,10 +0,0 @@ -function num_of_Comparison arg# = match arg# { - EQ => 0, - NE => 1, - GE => 2, - GEU => 3, - GT => 4, - LE => 5, - LT => 6, - LTU => 7 -} diff --git a/cheri/sail_latex/sailfnnumofException.tex b/cheri/sail_latex/sailfnnumofException.tex deleted file mode 100644 index 02bad081..00000000 --- a/cheri/sail_latex/sailfnnumofException.tex +++ /dev/null @@ -1,21 +0,0 @@ -function num_of_Exception arg# = match arg# { - Interrupt => 0, - TLBMod => 1, - TLBL => 2, - TLBS => 3, - AdEL => 4, - AdES => 5, - Sys => 6, - Bp => 7, - ResI => 8, - CpU => 9, - Ov => 10, - Tr => 11, - C2E => 12, - C2Trap => 13, - XTLBRefillL => 14, - XTLBRefillS => 15, - XTLBInvL => 16, - XTLBInvS => 17, - MCheck => 18 -} diff --git a/cheri/sail_latex/sailfnnumofMemAccessType.tex b/cheri/sail_latex/sailfnnumofMemAccessType.tex deleted file mode 100644 index 47b1af66..00000000 --- a/cheri/sail_latex/sailfnnumofMemAccessType.tex +++ /dev/null @@ -1,5 +0,0 @@ -function num_of_MemAccessType arg# = match arg# { - Instruction => 0, - LoadData => 1, - StoreData => 2 -} diff --git a/cheri/sail_latex/sailfnnumofWordType.tex b/cheri/sail_latex/sailfnnumofWordType.tex deleted file mode 100644 index 0ed09f63..00000000 --- a/cheri/sail_latex/sailfnnumofWordType.tex +++ /dev/null @@ -1,6 +0,0 @@ -function num_of_WordType arg# = match arg# { - B => 0, - H => 1, - W => 2, - D => 3 -} diff --git a/cheri/sail_latex/sailfnnumofWordTypeUnaligned.tex b/cheri/sail_latex/sailfnnumofWordTypeUnaligned.tex deleted file mode 100644 index f6b61ce7..00000000 --- a/cheri/sail_latex/sailfnnumofWordTypeUnaligned.tex +++ /dev/null @@ -1,6 +0,0 @@ -function num_of_WordTypeUnaligned arg# = match arg# { - WL => 0, - WR => 1, - DL => 2, - DR => 3 -} diff --git a/cheri/sail_latex/sailfnnumofdecodefailure.tex b/cheri/sail_latex/sailfnnumofdecodefailure.tex deleted file mode 100644 index 3b5fadb3..00000000 --- a/cheri/sail_latex/sailfnnumofdecodefailure.tex +++ /dev/null @@ -1,6 +0,0 @@ -function num_of_decode_failure arg# = match arg# { - no_matching_pattern => 0, - unsupported_instruction => 1, - illegal_instruction => 2, - internal_error => 3 -} diff --git a/cheri/sail_latex/sailfnones.tex b/cheri/sail_latex/sailfnones.tex deleted file mode 100644 index e58040d7..00000000 --- a/cheri/sail_latex/sailfnones.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zones]{ones}#() = #\hyperref[zreplicatezybits]{replicate\_bits}# (0b1,'n) diff --git a/cheri/sail_latex/sailfnpccaccesssystemregs.tex b/cheri/sail_latex/sailfnpccaccesssystemregs.tex deleted file mode 100644 index 3e54b060..00000000 --- a/cheri/sail_latex/sailfnpccaccesssystemregs.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# () = - let pcc = #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(PCC) in - (pcc.access_system_regs) diff --git a/cheri/sail_latex/sailfnrGPR.tex b/cheri/sail_latex/sailfnrGPR.tex deleted file mode 100644 index 751d67a3..00000000 --- a/cheri/sail_latex/sailfnrGPR.tex +++ /dev/null @@ -1,4 +0,0 @@ -function rGPR idx = { - let i as atom(_) = #\hyperref[zunsigned]{unsigned}#(idx) in - if i == 0 then 0x0000000000000000 else GPR[i] -} diff --git a/cheri/sail_latex/sailfnraisectwoexception.tex b/cheri/sail_latex/sailfnraisectwoexception.tex deleted file mode 100644 index e3d6bcbb..00000000 --- a/cheri/sail_latex/sailfnraisectwoexception.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(capEx, regnum) = - let reg8 = 0b000 @ regnum in - if ((capEx == CapEx_AccessSystemRegsViolation) & (regnum == IDCNO)) then - #\hyperref[zraisezyctwozyexceptioneight]{raise\_c2\_exception8}#(CapEx_AccessCCallIDCViolation, reg8) - else - #\hyperref[zraisezyctwozyexceptioneight]{raise\_c2\_exception8}#(capEx, reg8) diff --git a/cheri/sail_latex/sailfnraisectwoexceptioneight.tex b/cheri/sail_latex/sailfnraisectwoexceptioneight.tex deleted file mode 100644 index b6490aa0..00000000 --- a/cheri/sail_latex/sailfnraisectwoexceptioneight.tex +++ /dev/null @@ -1,9 +0,0 @@ -function #\hyperref[zraisezyctwozyexceptioneight]{raise\_c2\_exception8}#(capEx, regnum) = - { - CapCause->#\hyperref[zExcCode]{ExcCode}#() = #\hyperref[zCapExCode]{CapExCode}#(capEx); - CapCause->#\hyperref[zRegNum]{RegNum}#() = regnum; - let mipsEx = - if ((capEx == CapEx_CallTrap) | (capEx == CapEx_ReturnTrap)) - then C2Trap else C2E in - #\hyperref[zSignalException]{SignalException}#(mipsEx); - } diff --git a/cheri/sail_latex/sailfnraisectwoexceptionnoreg.tex b/cheri/sail_latex/sailfnraisectwoexceptionnoreg.tex deleted file mode 100644 index db246d80..00000000 --- a/cheri/sail_latex/sailfnraisectwoexceptionnoreg.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zraisezyctwozyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(capEx) = - #\hyperref[zraisezyctwozyexceptioneight]{raise\_c2\_exception8}#(capEx, 0xff) diff --git a/cheri/sail_latex/sailfnreadCapReg.tex b/cheri/sail_latex/sailfnreadCapReg.tex deleted file mode 100644 index 357027c3..00000000 --- a/cheri/sail_latex/sailfnreadCapReg.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zreadCapReg]{readCapReg}#(n) = - if (n == 0b00000) then - null_cap - else - let i = #\hyperref[zunsigned]{unsigned}#(n) in - #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(#\hyperref[zregzyderef]{reg\_deref}#(CapRegs[i])) diff --git a/cheri/sail_latex/sailfnreadCapRegDDC.tex b/cheri/sail_latex/sailfnreadCapRegDDC.tex deleted file mode 100644 index f2fea30c..00000000 --- a/cheri/sail_latex/sailfnreadCapRegDDC.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zreadCapRegDDC]{readCapRegDDC}#(n) = - let i = #\hyperref[zunsigned]{unsigned}#(n) in - #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(#\hyperref[zregzyderef]{reg\_deref}#(CapRegs[i])) /* NB CapRegs[0] is points to DDC */ diff --git a/cheri/sail_latex/sailfnregisterinaccessible.tex b/cheri/sail_latex/sailfnregisterinaccessible.tex deleted file mode 100644 index 368d01a4..00000000 --- a/cheri/sail_latex/sailfnregisterinaccessible.tex +++ /dev/null @@ -1,7 +0,0 @@ -function #\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(r) = - ((r == IDCNO) & inCCallDelay) | - ((r == KR1CNO | - r == KR2CNO | - r == KDCNO | - r == KCCNO | - r == EPCCNO) & #\hyperref[znot]{not}# (#\hyperref[zpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# ())) diff --git a/cheri/sail_latex/sailfnsailmask.tex b/cheri/sail_latex/sailfnsailmask.tex deleted file mode 100644 index 37ede658..00000000 --- a/cheri/sail_latex/sailfnsailmask.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zsailzymask]{sail\_mask}#(len, v) = if len <= #\hyperref[zlength]{length}#(v) then #\hyperref[ztruncate]{truncate}#(v, len) else #\hyperref[zsailzyzzerozyextend]{sail\_zero\_extend}#(v, len) diff --git a/cheri/sail_latex/sailfnsealCap.tex b/cheri/sail_latex/sailfnsealCap.tex deleted file mode 100644 index beb1435b..00000000 --- a/cheri/sail_latex/sailfnsealCap.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zsealCap]{sealCap}#(cap, otype) : (CapStruct, #\hyperref[zbits]{bits}#(24)) -> (bool, CapStruct) = - (true, {cap with sealed=true, otype=otype}) diff --git a/cheri/sail_latex/sailfnsetCapBounds.tex b/cheri/sail_latex/sailfnsetCapBounds.tex deleted file mode 100644 index cb689dd8..00000000 --- a/cheri/sail_latex/sailfnsetCapBounds.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zsetCapBounds]{setCapBounds}#(cap, base, top) = - let length : #\hyperref[zbits]{bits}#(65) = top - (0b0 @ base) in - (true, {cap with base = base, length = length[63..0], address = base}) diff --git a/cheri/sail_latex/sailfnsetCapCauseRegExcCode.tex b/cheri/sail_latex/sailfnsetCapCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCapCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCapCauseRegRegNum.tex b/cheri/sail_latex/sailfnsetCapCauseRegRegNum.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCapCauseRegRegNum.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCapCauseRegbits.tex b/cheri/sail_latex/sailfnsetCapCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCapCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCapOffset.tex b/cheri/sail_latex/sailfnsetCapOffset.tex deleted file mode 100644 index 404630e3..00000000 --- a/cheri/sail_latex/sailfnsetCapOffset.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zsetCapOffset]{setCapOffset}#(c, offset) = - (true, {c with address=c.base + offset}) diff --git a/cheri/sail_latex/sailfnsetCapPerms.tex b/cheri/sail_latex/sailfnsetCapPerms.tex deleted file mode 100644 index 1a1f67bd..00000000 --- a/cheri/sail_latex/sailfnsetCapPerms.tex +++ /dev/null @@ -1,16 +0,0 @@ -function #\hyperref[zsetCapPerms]{setCapPerms}#(cap, perms) : (CapStruct, #\hyperref[zbits]{bits}#(31)) -> CapStruct = - { cap with - uperms = perms[30..15], - /* perm_reserved11_14 = perms[14..11], XXX should allow to set? only affects cbuildcap. */ - access_system_regs = perms[10], - permit_unseal = perms[9], - permit_ccall = perms[8], - permit_seal = perms[7], - permit_store_local_cap = perms[6], - permit_store_cap = perms[5], - permit_load_cap = perms[4], - permit_store = perms[3], - permit_load = perms[2], - permit_execute = perms[1], - global = perms[0] - } diff --git a/cheri/sail_latex/sailfnsetCauseRegBD.tex b/cheri/sail_latex/sailfnsetCauseRegBD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegBD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCauseRegCE.tex b/cheri/sail_latex/sailfnsetCauseRegCE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegCE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCauseRegExcCode.tex b/cheri/sail_latex/sailfnsetCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCauseRegIP.tex b/cheri/sail_latex/sailfnsetCauseRegIP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegIP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCauseRegIV.tex b/cheri/sail_latex/sailfnsetCauseRegIV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegIV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCauseRegWP.tex b/cheri/sail_latex/sailfnsetCauseRegWP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegWP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetCauseRegbits.tex b/cheri/sail_latex/sailfnsetCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetContextRegBadVPNtwo.tex b/cheri/sail_latex/sailfnsetContextRegBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetContextRegBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetContextRegPTEBase.tex b/cheri/sail_latex/sailfnsetContextRegPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetContextRegPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetContextRegbits.tex b/cheri/sail_latex/sailfnsetContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegBEV.tex b/cheri/sail_latex/sailfnsetStatusRegBEV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegBEV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegCU.tex b/cheri/sail_latex/sailfnsetStatusRegCU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegCU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegERL.tex b/cheri/sail_latex/sailfnsetStatusRegERL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegERL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegEXL.tex b/cheri/sail_latex/sailfnsetStatusRegEXL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegEXL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegIE.tex b/cheri/sail_latex/sailfnsetStatusRegIE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegIE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegIM.tex b/cheri/sail_latex/sailfnsetStatusRegIM.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegIM.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegKSU.tex b/cheri/sail_latex/sailfnsetStatusRegKSU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegKSU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegKX.tex b/cheri/sail_latex/sailfnsetStatusRegKX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegKX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegSX.tex b/cheri/sail_latex/sailfnsetStatusRegSX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegSX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegUX.tex b/cheri/sail_latex/sailfnsetStatusRegUX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegUX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetStatusRegbits.tex b/cheri/sail_latex/sailfnsetStatusRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetStatusRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryHiRegASID.tex b/cheri/sail_latex/sailfnsetTLBEntryHiRegASID.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryHiRegASID.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryHiRegR.tex b/cheri/sail_latex/sailfnsetTLBEntryHiRegR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryHiRegR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryHiRegVPNtwo.tex b/cheri/sail_latex/sailfnsetTLBEntryHiRegVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryHiRegVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryHiRegbits.tex b/cheri/sail_latex/sailfnsetTLBEntryHiRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryHiRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegC.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegC.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegC.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegCapL.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegCapL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegCapL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegCapS.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegCapS.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegCapS.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegD.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegG.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegG.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegG.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegPFN.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegPFN.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegPFN.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegV.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryLoRegbits.tex b/cheri/sail_latex/sailfnsetTLBEntryLoRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryLoRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryasid.tex b/cheri/sail_latex/sailfnsetTLBEntryasid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryasid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrybits.tex b/cheri/sail_latex/sailfnsetTLBEntrybits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrybits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrycaplone.tex b/cheri/sail_latex/sailfnsetTLBEntrycaplone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrycaplone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrycaplzero.tex b/cheri/sail_latex/sailfnsetTLBEntrycaplzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrycaplzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrycapsone.tex b/cheri/sail_latex/sailfnsetTLBEntrycapsone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrycapsone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrycapszero.tex b/cheri/sail_latex/sailfnsetTLBEntrycapszero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrycapszero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrycone.tex b/cheri/sail_latex/sailfnsetTLBEntrycone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrycone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryczero.tex b/cheri/sail_latex/sailfnsetTLBEntryczero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryczero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrydone.tex b/cheri/sail_latex/sailfnsetTLBEntrydone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrydone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrydzero.tex b/cheri/sail_latex/sailfnsetTLBEntrydzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrydzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryg.tex b/cheri/sail_latex/sailfnsetTLBEntryg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrypagemask.tex b/cheri/sail_latex/sailfnsetTLBEntrypagemask.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrypagemask.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrypfnone.tex b/cheri/sail_latex/sailfnsetTLBEntrypfnone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrypfnone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntrypfnzero.tex b/cheri/sail_latex/sailfnsetTLBEntrypfnzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntrypfnzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryr.tex b/cheri/sail_latex/sailfnsetTLBEntryr.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryr.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryvalid.tex b/cheri/sail_latex/sailfnsetTLBEntryvalid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryvalid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryvone.tex b/cheri/sail_latex/sailfnsetTLBEntryvone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryvone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryvpntwo.tex b/cheri/sail_latex/sailfnsetTLBEntryvpntwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetTLBEntryvzero.tex b/cheri/sail_latex/sailfnsetTLBEntryvzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetTLBEntryvzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetXContextRegXBadVPNtwo.tex b/cheri/sail_latex/sailfnsetXContextRegXBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetXContextRegXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetXContextRegXPTEBase.tex b/cheri/sail_latex/sailfnsetXContextRegXPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetXContextRegXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetXContextRegXR.tex b/cheri/sail_latex/sailfnsetXContextRegXR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetXContextRegXR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsetXContextRegbits.tex b/cheri/sail_latex/sailfnsetXContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnsetXContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnsupportedinstructions.tex b/cheri/sail_latex/sailfnsupportedinstructions.tex deleted file mode 100644 index b3ffdfa4..00000000 --- a/cheri/sail_latex/sailfnsupportedinstructions.tex +++ /dev/null @@ -1 +0,0 @@ -function supported_instructions instr = #\hyperref[zSome]{Some}#(instr) diff --git a/cheri/sail_latex/sailfntlbEntryMatch.tex b/cheri/sail_latex/sailfntlbEntryMatch.tex deleted file mode 100644 index f952062f..00000000 --- a/cheri/sail_latex/sailfntlbEntryMatch.tex +++ /dev/null @@ -1,12 +0,0 @@ -function #\hyperref[ztlbEntryMatch]{tlbEntryMatch}#(r, vpn2, asid, entry) = - let entryValid = entry.#\hyperref[zvalid]{valid}#() in - let entryR = entry.#\hyperref[zr]{r}#() in - let entryMask = entry.#\hyperref[zpagemask]{pagemask}#() in - let entryVPN = entry.#\hyperref[zvpntwo]{vpn2}#() in - let entryASID = entry.#\hyperref[zasid]{asid}#() in - let entryG = entry.#\hyperref[zg]{g}#() in - let vpnMask : #\hyperref[zbits]{bits}#(27) = ~(#\hyperref[zzzerozyextend]{zero\_extend}#(entryMask)) in - (entryValid & - (r == entryR) & - ((vpn2 & vpnMask) == ((entryVPN) & vpnMask)) & - ((asid == (entryASID)) | (entryG))) diff --git a/cheri/sail_latex/sailfntlbSearch.tex b/cheri/sail_latex/sailfntlbSearch.tex deleted file mode 100644 index 8bce6f3b..00000000 --- a/cheri/sail_latex/sailfntlbSearch.tex +++ /dev/null @@ -1,10 +0,0 @@ -function #\hyperref[ztlbSearch]{tlbSearch}#(VAddr) = - let r = (VAddr[63..62]) in - let vpn2 = (VAddr[39..13]) in - let asid = TLBEntryHi.#\hyperref[zASID]{ASID}#() in { - foreach (idx from 0 to 63) { - if(#\hyperref[ztlbEntryMatch]{tlbEntryMatch}#(r, vpn2, asid, #\hyperref[zregzyderef]{reg\_deref}#(TLBEntries[idx]))) then - return #\hyperref[zSome]{Some}#(#\hyperref[ztozybits]{to\_bits}#(6, idx)) - }; - #\hyperref[zNone]{None}#() - } diff --git a/cheri/sail_latex/sailfntobits.tex b/cheri/sail_latex/sailfntobits.tex deleted file mode 100644 index d1df5e83..00000000 --- a/cheri/sail_latex/sailfntobits.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[ztozybits]{to\_bits}# (l, n) = #\hyperref[zgetzyslicezyint]{get\_slice\_int}#(l, n, 0) diff --git a/cheri/sail_latex/sailfnupdateCapCauseRegExcCode.tex b/cheri/sail_latex/sailfnupdateCapCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCapCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCapCauseRegRegNum.tex b/cheri/sail_latex/sailfnupdateCapCauseRegRegNum.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCapCauseRegRegNum.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCapCauseRegbits.tex b/cheri/sail_latex/sailfnupdateCapCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCapCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegBD.tex b/cheri/sail_latex/sailfnupdateCauseRegBD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegBD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegCE.tex b/cheri/sail_latex/sailfnupdateCauseRegCE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegCE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegExcCode.tex b/cheri/sail_latex/sailfnupdateCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegIP.tex b/cheri/sail_latex/sailfnupdateCauseRegIP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegIP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegIV.tex b/cheri/sail_latex/sailfnupdateCauseRegIV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegIV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegWP.tex b/cheri/sail_latex/sailfnupdateCauseRegWP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegWP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateCauseRegbits.tex b/cheri/sail_latex/sailfnupdateCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateContextRegBadVPNtwo.tex b/cheri/sail_latex/sailfnupdateContextRegBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateContextRegBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateContextRegPTEBase.tex b/cheri/sail_latex/sailfnupdateContextRegPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateContextRegPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateContextRegbits.tex b/cheri/sail_latex/sailfnupdateContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegBEV.tex b/cheri/sail_latex/sailfnupdateStatusRegBEV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegBEV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegCU.tex b/cheri/sail_latex/sailfnupdateStatusRegCU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegCU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegERL.tex b/cheri/sail_latex/sailfnupdateStatusRegERL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegERL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegEXL.tex b/cheri/sail_latex/sailfnupdateStatusRegEXL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegEXL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegIE.tex b/cheri/sail_latex/sailfnupdateStatusRegIE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegIE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegIM.tex b/cheri/sail_latex/sailfnupdateStatusRegIM.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegIM.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegKSU.tex b/cheri/sail_latex/sailfnupdateStatusRegKSU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegKSU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegKX.tex b/cheri/sail_latex/sailfnupdateStatusRegKX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegKX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegSX.tex b/cheri/sail_latex/sailfnupdateStatusRegSX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegSX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegUX.tex b/cheri/sail_latex/sailfnupdateStatusRegUX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegUX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateStatusRegbits.tex b/cheri/sail_latex/sailfnupdateStatusRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateStatusRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryHiRegASID.tex b/cheri/sail_latex/sailfnupdateTLBEntryHiRegASID.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryHiRegASID.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryHiRegR.tex b/cheri/sail_latex/sailfnupdateTLBEntryHiRegR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryHiRegR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryHiRegVPNtwo.tex b/cheri/sail_latex/sailfnupdateTLBEntryHiRegVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryHiRegVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryHiRegbits.tex b/cheri/sail_latex/sailfnupdateTLBEntryHiRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryHiRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegC.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegC.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegC.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegCapL.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegCapL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegCapL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegCapS.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegCapS.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegCapS.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegD.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegG.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegG.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegG.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegPFN.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegPFN.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegPFN.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegV.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryLoRegbits.tex b/cheri/sail_latex/sailfnupdateTLBEntryLoRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryLoRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryasid.tex b/cheri/sail_latex/sailfnupdateTLBEntryasid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryasid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrybits.tex b/cheri/sail_latex/sailfnupdateTLBEntrybits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrybits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrycaplone.tex b/cheri/sail_latex/sailfnupdateTLBEntrycaplone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrycaplone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrycaplzero.tex b/cheri/sail_latex/sailfnupdateTLBEntrycaplzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrycaplzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrycapsone.tex b/cheri/sail_latex/sailfnupdateTLBEntrycapsone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrycapsone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrycapszero.tex b/cheri/sail_latex/sailfnupdateTLBEntrycapszero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrycapszero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrycone.tex b/cheri/sail_latex/sailfnupdateTLBEntrycone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrycone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryczero.tex b/cheri/sail_latex/sailfnupdateTLBEntryczero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryczero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrydone.tex b/cheri/sail_latex/sailfnupdateTLBEntrydone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrydone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrydzero.tex b/cheri/sail_latex/sailfnupdateTLBEntrydzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrydzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryg.tex b/cheri/sail_latex/sailfnupdateTLBEntryg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrypagemask.tex b/cheri/sail_latex/sailfnupdateTLBEntrypagemask.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrypagemask.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrypfnone.tex b/cheri/sail_latex/sailfnupdateTLBEntrypfnone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrypfnone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntrypfnzero.tex b/cheri/sail_latex/sailfnupdateTLBEntrypfnzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntrypfnzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryr.tex b/cheri/sail_latex/sailfnupdateTLBEntryr.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryr.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryvalid.tex b/cheri/sail_latex/sailfnupdateTLBEntryvalid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryvalid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryvone.tex b/cheri/sail_latex/sailfnupdateTLBEntryvone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryvone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryvpntwo.tex b/cheri/sail_latex/sailfnupdateTLBEntryvpntwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateTLBEntryvzero.tex b/cheri/sail_latex/sailfnupdateTLBEntryvzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateTLBEntryvzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateXContextRegXBadVPNtwo.tex b/cheri/sail_latex/sailfnupdateXContextRegXBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateXContextRegXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateXContextRegXPTEBase.tex b/cheri/sail_latex/sailfnupdateXContextRegXPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateXContextRegXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateXContextRegXR.tex b/cheri/sail_latex/sailfnupdateXContextRegXR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateXContextRegXR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnupdateXContextRegbits.tex b/cheri/sail_latex/sailfnupdateXContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailfnupdateXContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailfnwGPR.tex b/cheri/sail_latex/sailfnwGPR.tex deleted file mode 100644 index 338d4b5c..00000000 --- a/cheri/sail_latex/sailfnwGPR.tex +++ /dev/null @@ -1,8 +0,0 @@ -function #\hyperref[zwGPR]{wGPR}# (idx, v) = { - let i as atom(_) = #\hyperref[zunsigned]{unsigned}#(idx) in - if i != 0 then { - /*#\hyperref[zprerrzystring]{prerr\_string}#(#\hyperref[zstringzyofzyint]{string\_of\_int}#(i)); - #\hyperref[zprerrzybits]{prerr\_bits}#(" <- ", v);*/ - GPR[i] = v; - }; -} diff --git a/cheri/sail_latex/sailfnwordWidthBytes.tex b/cheri/sail_latex/sailfnwordWidthBytes.tex deleted file mode 100644 index a5760d98..00000000 --- a/cheri/sail_latex/sailfnwordWidthBytes.tex +++ /dev/null @@ -1,7 +0,0 @@ -function #\hyperref[zwordWidthBytes]{wordWidthBytes}#(w) = - match w { - B => 1, - H => 2, - W => 4, - D => 8 - } diff --git a/cheri/sail_latex/sailfnwriteCapReg.tex b/cheri/sail_latex/sailfnwriteCapReg.tex deleted file mode 100644 index d8de79fd..00000000 --- a/cheri/sail_latex/sailfnwriteCapReg.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zwriteCapReg]{writeCapReg}#(n, cap) : (regno, CapStruct) -> unit = - if (n == 0b00000) then - () - else - let i = #\hyperref[zunsigned]{unsigned}#(n) in - (*CapRegs[i]) = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(cap) diff --git a/cheri/sail_latex/sailfnzeightoperatorzzerozIsznine.tex b/cheri/sail_latex/sailfnzeightoperatorzzerozIsznine.tex deleted file mode 100644 index 62e5a2e4..00000000 --- a/cheri/sail_latex/sailfnzeightoperatorzzerozIsznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator <#\hyperref[zzys]{\_s}# (x, y) = #\hyperref[zsigned]{signed}#(x) < #\hyperref[zsigned]{signed}#(y) diff --git a/cheri/sail_latex/sailfnzeightoperatorzzerozIuznine.tex b/cheri/sail_latex/sailfnzeightoperatorzzerozIuznine.tex deleted file mode 100644 index 3f946820..00000000 --- a/cheri/sail_latex/sailfnzeightoperatorzzerozIuznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator <#\hyperref[zzyu]{\_u}# (x, y) = #\hyperref[zunsigned]{unsigned}#(x) < #\hyperref[zunsigned]{unsigned}#(y) diff --git a/cheri/sail_latex/sailfnzeightoperatorzzerozKzJsznine.tex b/cheri/sail_latex/sailfnzeightoperatorzzerozKzJsznine.tex deleted file mode 100644 index 57ecf181..00000000 --- a/cheri/sail_latex/sailfnzeightoperatorzzerozKzJsznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator >=#\hyperref[zzys]{\_s}# (x, y) = #\hyperref[zsigned]{signed}#(x) >= #\hyperref[zsigned]{signed}#(y) diff --git a/cheri/sail_latex/sailfnzeightoperatorzzerozKzJuznine.tex b/cheri/sail_latex/sailfnzeightoperatorzzerozKzJuznine.tex deleted file mode 100644 index 6df36c6f..00000000 --- a/cheri/sail_latex/sailfnzeightoperatorzzerozKzJuznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator >=#\hyperref[zzyu]{\_u}# (x, y) = #\hyperref[zunsigned]{unsigned}#(x) >= #\hyperref[zunsigned]{unsigned}#(y) diff --git a/cheri/sail_latex/sailfnzeightoperatorzzerozQzQznine.tex b/cheri/sail_latex/sailfnzeightoperatorzzerozQzQznine.tex deleted file mode 100644 index 2c372e1b..00000000 --- a/cheri/sail_latex/sailfnzeightoperatorzzerozQzQznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator ^^ (bs, n) = #\hyperref[zreplicatezybits]{replicate\_bits}# (bs, n) diff --git a/cheri/sail_latex/sailfnzzeros.tex b/cheri/sail_latex/sailfnzzeros.tex deleted file mode 100644 index 38d463fb..00000000 --- a/cheri/sail_latex/sailfnzzeros.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zzzeros]{zeros}#() = #\hyperref[zreplicatezybits]{replicate\_bits}# (0b0,'n) diff --git a/cheri/sail_latex/sailgetAccessLevel.tex b/cheri/sail_latex/sailgetAccessLevel.tex deleted file mode 100644 index 4412096c..00000000 --- a/cheri/sail_latex/sailgetAccessLevel.tex +++ /dev/null @@ -1 +0,0 @@ -val getAccessLevel : unit -> AccessLevel effect {rreg} diff --git a/cheri/sail_latex/sailgetCapBase.tex b/cheri/sail_latex/sailgetCapBase.tex deleted file mode 100644 index c7044d1d..00000000 --- a/cheri/sail_latex/sailgetCapBase.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapBase : CapStruct -> uint64 diff --git a/cheri/sail_latex/sailgetCapCauseRegExcCode.tex b/cheri/sail_latex/sailgetCapCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCapCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCapCauseRegRegNum.tex b/cheri/sail_latex/sailgetCapCauseRegRegNum.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCapCauseRegRegNum.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCapCauseRegbits.tex b/cheri/sail_latex/sailgetCapCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCapCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCapCursor.tex b/cheri/sail_latex/sailgetCapCursor.tex deleted file mode 100644 index fd5d72d8..00000000 --- a/cheri/sail_latex/sailgetCapCursor.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapCursor : CapStruct -> uint64 diff --git a/cheri/sail_latex/sailgetCapLength.tex b/cheri/sail_latex/sailgetCapLength.tex deleted file mode 100644 index aaa822c8..00000000 --- a/cheri/sail_latex/sailgetCapLength.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapLength : CapStruct -> CapLen diff --git a/cheri/sail_latex/sailgetCapOffset.tex b/cheri/sail_latex/sailgetCapOffset.tex deleted file mode 100644 index 668c3df1..00000000 --- a/cheri/sail_latex/sailgetCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapOffset : CapStruct -> uint64 diff --git a/cheri/sail_latex/sailgetCapPerms.tex b/cheri/sail_latex/sailgetCapPerms.tex deleted file mode 100644 index b2dabf89..00000000 --- a/cheri/sail_latex/sailgetCapPerms.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapPerms : CapStruct -> bits(31) diff --git a/cheri/sail_latex/sailgetCapTop.tex b/cheri/sail_latex/sailgetCapTop.tex deleted file mode 100644 index ff0e5f95..00000000 --- a/cheri/sail_latex/sailgetCapTop.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapTop : CapStruct -> CapLen diff --git a/cheri/sail_latex/sailgetCauseRegBD.tex b/cheri/sail_latex/sailgetCauseRegBD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegBD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCauseRegCE.tex b/cheri/sail_latex/sailgetCauseRegCE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegCE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCauseRegExcCode.tex b/cheri/sail_latex/sailgetCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCauseRegIP.tex b/cheri/sail_latex/sailgetCauseRegIP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegIP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCauseRegIV.tex b/cheri/sail_latex/sailgetCauseRegIV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegIV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCauseRegWP.tex b/cheri/sail_latex/sailgetCauseRegWP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegWP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetCauseRegbits.tex b/cheri/sail_latex/sailgetCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetContextRegBadVPNtwo.tex b/cheri/sail_latex/sailgetContextRegBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetContextRegBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetContextRegPTEBase.tex b/cheri/sail_latex/sailgetContextRegPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetContextRegPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetContextRegbits.tex b/cheri/sail_latex/sailgetContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegBEV.tex b/cheri/sail_latex/sailgetStatusRegBEV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegBEV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegCU.tex b/cheri/sail_latex/sailgetStatusRegCU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegCU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegERL.tex b/cheri/sail_latex/sailgetStatusRegERL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegERL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegEXL.tex b/cheri/sail_latex/sailgetStatusRegEXL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegEXL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegIE.tex b/cheri/sail_latex/sailgetStatusRegIE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegIE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegIM.tex b/cheri/sail_latex/sailgetStatusRegIM.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegIM.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegKSU.tex b/cheri/sail_latex/sailgetStatusRegKSU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegKSU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegKX.tex b/cheri/sail_latex/sailgetStatusRegKX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegKX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegSX.tex b/cheri/sail_latex/sailgetStatusRegSX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegSX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegUX.tex b/cheri/sail_latex/sailgetStatusRegUX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegUX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetStatusRegbits.tex b/cheri/sail_latex/sailgetStatusRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetStatusRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryHiRegASID.tex b/cheri/sail_latex/sailgetTLBEntryHiRegASID.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryHiRegASID.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryHiRegR.tex b/cheri/sail_latex/sailgetTLBEntryHiRegR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryHiRegR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryHiRegVPNtwo.tex b/cheri/sail_latex/sailgetTLBEntryHiRegVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryHiRegVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryHiRegbits.tex b/cheri/sail_latex/sailgetTLBEntryHiRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryHiRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegC.tex b/cheri/sail_latex/sailgetTLBEntryLoRegC.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegC.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegCapL.tex b/cheri/sail_latex/sailgetTLBEntryLoRegCapL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegCapL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegCapS.tex b/cheri/sail_latex/sailgetTLBEntryLoRegCapS.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegCapS.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegD.tex b/cheri/sail_latex/sailgetTLBEntryLoRegD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegG.tex b/cheri/sail_latex/sailgetTLBEntryLoRegG.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegG.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegPFN.tex b/cheri/sail_latex/sailgetTLBEntryLoRegPFN.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegPFN.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegV.tex b/cheri/sail_latex/sailgetTLBEntryLoRegV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryLoRegbits.tex b/cheri/sail_latex/sailgetTLBEntryLoRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryLoRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryasid.tex b/cheri/sail_latex/sailgetTLBEntryasid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryasid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrybits.tex b/cheri/sail_latex/sailgetTLBEntrybits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrybits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrycaplone.tex b/cheri/sail_latex/sailgetTLBEntrycaplone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrycaplone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrycaplzero.tex b/cheri/sail_latex/sailgetTLBEntrycaplzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrycaplzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrycapsone.tex b/cheri/sail_latex/sailgetTLBEntrycapsone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrycapsone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrycapszero.tex b/cheri/sail_latex/sailgetTLBEntrycapszero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrycapszero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrycone.tex b/cheri/sail_latex/sailgetTLBEntrycone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrycone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryczero.tex b/cheri/sail_latex/sailgetTLBEntryczero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryczero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrydone.tex b/cheri/sail_latex/sailgetTLBEntrydone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrydone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrydzero.tex b/cheri/sail_latex/sailgetTLBEntrydzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrydzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryg.tex b/cheri/sail_latex/sailgetTLBEntryg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrypagemask.tex b/cheri/sail_latex/sailgetTLBEntrypagemask.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrypagemask.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrypfnone.tex b/cheri/sail_latex/sailgetTLBEntrypfnone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrypfnone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntrypfnzero.tex b/cheri/sail_latex/sailgetTLBEntrypfnzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntrypfnzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryr.tex b/cheri/sail_latex/sailgetTLBEntryr.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryr.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryvalid.tex b/cheri/sail_latex/sailgetTLBEntryvalid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryvalid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryvone.tex b/cheri/sail_latex/sailgetTLBEntryvone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryvone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryvpntwo.tex b/cheri/sail_latex/sailgetTLBEntryvpntwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetTLBEntryvzero.tex b/cheri/sail_latex/sailgetTLBEntryvzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetTLBEntryvzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetXContextRegXBadVPNtwo.tex b/cheri/sail_latex/sailgetXContextRegXBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetXContextRegXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetXContextRegXPTEBase.tex b/cheri/sail_latex/sailgetXContextRegXPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetXContextRegXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetXContextRegXR.tex b/cheri/sail_latex/sailgetXContextRegXR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetXContextRegXR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetXContextRegbits.tex b/cheri/sail_latex/sailgetXContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailgetXContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailgetsliceint.tex b/cheri/sail_latex/sailgetsliceint.tex deleted file mode 100644 index 2b30d096..00000000 --- a/cheri/sail_latex/sailgetsliceint.tex +++ /dev/null @@ -1 +0,0 @@ -val get_slice_int = "get_slice_int" : forall 'w. (atom('w), int, int) -> #\hyperref[zbits]{bits}#('w) diff --git a/cheri/sail_latex/sailgettimens.tex b/cheri/sail_latex/sailgettimens.tex deleted file mode 100644 index 74cfd526..00000000 --- a/cheri/sail_latex/sailgettimens.tex +++ /dev/null @@ -1 +0,0 @@ -val "get_time_ns" : unit -> int diff --git a/cheri/sail_latex/sailgrantsAccess.tex b/cheri/sail_latex/sailgrantsAccess.tex deleted file mode 100644 index ab28ac58..00000000 --- a/cheri/sail_latex/sailgrantsAccess.tex +++ /dev/null @@ -1 +0,0 @@ -val grantsAccess : (AccessLevel, AccessLevel) -> bool diff --git a/cheri/sail_latex/sailgtatom.tex b/cheri/sail_latex/sailgtatom.tex deleted file mode 100644 index b2147a8f..00000000 --- a/cheri/sail_latex/sailgtatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_atom = {coq: "Z.gtb", _: "gt"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latex/sailgtatomrange.tex b/cheri/sail_latex/sailgtatomrange.tex deleted file mode 100644 index 3c520181..00000000 --- a/cheri/sail_latex/sailgtatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_atom_range = {coq: "gtb_range_r", _: "gt"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latex/sailgteqatom.tex b/cheri/sail_latex/sailgteqatom.tex deleted file mode 100644 index fb3b66b2..00000000 --- a/cheri/sail_latex/sailgteqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_atom = {coq: "Z.geb", _: "gteq"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latex/sailgteqatomrange.tex b/cheri/sail_latex/sailgteqatomrange.tex deleted file mode 100644 index 7aaf633f..00000000 --- a/cheri/sail_latex/sailgteqatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_atom_range = {coq: "geb_range_r", _: "gteq"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latex/sailgteqint.tex b/cheri/sail_latex/sailgteqint.tex deleted file mode 100644 index 77271d1f..00000000 --- a/cheri/sail_latex/sailgteqint.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_int = {coq: "Z.geb", _:"gteq"} : (int, int) -> bool diff --git a/cheri/sail_latex/sailgteqrangeatom.tex b/cheri/sail_latex/sailgteqrangeatom.tex deleted file mode 100644 index fda25265..00000000 --- a/cheri/sail_latex/sailgteqrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_range_atom = {coq: "geb_range_l", _: "gteq"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latex/sailgtint.tex b/cheri/sail_latex/sailgtint.tex deleted file mode 100644 index 2d953eec..00000000 --- a/cheri/sail_latex/sailgtint.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_int = {coq: "Z.gtb", _:"gt"} : (int, int) -> bool diff --git a/cheri/sail_latex/sailgtrangeatom.tex b/cheri/sail_latex/sailgtrangeatom.tex deleted file mode 100644 index b8635909..00000000 --- a/cheri/sail_latex/sailgtrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_range_atom = {coq: "gtb_range_l", _: "gt"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latex/sailimmonesix.tex b/cheri/sail_latex/sailimmonesix.tex deleted file mode 100644 index bec28c6c..00000000 --- a/cheri/sail_latex/sailimmonesix.tex +++ /dev/null @@ -1 +0,0 @@ -type imm16 = #\hyperref[zbits]{bits}#(16) /* 16-bit immediate */ diff --git a/cheri/sail_latex/sailincCapOffset.tex b/cheri/sail_latex/sailincCapOffset.tex deleted file mode 100644 index 8e182ff3..00000000 --- a/cheri/sail_latex/sailincCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -val incCapOffset : (CapStruct, #\hyperref[zbits]{bits}#(64)) -> (bool, CapStruct) diff --git a/cheri/sail_latex/sailincrementCPzeroCount.tex b/cheri/sail_latex/sailincrementCPzeroCount.tex deleted file mode 100644 index ca1384eb..00000000 --- a/cheri/sail_latex/sailincrementCPzeroCount.tex +++ /dev/null @@ -1 +0,0 @@ -val incrementCP0Count : unit -> unit effect {rreg,wreg,escape} diff --git a/cheri/sail_latex/sailinitcptwostate.tex b/cheri/sail_latex/sailinitcptwostate.tex deleted file mode 100644 index 98ced710..00000000 --- a/cheri/sail_latex/sailinitcptwostate.tex +++ /dev/null @@ -1 +0,0 @@ -val init_cp2_state : unit -> unit effect {wreg} diff --git a/cheri/sail_latex/sailinitcpzerostate.tex b/cheri/sail_latex/sailinitcpzerostate.tex deleted file mode 100644 index 743cc402..00000000 --- a/cheri/sail_latex/sailinitcpzerostate.tex +++ /dev/null @@ -1 +0,0 @@ -val init_cp0_state : unit -> unit effect {wreg} diff --git a/cheri/sail_latex/sailintofAccessLevel.tex b/cheri/sail_latex/sailintofAccessLevel.tex deleted file mode 100644 index 257f321f..00000000 --- a/cheri/sail_latex/sailintofAccessLevel.tex +++ /dev/null @@ -1 +0,0 @@ -val int_of_AccessLevel : AccessLevel -> {|0, 1, 2|} effect pure diff --git a/cheri/sail_latex/sailintpower.tex b/cheri/sail_latex/sailintpower.tex deleted file mode 100644 index 0aa13188..00000000 --- a/cheri/sail_latex/sailintpower.tex +++ /dev/null @@ -1 +0,0 @@ -val int_power = {ocaml: "int_power", lem: "pow", coq: "Z.pow"} : (int, int) -> int diff --git a/cheri/sail_latex/sailinttocap.tex b/cheri/sail_latex/sailinttocap.tex deleted file mode 100644 index 0f4cd328..00000000 --- a/cheri/sail_latex/sailinttocap.tex +++ /dev/null @@ -1 +0,0 @@ -val int_to_cap : bits(64) -> CapStruct diff --git a/cheri/sail_latex/sailisAddressAligned.tex b/cheri/sail_latex/sailisAddressAligned.tex deleted file mode 100644 index e1f8c318..00000000 --- a/cheri/sail_latex/sailisAddressAligned.tex +++ /dev/null @@ -1 +0,0 @@ -val isAddressAligned : (#\hyperref[zbits]{bits}#(64), WordType) -> bool diff --git a/cheri/sail_latex/sailisnone.tex b/cheri/sail_latex/sailisnone.tex deleted file mode 100644 index 76688d37..00000000 --- a/cheri/sail_latex/sailisnone.tex +++ /dev/null @@ -1 +0,0 @@ -val is_none : forall ('a : Type). #\hyperref[zoption]{option}#('a) -> bool diff --git a/cheri/sail_latex/sailissome.tex b/cheri/sail_latex/sailissome.tex deleted file mode 100644 index 071ac6b6..00000000 --- a/cheri/sail_latex/sailissome.tex +++ /dev/null @@ -1 +0,0 @@ -val is_some : forall ('a : Type). #\hyperref[zoption]{option}#('a) -> bool diff --git a/cheri/sail_latex/saillength.tex b/cheri/sail_latex/saillength.tex deleted file mode 100644 index 248c8507..00000000 --- a/cheri/sail_latex/saillength.tex +++ /dev/null @@ -1 +0,0 @@ -overload length = {bitvector_length, vector_length}
\ No newline at end of file diff --git a/cheri/sail_latex/sailltatom.tex b/cheri/sail_latex/sailltatom.tex deleted file mode 100644 index 5cca54df..00000000 --- a/cheri/sail_latex/sailltatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_atom = {coq: "Z.ltb", _: "lt"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latex/sailltatomrange.tex b/cheri/sail_latex/sailltatomrange.tex deleted file mode 100644 index 19d3375d..00000000 --- a/cheri/sail_latex/sailltatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_atom_range = {coq: "ltb_range_r", _: "lt"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latex/saillteqatom.tex b/cheri/sail_latex/saillteqatom.tex deleted file mode 100644 index 26e27e2d..00000000 --- a/cheri/sail_latex/saillteqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_atom = {coq: "Z.leb", _: "lteq"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latex/saillteqatomrange.tex b/cheri/sail_latex/saillteqatomrange.tex deleted file mode 100644 index 6e951cf7..00000000 --- a/cheri/sail_latex/saillteqatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_atom_range = {coq: "leb_range_r", _: "lteq"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latex/saillteqint.tex b/cheri/sail_latex/saillteqint.tex deleted file mode 100644 index 555176be..00000000 --- a/cheri/sail_latex/saillteqint.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_int = {coq: "Z.leb", _:"lteq"} : (int, int) -> bool diff --git a/cheri/sail_latex/saillteqrangeatom.tex b/cheri/sail_latex/saillteqrangeatom.tex deleted file mode 100644 index f8fcd32d..00000000 --- a/cheri/sail_latex/saillteqrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_range_atom = {coq: "leb_range_l", _: "lteq"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latex/sailltint.tex b/cheri/sail_latex/sailltint.tex deleted file mode 100644 index 40bd4e85..00000000 --- a/cheri/sail_latex/sailltint.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_int = {coq: "Z.ltb", _:"lt"} : (int, int) -> bool diff --git a/cheri/sail_latex/sailltrangeatom.tex b/cheri/sail_latex/sailltrangeatom.tex deleted file mode 100644 index d8495496..00000000 --- a/cheri/sail_latex/sailltrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_range_atom = {coq: "ltb_range_l", _: "lt"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latex/sailmask.tex b/cheri/sail_latex/sailmask.tex deleted file mode 100644 index 35d052db..00000000 --- a/cheri/sail_latex/sailmask.tex +++ /dev/null @@ -1 +0,0 @@ -val mask : forall 'm 'n , 'm >= 'n > 0 . #\hyperref[zbits]{bits}#('m) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailmaxatom.tex b/cheri/sail_latex/sailmaxatom.tex deleted file mode 100644 index 6cbdfa7f..00000000 --- a/cheri/sail_latex/sailmaxatom.tex +++ /dev/null @@ -1 +0,0 @@ -val max_atom = {ocaml: "max_int", lem: "max", coq: "max_atom", c:"max_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c >= 'a & 'c >= 'b . atom('c)} diff --git a/cheri/sail_latex/sailmaxint.tex b/cheri/sail_latex/sailmaxint.tex deleted file mode 100644 index c537babb..00000000 --- a/cheri/sail_latex/sailmaxint.tex +++ /dev/null @@ -1 +0,0 @@ -val max_int = {lem: "max", coq: "Z.max", _: "max_int"} : (int, int) -> int diff --git a/cheri/sail_latex/sailmaxnat.tex b/cheri/sail_latex/sailmaxnat.tex deleted file mode 100644 index 1b62334a..00000000 --- a/cheri/sail_latex/sailmaxnat.tex +++ /dev/null @@ -1 +0,0 @@ -val max_nat = {lem: "max", coq: "Z.max", _: "max_int"} : (nat, nat) -> nat diff --git a/cheri/sail_latex/sailmemBitsToCapBits.tex b/cheri/sail_latex/sailmemBitsToCapBits.tex deleted file mode 100644 index 99aaa592..00000000 --- a/cheri/sail_latex/sailmemBitsToCapBits.tex +++ /dev/null @@ -1 +0,0 @@ -val memBitsToCapBits : (bool, bits(256)) -> bits(257) diff --git a/cheri/sail_latex/sailmin.tex b/cheri/sail_latex/sailmin.tex deleted file mode 100644 index 94097198..00000000 --- a/cheri/sail_latex/sailmin.tex +++ /dev/null @@ -1 +0,0 @@ -overload min = {min_atom, min_nat, min_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailminatom.tex b/cheri/sail_latex/sailminatom.tex deleted file mode 100644 index acfea384..00000000 --- a/cheri/sail_latex/sailminatom.tex +++ /dev/null @@ -1 +0,0 @@ -val min_atom = {ocaml: "min_int", lem: "min", coq: "min_atom", c:"min_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c <= 'a & 'c <= 'b . atom('c)} diff --git a/cheri/sail_latex/sailminint.tex b/cheri/sail_latex/sailminint.tex deleted file mode 100644 index 3d633d08..00000000 --- a/cheri/sail_latex/sailminint.tex +++ /dev/null @@ -1 +0,0 @@ -val min_int = {lem: "min", coq: "Z.min", _: "min_int"} : (int, int) -> int diff --git a/cheri/sail_latex/sailminnat.tex b/cheri/sail_latex/sailminnat.tex deleted file mode 100644 index 85409bd8..00000000 --- a/cheri/sail_latex/sailminnat.tex +++ /dev/null @@ -1 +0,0 @@ -val min_nat = {lem: "min", coq: "Z.min", _: "min_int"} : (nat, nat) -> nat diff --git a/cheri/sail_latex/sailmipssignextend.tex b/cheri/sail_latex/sailmipssignextend.tex deleted file mode 100644 index e613567d..00000000 --- a/cheri/sail_latex/sailmipssignextend.tex +++ /dev/null @@ -1 +0,0 @@ -val mips_sign_extend : forall 'n 'm , 'm >= 'n . #\hyperref[zbits]{bits}#('n) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latex/sailmipszzeroextend.tex b/cheri/sail_latex/sailmipszzeroextend.tex deleted file mode 100644 index adbb4188..00000000 --- a/cheri/sail_latex/sailmipszzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -val mips_zero_extend : forall 'n 'm , 'm >= 'n . #\hyperref[zbits]{bits}#('n) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latex/sailmod.tex b/cheri/sail_latex/sailmod.tex deleted file mode 100644 index ab70dd7a..00000000 --- a/cheri/sail_latex/sailmod.tex +++ /dev/null @@ -1,7 +0,0 @@ -val mod = { - smt: "mod", - ocaml: "modulus", - lem: "integerMod", - c: "tmod_int", - coq: "mod_with_eq" -} : forall 'n 'm. (atom('n), atom('m)) -> {'o, 'o = #\hyperref[zmod]{mod}#('n, 'm). atom('o)} diff --git a/cheri/sail_latex/sailmodBD.tex b/cheri/sail_latex/sailmodBD.tex deleted file mode 100644 index f3e58d9b..00000000 --- a/cheri/sail_latex/sailmodBD.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_BD = {_get_CauseReg_BD, _set_CauseReg_BD}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodBEV.tex b/cheri/sail_latex/sailmodBEV.tex deleted file mode 100644 index beee53c1..00000000 --- a/cheri/sail_latex/sailmodBEV.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_BEV = {_get_StatusReg_BEV, _set_StatusReg_BEV}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodBadVPNtwo.tex b/cheri/sail_latex/sailmodBadVPNtwo.tex deleted file mode 100644 index c2578121..00000000 --- a/cheri/sail_latex/sailmodBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_BadVPN2 = {_get_ContextReg_BadVPN2, _set_ContextReg_BadVPN2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodC.tex b/cheri/sail_latex/sailmodC.tex deleted file mode 100644 index 01df09e2..00000000 --- a/cheri/sail_latex/sailmodC.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_C = {_get_TLBEntryLoReg_C, _set_TLBEntryLoReg_C}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodCE.tex b/cheri/sail_latex/sailmodCE.tex deleted file mode 100644 index 9136541c..00000000 --- a/cheri/sail_latex/sailmodCE.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_CE = {_get_CauseReg_CE, _set_CauseReg_CE}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodCU.tex b/cheri/sail_latex/sailmodCU.tex deleted file mode 100644 index 2a2b7db3..00000000 --- a/cheri/sail_latex/sailmodCU.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_CU = {_get_StatusReg_CU, _set_StatusReg_CU}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodCapL.tex b/cheri/sail_latex/sailmodCapL.tex deleted file mode 100644 index 1e92b0d4..00000000 --- a/cheri/sail_latex/sailmodCapL.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_CapL = {_get_TLBEntryLoReg_CapL, _set_TLBEntryLoReg_CapL}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodCapS.tex b/cheri/sail_latex/sailmodCapS.tex deleted file mode 100644 index bdacef07..00000000 --- a/cheri/sail_latex/sailmodCapS.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_CapS = {_get_TLBEntryLoReg_CapS, _set_TLBEntryLoReg_CapS}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodD.tex b/cheri/sail_latex/sailmodD.tex deleted file mode 100644 index af4cad2e..00000000 --- a/cheri/sail_latex/sailmodD.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_D = {_get_TLBEntryLoReg_D, _set_TLBEntryLoReg_D}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodERL.tex b/cheri/sail_latex/sailmodERL.tex deleted file mode 100644 index b334b7dc..00000000 --- a/cheri/sail_latex/sailmodERL.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_ERL = {_get_StatusReg_ERL, _set_StatusReg_ERL}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodEXL.tex b/cheri/sail_latex/sailmodEXL.tex deleted file mode 100644 index 16b2bc8c..00000000 --- a/cheri/sail_latex/sailmodEXL.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_EXL = {_get_StatusReg_EXL, _set_StatusReg_EXL}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodExcCode.tex b/cheri/sail_latex/sailmodExcCode.tex deleted file mode 100644 index baa16ec2..00000000 --- a/cheri/sail_latex/sailmodExcCode.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_ExcCode = {_get_CapCauseReg_ExcCode, _set_CapCauseReg_ExcCode}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodIE.tex b/cheri/sail_latex/sailmodIE.tex deleted file mode 100644 index 940ad6f3..00000000 --- a/cheri/sail_latex/sailmodIE.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_IE = {_get_StatusReg_IE, _set_StatusReg_IE}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodIM.tex b/cheri/sail_latex/sailmodIM.tex deleted file mode 100644 index d3a58dd0..00000000 --- a/cheri/sail_latex/sailmodIM.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_IM = {_get_StatusReg_IM, _set_StatusReg_IM}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodIP.tex b/cheri/sail_latex/sailmodIP.tex deleted file mode 100644 index 361230bf..00000000 --- a/cheri/sail_latex/sailmodIP.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_IP = {_get_CauseReg_IP, _set_CauseReg_IP}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodIV.tex b/cheri/sail_latex/sailmodIV.tex deleted file mode 100644 index 1222520b..00000000 --- a/cheri/sail_latex/sailmodIV.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_IV = {_get_CauseReg_IV, _set_CauseReg_IV}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodKSU.tex b/cheri/sail_latex/sailmodKSU.tex deleted file mode 100644 index 7cff9a26..00000000 --- a/cheri/sail_latex/sailmodKSU.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_KSU = {_get_StatusReg_KSU, _set_StatusReg_KSU}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodKX.tex b/cheri/sail_latex/sailmodKX.tex deleted file mode 100644 index a90ad274..00000000 --- a/cheri/sail_latex/sailmodKX.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_KX = {_get_StatusReg_KX, _set_StatusReg_KX}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodPFN.tex b/cheri/sail_latex/sailmodPFN.tex deleted file mode 100644 index bba40f6d..00000000 --- a/cheri/sail_latex/sailmodPFN.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_PFN = {_get_TLBEntryLoReg_PFN, _set_TLBEntryLoReg_PFN}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodPTEBase.tex b/cheri/sail_latex/sailmodPTEBase.tex deleted file mode 100644 index 890eb57c..00000000 --- a/cheri/sail_latex/sailmodPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_PTEBase = {_get_ContextReg_PTEBase, _set_ContextReg_PTEBase}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodRegNum.tex b/cheri/sail_latex/sailmodRegNum.tex deleted file mode 100644 index 6cc28de3..00000000 --- a/cheri/sail_latex/sailmodRegNum.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_RegNum = {_get_CapCauseReg_RegNum, _set_CapCauseReg_RegNum}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodSX.tex b/cheri/sail_latex/sailmodSX.tex deleted file mode 100644 index 4ea62484..00000000 --- a/cheri/sail_latex/sailmodSX.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_SX = {_get_StatusReg_SX, _set_StatusReg_SX}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodUX.tex b/cheri/sail_latex/sailmodUX.tex deleted file mode 100644 index aa31242d..00000000 --- a/cheri/sail_latex/sailmodUX.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_UX = {_get_StatusReg_UX, _set_StatusReg_UX}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodV.tex b/cheri/sail_latex/sailmodV.tex deleted file mode 100644 index 964f5eab..00000000 --- a/cheri/sail_latex/sailmodV.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_V = {_get_TLBEntryLoReg_V, _set_TLBEntryLoReg_V}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodWP.tex b/cheri/sail_latex/sailmodWP.tex deleted file mode 100644 index 1ab7fbf7..00000000 --- a/cheri/sail_latex/sailmodWP.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_WP = {_get_CauseReg_WP, _set_CauseReg_WP}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodXBadVPNtwo.tex b/cheri/sail_latex/sailmodXBadVPNtwo.tex deleted file mode 100644 index 9122b39d..00000000 --- a/cheri/sail_latex/sailmodXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_XBadVPN2 = {_get_XContextReg_XBadVPN2, _set_XContextReg_XBadVPN2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodXPTEBase.tex b/cheri/sail_latex/sailmodXPTEBase.tex deleted file mode 100644 index 67e094bf..00000000 --- a/cheri/sail_latex/sailmodXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_XPTEBase = {_get_XContextReg_XPTEBase, _set_XContextReg_XPTEBase}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodXR.tex b/cheri/sail_latex/sailmodXR.tex deleted file mode 100644 index a3c5ab29..00000000 --- a/cheri/sail_latex/sailmodXR.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_XR = {_get_XContextReg_XR, _set_XContextReg_XR}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodasid.tex b/cheri/sail_latex/sailmodasid.tex deleted file mode 100644 index b80fbc05..00000000 --- a/cheri/sail_latex/sailmodasid.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_asid = {_get_TLBEntry_asid, _set_TLBEntry_asid}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodbits.tex b/cheri/sail_latex/sailmodbits.tex deleted file mode 100644 index b14554ac..00000000 --- a/cheri/sail_latex/sailmodbits.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_CapCauseReg_bits, _set_CapCauseReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodcaplone.tex b/cheri/sail_latex/sailmodcaplone.tex deleted file mode 100644 index cc216500..00000000 --- a/cheri/sail_latex/sailmodcaplone.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_capl1 = {_get_TLBEntry_capl1, _set_TLBEntry_capl1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodcaplzero.tex b/cheri/sail_latex/sailmodcaplzero.tex deleted file mode 100644 index 91969233..00000000 --- a/cheri/sail_latex/sailmodcaplzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_capl0 = {_get_TLBEntry_capl0, _set_TLBEntry_capl0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodcapsone.tex b/cheri/sail_latex/sailmodcapsone.tex deleted file mode 100644 index c2aa1743..00000000 --- a/cheri/sail_latex/sailmodcapsone.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_caps1 = {_get_TLBEntry_caps1, _set_TLBEntry_caps1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodcapszero.tex b/cheri/sail_latex/sailmodcapszero.tex deleted file mode 100644 index 36fbc5bb..00000000 --- a/cheri/sail_latex/sailmodcapszero.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_caps0 = {_get_TLBEntry_caps0, _set_TLBEntry_caps0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodcone.tex b/cheri/sail_latex/sailmodcone.tex deleted file mode 100644 index 70d2a78c..00000000 --- a/cheri/sail_latex/sailmodcone.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_c1 = {_get_TLBEntry_c1, _set_TLBEntry_c1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodczero.tex b/cheri/sail_latex/sailmodczero.tex deleted file mode 100644 index 56a19643..00000000 --- a/cheri/sail_latex/sailmodczero.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_c0 = {_get_TLBEntry_c0, _set_TLBEntry_c0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmoddone.tex b/cheri/sail_latex/sailmoddone.tex deleted file mode 100644 index d970eb5b..00000000 --- a/cheri/sail_latex/sailmoddone.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_d1 = {_get_TLBEntry_d1, _set_TLBEntry_d1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmoddzero.tex b/cheri/sail_latex/sailmoddzero.tex deleted file mode 100644 index 0e860884..00000000 --- a/cheri/sail_latex/sailmoddzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_d0 = {_get_TLBEntry_d0, _set_TLBEntry_d0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodg.tex b/cheri/sail_latex/sailmodg.tex deleted file mode 100644 index 6c46a49a..00000000 --- a/cheri/sail_latex/sailmodg.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_g = {_get_TLBEntry_g, _set_TLBEntry_g}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodint.tex b/cheri/sail_latex/sailmodint.tex deleted file mode 100644 index bd5677aa..00000000 --- a/cheri/sail_latex/sailmodint.tex +++ /dev/null @@ -1,7 +0,0 @@ -val mod_int = { - smt: "mod", - ocaml: "modulus", - lem: "integerMod", - c: "tmod_int", - coq: "Z.rem" -} : (int, int) -> int diff --git a/cheri/sail_latex/sailmodpagemask.tex b/cheri/sail_latex/sailmodpagemask.tex deleted file mode 100644 index 130ccab2..00000000 --- a/cheri/sail_latex/sailmodpagemask.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_pagemask = {_get_TLBEntry_pagemask, _set_TLBEntry_pagemask}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodpfnone.tex b/cheri/sail_latex/sailmodpfnone.tex deleted file mode 100644 index 3e703530..00000000 --- a/cheri/sail_latex/sailmodpfnone.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_pfn1 = {_get_TLBEntry_pfn1, _set_TLBEntry_pfn1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodpfnzero.tex b/cheri/sail_latex/sailmodpfnzero.tex deleted file mode 100644 index e3e2bfb2..00000000 --- a/cheri/sail_latex/sailmodpfnzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_pfn0 = {_get_TLBEntry_pfn0, _set_TLBEntry_pfn0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodr.tex b/cheri/sail_latex/sailmodr.tex deleted file mode 100644 index ca85fe92..00000000 --- a/cheri/sail_latex/sailmodr.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_r = {_get_TLBEntry_r, _set_TLBEntry_r}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodulus.tex b/cheri/sail_latex/sailmodulus.tex deleted file mode 100644 index ca23a339..00000000 --- a/cheri/sail_latex/sailmodulus.tex +++ /dev/null @@ -1 +0,0 @@ -val modulus = {ocaml: "modulus", lem: "hardware_mod", coq: "euclid_modulo", _ : "tmod_int"} : forall 'n, 'n > 0 . (int, atom('n)) -> range(0, 'n - 1) diff --git a/cheri/sail_latex/sailmodvalid.tex b/cheri/sail_latex/sailmodvalid.tex deleted file mode 100644 index 21baa26c..00000000 --- a/cheri/sail_latex/sailmodvalid.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_valid = {_get_TLBEntry_valid, _set_TLBEntry_valid}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodvone.tex b/cheri/sail_latex/sailmodvone.tex deleted file mode 100644 index 30619a05..00000000 --- a/cheri/sail_latex/sailmodvone.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_v1 = {_get_TLBEntry_v1, _set_TLBEntry_v1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodvpntwo.tex b/cheri/sail_latex/sailmodvpntwo.tex deleted file mode 100644 index 08cd1947..00000000 --- a/cheri/sail_latex/sailmodvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_vpn2 = {_get_TLBEntry_vpn2, _set_TLBEntry_vpn2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmodvzero.tex b/cheri/sail_latex/sailmodvzero.tex deleted file mode 100644 index 3e05b3f3..00000000 --- a/cheri/sail_latex/sailmodvzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_v0 = {_get_TLBEntry_v0, _set_TLBEntry_v0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailmultatom.tex b/cheri/sail_latex/sailmultatom.tex deleted file mode 100644 index bbac3e2f..00000000 --- a/cheri/sail_latex/sailmultatom.tex +++ /dev/null @@ -1,2 +0,0 @@ -val mult_atom = {ocaml: "mult", lem: "integerMult", c: "mult_int", coq: "Z.mul"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n * 'm) diff --git a/cheri/sail_latex/sailmultint.tex b/cheri/sail_latex/sailmultint.tex deleted file mode 100644 index 08698e6f..00000000 --- a/cheri/sail_latex/sailmultint.tex +++ /dev/null @@ -1 +0,0 @@ -val mult_int = {ocaml: "mult", lem: "integerMult", c: "mult_int", coq: "Z.mul"} : (int, int) -> int diff --git a/cheri/sail_latex/sailnegate.tex b/cheri/sail_latex/sailnegate.tex deleted file mode 100644 index ce000062..00000000 --- a/cheri/sail_latex/sailnegate.tex +++ /dev/null @@ -1 +0,0 @@ -overload negate = {negate_range, negate_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailnegateatom.tex b/cheri/sail_latex/sailnegateatom.tex deleted file mode 100644 index d1361e63..00000000 --- a/cheri/sail_latex/sailnegateatom.tex +++ /dev/null @@ -1 +0,0 @@ -val negate_atom = {ocaml: "negate", lem: "integerNegate", c: "neg_int", coq: "Z.opp"} : forall 'n. atom('n) -> atom(- 'n) diff --git a/cheri/sail_latex/sailnegateint.tex b/cheri/sail_latex/sailnegateint.tex deleted file mode 100644 index 52375787..00000000 --- a/cheri/sail_latex/sailnegateint.tex +++ /dev/null @@ -1 +0,0 @@ -val negate_int = {ocaml: "negate", lem: "integerNegate", c: "neg_int", coq: "Z.opp"} : int -> int diff --git a/cheri/sail_latex/sailnegaterange.tex b/cheri/sail_latex/sailnegaterange.tex deleted file mode 100644 index 7a4ad386..00000000 --- a/cheri/sail_latex/sailnegaterange.tex +++ /dev/null @@ -1 +0,0 @@ -val negate_range = {ocaml: "minus_big_int", lem: "integerNegate", coq: "negate_range"} : forall 'n 'm. range('n, 'm) -> range(- 'm, - 'n) diff --git a/cheri/sail_latex/sailneqanything.tex b/cheri/sail_latex/sailneqanything.tex deleted file mode 100644 index a898649e..00000000 --- a/cheri/sail_latex/sailneqanything.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_anything = {lem: "neq", coq: "generic_neq"} : forall ('a : Type). ('a, 'a) -> bool diff --git a/cheri/sail_latex/sailneqatom.tex b/cheri/sail_latex/sailneqatom.tex deleted file mode 100644 index be777013..00000000 --- a/cheri/sail_latex/sailneqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_atom = {lem: "neq", coq: "neq_atom"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latex/sailneqbool.tex b/cheri/sail_latex/sailneqbool.tex deleted file mode 100644 index 0d80dc17..00000000 --- a/cheri/sail_latex/sailneqbool.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_bool : (bool, bool) -> bool diff --git a/cheri/sail_latex/sailneqint.tex b/cheri/sail_latex/sailneqint.tex deleted file mode 100644 index b233ca6b..00000000 --- a/cheri/sail_latex/sailneqint.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_int = {lem: "neq"} : (int, int) -> bool diff --git a/cheri/sail_latex/sailneqrange.tex b/cheri/sail_latex/sailneqrange.tex deleted file mode 100644 index d2d8fb0c..00000000 --- a/cheri/sail_latex/sailneqrange.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_range = {lem: "neq"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool diff --git a/cheri/sail_latex/sailneqvec.tex b/cheri/sail_latex/sailneqvec.tex deleted file mode 100644 index f655b3d8..00000000 --- a/cheri/sail_latex/sailneqvec.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_vec = {lem: "neq"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latex/sailnot.tex b/cheri/sail_latex/sailnot.tex deleted file mode 100644 index 515b3ef9..00000000 --- a/cheri/sail_latex/sailnot.tex +++ /dev/null @@ -1 +0,0 @@ -val not = {coq:"negb", _:"not"} : bool -> bool diff --git a/cheri/sail_latex/sailnotbool.tex b/cheri/sail_latex/sailnotbool.tex deleted file mode 100644 index 7630f6c2..00000000 --- a/cheri/sail_latex/sailnotbool.tex +++ /dev/null @@ -1 +0,0 @@ -val not_bool = {coq: "negb", _: "not"} : bool -> bool diff --git a/cheri/sail_latex/sailnotvec.tex b/cheri/sail_latex/sailnotvec.tex deleted file mode 100644 index a560a544..00000000 --- a/cheri/sail_latex/sailnotvec.tex +++ /dev/null @@ -1 +0,0 @@ -val not_vec = {c:"not_bits", _:"not_vec"} : forall 'n. #\hyperref[zbits]{bits}#('n) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailnumofAccessLevel.tex b/cheri/sail_latex/sailnumofAccessLevel.tex deleted file mode 100644 index 0c618cc8..00000000 --- a/cheri/sail_latex/sailnumofAccessLevel.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_AccessLevel : AccessLevel -> {'e, 0 <= 'e & 'e <= 2. atom('e)} diff --git a/cheri/sail_latex/sailnumofCPtrCmpOp.tex b/cheri/sail_latex/sailnumofCPtrCmpOp.tex deleted file mode 100644 index 40f1bfa9..00000000 --- a/cheri/sail_latex/sailnumofCPtrCmpOp.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_CPtrCmpOp : CPtrCmpOp -> {'e, 0 <= 'e & 'e <= 7. atom('e)} diff --git a/cheri/sail_latex/sailnumofCapEx.tex b/cheri/sail_latex/sailnumofCapEx.tex deleted file mode 100644 index 3bec74dc..00000000 --- a/cheri/sail_latex/sailnumofCapEx.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_CapEx : CapEx -> {'e, 0 <= 'e & 'e <= 22. atom('e)} diff --git a/cheri/sail_latex/sailnumofClearRegSet.tex b/cheri/sail_latex/sailnumofClearRegSet.tex deleted file mode 100644 index 14ea7bea..00000000 --- a/cheri/sail_latex/sailnumofClearRegSet.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_ClearRegSet : ClearRegSet -> {'e, 0 <= 'e & 'e <= 3. atom('e)} diff --git a/cheri/sail_latex/sailnumofComparison.tex b/cheri/sail_latex/sailnumofComparison.tex deleted file mode 100644 index bac8031f..00000000 --- a/cheri/sail_latex/sailnumofComparison.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_Comparison : Comparison -> {'e, 0 <= 'e & 'e <= 7. atom('e)} diff --git a/cheri/sail_latex/sailnumofException.tex b/cheri/sail_latex/sailnumofException.tex deleted file mode 100644 index 2f823724..00000000 --- a/cheri/sail_latex/sailnumofException.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_Exception : Exception -> {'e, 0 <= 'e & 'e <= 18. atom('e)} diff --git a/cheri/sail_latex/sailnumofMemAccessType.tex b/cheri/sail_latex/sailnumofMemAccessType.tex deleted file mode 100644 index dc81a81c..00000000 --- a/cheri/sail_latex/sailnumofMemAccessType.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_MemAccessType : MemAccessType -> {'e, 0 <= 'e & 'e <= 2. atom('e)} diff --git a/cheri/sail_latex/sailnumofWordType.tex b/cheri/sail_latex/sailnumofWordType.tex deleted file mode 100644 index 2be61446..00000000 --- a/cheri/sail_latex/sailnumofWordType.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_WordType : WordType -> {'e, 0 <= 'e & 'e <= 3. atom('e)} diff --git a/cheri/sail_latex/sailnumofWordTypeUnaligned.tex b/cheri/sail_latex/sailnumofWordTypeUnaligned.tex deleted file mode 100644 index 40c9a426..00000000 --- a/cheri/sail_latex/sailnumofWordTypeUnaligned.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_WordTypeUnaligned : WordTypeUnaligned -> {'e, 0 <= 'e & 'e <= 3. atom('e)} diff --git a/cheri/sail_latex/sailnumofdecodefailure.tex b/cheri/sail_latex/sailnumofdecodefailure.tex deleted file mode 100644 index 197b4ae9..00000000 --- a/cheri/sail_latex/sailnumofdecodefailure.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_decode_failure : decode_failure -> {'e, 0 <= 'e & 'e <= 3. atom('e)} diff --git a/cheri/sail_latex/sailones.tex b/cheri/sail_latex/sailones.tex deleted file mode 100644 index 94fd805f..00000000 --- a/cheri/sail_latex/sailones.tex +++ /dev/null @@ -1 +0,0 @@ -val ones : forall 'n, 'n >= 0 . unit -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailorbits.tex b/cheri/sail_latex/sailorbits.tex deleted file mode 100644 index 55db5ffa..00000000 --- a/cheri/sail_latex/sailorbits.tex +++ /dev/null @@ -1 +0,0 @@ -val or_bits = {c: "or_bits", _: "or_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailorbool.tex b/cheri/sail_latex/sailorbool.tex deleted file mode 100644 index 4b6bfa15..00000000 --- a/cheri/sail_latex/sailorbool.tex +++ /dev/null @@ -1 +0,0 @@ -val or_bool = {coq: "orb", _: "or_bool"} : (bool, bool) -> bool diff --git a/cheri/sail_latex/sailpccaccesssystemregs.tex b/cheri/sail_latex/sailpccaccesssystemregs.tex deleted file mode 100644 index 399ab221..00000000 --- a/cheri/sail_latex/sailpccaccesssystemregs.tex +++ /dev/null @@ -1 +0,0 @@ -val pcc_access_system_regs : unit -> bool effect {rreg} diff --git a/cheri/sail_latex/sailplainvectoraccess.tex b/cheri/sail_latex/sailplainvectoraccess.tex deleted file mode 100644 index 94824f77..00000000 --- a/cheri/sail_latex/sailplainvectoraccess.tex +++ /dev/null @@ -1,6 +0,0 @@ -val plain_vector_access = { - ocaml: "access", - lem: "access_list_dec", - coq: "vec_access_dec", - c: "vector_access" -} : forall ('n : Int) ('m : Int) ('a : Type), 0 <= 'm < 'n. (vector('n, dec, 'a), atom('m)) -> 'a diff --git a/cheri/sail_latex/sailplainvectorupdate.tex b/cheri/sail_latex/sailplainvectorupdate.tex deleted file mode 100644 index 6880d9bd..00000000 --- a/cheri/sail_latex/sailplainvectorupdate.tex +++ /dev/null @@ -1,6 +0,0 @@ -val plain_vector_update = { - ocaml: "update", - lem: "update_list_dec", - coq: "vec_update_dec", - c: "vector_update" -} : forall '#\hyperref[zn]{n}# ('a : Type). (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a) diff --git a/cheri/sail_latex/sailpowtwo.tex b/cheri/sail_latex/sailpowtwo.tex deleted file mode 100644 index 41da946e..00000000 --- a/cheri/sail_latex/sailpowtwo.tex +++ /dev/null @@ -1 +0,0 @@ -val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n) diff --git a/cheri/sail_latex/sailprerrbits.tex b/cheri/sail_latex/sailprerrbits.tex deleted file mode 100644 index 7d926384..00000000 --- a/cheri/sail_latex/sailprerrbits.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_bits" : forall 'n. (string, #\hyperref[zbits]{bits}#('n)) -> unit diff --git a/cheri/sail_latex/sailprerrendline.tex b/cheri/sail_latex/sailprerrendline.tex deleted file mode 100644 index ad4a94a0..00000000 --- a/cheri/sail_latex/sailprerrendline.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_endline" : string -> unit diff --git a/cheri/sail_latex/sailprerrint.tex b/cheri/sail_latex/sailprerrint.tex deleted file mode 100644 index ce7a7d61..00000000 --- a/cheri/sail_latex/sailprerrint.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_int" : (string, int) -> unit diff --git a/cheri/sail_latex/sailprerrstring.tex b/cheri/sail_latex/sailprerrstring.tex deleted file mode 100644 index 7b849da2..00000000 --- a/cheri/sail_latex/sailprerrstring.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_string" : string -> unit diff --git a/cheri/sail_latex/sailprint.tex b/cheri/sail_latex/sailprint.tex deleted file mode 100644 index 50a64219..00000000 --- a/cheri/sail_latex/sailprint.tex +++ /dev/null @@ -1 +0,0 @@ -val print = "print_endline" : string -> unit diff --git a/cheri/sail_latex/sailprintbits.tex b/cheri/sail_latex/sailprintbits.tex deleted file mode 100644 index 8783a59a..00000000 --- a/cheri/sail_latex/sailprintbits.tex +++ /dev/null @@ -1 +0,0 @@ -val "print_bits" : forall 'n. (string, #\hyperref[zbits]{bits}#('n)) -> unit diff --git a/cheri/sail_latex/sailprintint.tex b/cheri/sail_latex/sailprintint.tex deleted file mode 100644 index ddf33afc..00000000 --- a/cheri/sail_latex/sailprintint.tex +++ /dev/null @@ -1 +0,0 @@ -val "print_int" : (string, int) -> unit diff --git a/cheri/sail_latex/sailputchar.tex b/cheri/sail_latex/sailputchar.tex deleted file mode 100644 index a123c709..00000000 --- a/cheri/sail_latex/sailputchar.tex +++ /dev/null @@ -1 +0,0 @@ -val putchar = {c:"sail_putchar", _:"putchar"} : int -> unit diff --git a/cheri/sail_latex/sailquotient.tex b/cheri/sail_latex/sailquotient.tex deleted file mode 100644 index 7dba5359..00000000 --- a/cheri/sail_latex/sailquotient.tex +++ /dev/null @@ -1 +0,0 @@ -val quotient = {ocaml: "quotient", lem: "integerDiv", coq: "Z.mod"} : (int, int) -> int diff --git a/cheri/sail_latex/sailquotientnat.tex b/cheri/sail_latex/sailquotientnat.tex deleted file mode 100644 index 14db4ae0..00000000 --- a/cheri/sail_latex/sailquotientnat.tex +++ /dev/null @@ -1 +0,0 @@ -val quotient_nat = {ocaml: "quotient", lem: "integerDiv", coq: "Z.div"} : (nat, nat) -> nat diff --git a/cheri/sail_latex/sailquotroundzzero.tex b/cheri/sail_latex/sailquotroundzzero.tex deleted file mode 100644 index 9523cfcc..00000000 --- a/cheri/sail_latex/sailquotroundzzero.tex +++ /dev/null @@ -1 +0,0 @@ -val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot", coq: "Z.quot", _ : "tdiv_int"} : (int, int) -> int diff --git a/cheri/sail_latex/sailrGPR.tex b/cheri/sail_latex/sailrGPR.tex deleted file mode 100644 index 19721488..00000000 --- a/cheri/sail_latex/sailrGPR.tex +++ /dev/null @@ -1 +0,0 @@ -val rGPR : #\hyperref[zbits]{bits}#(5) -> #\hyperref[zbits]{bits}#(64) effect {rreg} diff --git a/cheri/sail_latex/sailraisectwoexception.tex b/cheri/sail_latex/sailraisectwoexception.tex deleted file mode 100644 index f8a562ec..00000000 --- a/cheri/sail_latex/sailraisectwoexception.tex +++ /dev/null @@ -1 +0,0 @@ -val raise_c2_exception : forall ('o : Type) . (CapEx, regno) -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailraisectwoexceptioneight.tex b/cheri/sail_latex/sailraisectwoexceptioneight.tex deleted file mode 100644 index 21b0bcf9..00000000 --- a/cheri/sail_latex/sailraisectwoexceptioneight.tex +++ /dev/null @@ -1 +0,0 @@ -val raise_c2_exception8 : forall ('o : Type) . (CapEx, #\hyperref[zbits]{bits}#(8)) -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailraisectwoexceptionnoreg.tex b/cheri/sail_latex/sailraisectwoexceptionnoreg.tex deleted file mode 100644 index be594e4e..00000000 --- a/cheri/sail_latex/sailraisectwoexceptionnoreg.tex +++ /dev/null @@ -1 +0,0 @@ -val raise_c2_exception_noreg : forall ('o : Type) . (CapEx) -> 'o effect {escape, rreg, wreg} diff --git a/cheri/sail_latex/sailreadCapReg.tex b/cheri/sail_latex/sailreadCapReg.tex deleted file mode 100644 index f4d77264..00000000 --- a/cheri/sail_latex/sailreadCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -val readCapReg : regno -> CapStruct effect {rreg} diff --git a/cheri/sail_latex/sailreadCapRegDDC.tex b/cheri/sail_latex/sailreadCapRegDDC.tex deleted file mode 100644 index 2ec2e75d..00000000 --- a/cheri/sail_latex/sailreadCapRegDDC.tex +++ /dev/null @@ -1 +0,0 @@ -val readCapRegDDC : regno -> CapStruct effect {rreg} diff --git a/cheri/sail_latex/sailregderef.tex b/cheri/sail_latex/sailregderef.tex deleted file mode 100644 index 7f1dc7e8..00000000 --- a/cheri/sail_latex/sailregderef.tex +++ /dev/null @@ -1 +0,0 @@ -val _reg_deref = "reg_deref" : forall ('a : Type). #\hyperref[zregister]{register}#('a) -> 'a diff --git a/cheri/sail_latex/sailregisterinaccessible.tex b/cheri/sail_latex/sailregisterinaccessible.tex deleted file mode 100644 index d732248a..00000000 --- a/cheri/sail_latex/sailregisterinaccessible.tex +++ /dev/null @@ -1 +0,0 @@ -val register_inaccessible : regno -> bool effect {rreg} diff --git a/cheri/sail_latex/sailregno.tex b/cheri/sail_latex/sailregno.tex deleted file mode 100644 index 5246f847..00000000 --- a/cheri/sail_latex/sailregno.tex +++ /dev/null @@ -1 +0,0 @@ -type regno = #\hyperref[zbits]{bits}#(5) /* a register number */ diff --git a/cheri/sail_latex/sailregregimmonesix.tex b/cheri/sail_latex/sailregregimmonesix.tex deleted file mode 100644 index 0be3ccec..00000000 --- a/cheri/sail_latex/sailregregimmonesix.tex +++ /dev/null @@ -1 +0,0 @@ -type regregimm16 = (regno, regno, imm16) diff --git a/cheri/sail_latex/sailregregreg.tex b/cheri/sail_latex/sailregregreg.tex deleted file mode 100644 index e3409dff..00000000 --- a/cheri/sail_latex/sailregregreg.tex +++ /dev/null @@ -1 +0,0 @@ -type regregreg = (regno, regno, regno) diff --git a/cheri/sail_latex/sailremroundzzero.tex b/cheri/sail_latex/sailremroundzzero.tex deleted file mode 100644 index 9d8113ba..00000000 --- a/cheri/sail_latex/sailremroundzzero.tex +++ /dev/null @@ -1 +0,0 @@ -val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod", coq: "Z.rem", _ : "tmod_int"} : (int, int) -> int diff --git a/cheri/sail_latex/sailreplicatebits.tex b/cheri/sail_latex/sailreplicatebits.tex deleted file mode 100644 index cd7a97d7..00000000 --- a/cheri/sail_latex/sailreplicatebits.tex +++ /dev/null @@ -1 +0,0 @@ -val replicate_bits = "replicate_bits" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('n * 'm) diff --git a/cheri/sail_latex/sailreverseendianness.tex b/cheri/sail_latex/sailreverseendianness.tex deleted file mode 100644 index 9105738f..00000000 --- a/cheri/sail_latex/sailreverseendianness.tex +++ /dev/null @@ -1 +0,0 @@ -val reverse_endianness = "reverse_endianness" : forall 'W, 'W >= 1. #\hyperref[zbits]{bits}#(8 * 'W) -> #\hyperref[zbits]{bits}#(8 * 'W) effect pure diff --git a/cheri/sail_latex/sailsailfndecodeSomeBCMPZv.tex b/cheri/sail_latex/sailsailfndecodeSomeBCMPZv.tex deleted file mode 100644 index 5106d2ec..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeBCMPZv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b10000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, LT, true, false)) /* BLTZAL */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeBEQv.tex b/cheri/sail_latex/sailsailfndecodeSomeBEQv.tex deleted file mode 100644 index aa31ba6b..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeBEQv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010100 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBEQ]{BEQ}#(rs, rt, imm, false, true)) /* BEQL */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCAndPermv.tex b/cheri/sail_latex/sailsailfndecodeSomeCAndPermv.tex deleted file mode 100644 index 893a1c6d..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCAndPermv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001101) = #\hyperref[zSome]{Some}#(#\hyperref[zCAndPerm]{CAndPerm}#(cd, cs, rt)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCBXv.tex b/cheri/sail_latex/sailsailfndecodeSomeCBXv.tex deleted file mode 100644 index 32d3c875..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCBXv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01010 @ cd : regno @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zCBX]{CBX}#(cd, imm, false)) /* CBTS */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCBZv.tex b/cheri/sail_latex/sailsailfndecodeSomeCBZv.tex deleted file mode 100644 index 32781f76..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCBZv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10010 @ cd : regno @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zCBZ]{CBZ}#(cd, imm, true)) /* CBNZ */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCCheckPermv.tex b/cheri/sail_latex/sailsailfndecodeSomeCCheckPermv.tex deleted file mode 100644 index ee2c8bde..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCCheckPermv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cs : regno @ rt : regno @ 0b01000 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCCheckPerm]{CCheckPerm}#(cs, rt)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCCheckTypev.tex b/cheri/sail_latex/sailsailfndecodeSomeCCheckTypev.tex deleted file mode 100644 index 661760cc..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCCheckTypev.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cs : regno @ cb : regno @ 0b01001 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCCheckType]{CCheckType}#(cs, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCClearTagv.tex b/cheri/sail_latex/sailsailfndecodeSomeCClearTagv.tex deleted file mode 100644 index 766ce399..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCClearTagv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ 0b01011 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCClearTag]{CClearTag}#(cd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCFromPtrv.tex b/cheri/sail_latex/sailsailfndecodeSomeCFromPtrv.tex deleted file mode 100644 index e977fcd2..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCFromPtrv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ rs : regno @ 0b010011) = #\hyperref[zSome]{Some}#(#\hyperref[zCFromPtr]{CFromPtr}#(cd, cb, rs)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetBasev.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetBasev.tex deleted file mode 100644 index 05fa9835..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetBasev.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00010 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetBase]{CGetBase}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetCauserdv.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetCauserdv.tex deleted file mode 100644 index c44fd7ff..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetCauserdv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ 0b00001 @ 0b11111 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetCause]{CGetCause}#(rd)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetLenv.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetLenv.tex deleted file mode 100644 index 3a4a434b..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetLenv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00011 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetLen]{CGetLen}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetOffsetv.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetOffsetv.tex deleted file mode 100644 index a5a22beb..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetOffsetv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00110 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetOffset]{CGetOffset}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetPermv.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetPermv.tex deleted file mode 100644 index 5dbabd98..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetPermv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00000 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetPerm]{CGetPerm}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetSealedv.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetSealedv.tex deleted file mode 100644 index 00d254ad..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetSealedv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00101 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetSealed]{CGetSealed}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetTagv.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetTagv.tex deleted file mode 100644 index e46392b5..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetTagv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00100 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetTag]{CGetTag}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCGetTypev.tex b/cheri/sail_latex/sailsailfndecodeSomeCGetTypev.tex deleted file mode 100644 index 20baf29c..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCGetTypev.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ 0b00001 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCGetType]{CGetType}#(rd, cb)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCIncOffsetv.tex b/cheri/sail_latex/sailsailfndecodeSomeCIncOffsetv.tex deleted file mode 100644 index 5d2501bb..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCIncOffsetv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ rt : regno @ 0b010001) = #\hyperref[zSome]{Some}#(#\hyperref[zCIncOffset]{CIncOffset}#(cd, cb, rt)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCJALRv.tex b/cheri/sail_latex/sailsailfndecodeSomeCJALRv.tex deleted file mode 100644 index 3f5f8411..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCJALRv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01000 @ 0b00000 @ cb : regno @ 0b00000 @ 0b000000) = #\hyperref[zSome]{Some}#(#\hyperref[zCJALR]{CJALR}#(0b00000, cb, false)) /* CJR */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCLCv.tex b/cheri/sail_latex/sailsailfndecodeSomeCLCv.tex deleted file mode 100644 index fa732648..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCLCv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ cd : regno @ cb : regno@ 0b0000000 @ 0b1111) = #\hyperref[zSome]{Some}#(#\hyperref[zCLC]{CLC}#(cd, cb, 0b00000, 0x0000, true)) /* CLLC */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCLoadv.tex b/cheri/sail_latex/sailsailfndecodeSomeCLoadv.tex deleted file mode 100644 index 9fbd4a7b..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCLoadv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b1 @ 0b00) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, true, B, false)) /* CLB */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCMOVXv.tex b/cheri/sail_latex/sailsailfndecodeSomeCMOVXv.tex deleted file mode 100644 index 09fb371f..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCMOVXv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rs : regno @ 0b011011) = #\hyperref[zSome]{Some}#(#\hyperref[zCMOVX]{CMOVX}#(cd, cs, rs, false)) /* CMOVZ */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCPtrCmpv.tex b/cheri/sail_latex/sailsailfndecodeSomeCPtrCmpv.tex deleted file mode 100644 index af60dcc8..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCPtrCmpv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b001) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CNE)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCReturnv.tex b/cheri/sail_latex/sailsailfndecodeSomeCReturnv.tex deleted file mode 100644 index da0a09d2..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCReturnv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00101 @ 0b00000 @ 0b00000 @ 0b11111111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCReturn]{CReturn}#()) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCSCv.tex b/cheri/sail_latex/sailsailfndecodeSomeCSCv.tex deleted file mode 100644 index 14b9e73a..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCSCv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ cs : regno @ cb : regno@ rd : regno @ 0b00 @ 0b0111) = #\hyperref[zSome]{Some}#(#\hyperref[zCSC]{CSC}#(cs, cb, 0b00000, rd, 0b00000000000, true)) /* CSCC */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCSealv.tex b/cheri/sail_latex/sailsailfndecodeSomeCSealv.tex deleted file mode 100644 index 4000c397..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCSealv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ ct : regno @ 0b001011) = #\hyperref[zSome]{Some}#(#\hyperref[zCSeal]{CSeal}#(cd, cs, ct)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCSetBoundsv.tex b/cheri/sail_latex/sailsailfndecodeSomeCSetBoundsv.tex deleted file mode 100644 index 1d6a4e52..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCSetBoundsv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001000) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetBounds]{CSetBounds}#(cd, cs, rt)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCSetOffsetv.tex b/cheri/sail_latex/sailsailfndecodeSomeCSetOffsetv.tex deleted file mode 100644 index 478a8f93..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCSetOffsetv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rt : regno @ 0b001111) = #\hyperref[zSome]{Some}#(#\hyperref[zCSetOffset]{CSetOffset}#(cd, cs, rt)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCStorev.tex b/cheri/sail_latex/sailsailfndecodeSomeCStorev.tex deleted file mode 100644 index e5e4dd1d..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCStorev.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b01) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, rt, 0b00000, offset, H, false)) /* CSH */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeCToPtrv.tex b/cheri/sail_latex/sailsailfndecodeSomeCToPtrv.tex deleted file mode 100644 index d9b325f9..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCToPtrv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ ct : regno @ 0b010010) = #\hyperref[zSome]{Some}#(#\hyperref[zCToPtr]{CToPtr}#(rd, cb, ct)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeCUnsealv.tex b/cheri/sail_latex/sailsailfndecodeSomeCUnsealv.tex deleted file mode 100644 index acb3c721..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeCUnsealv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ ct : regno @ 0b001100) = #\hyperref[zSome]{Some}#(#\hyperref[zCUnseal]{CUnseal}#(cd, cs, ct)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeClearRegsv.tex b/cheri/sail_latex/sailsailfndecodeSomeClearRegsv.tex deleted file mode 100644 index 791485cd..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeClearRegsv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01111 @ 0b00001 @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zClearRegs]{ClearRegs}#(GPHi, imm)) diff --git a/cheri/sail_latex/sailsailfndecodeSomeHCFv.tex b/cheri/sail_latex/sailsailfndecodeSomeHCFv.tex deleted file mode 100644 index dbecd8da..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeHCFv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b00100 @ rt : regno @ 0b11010 @ 0b00000000000) = - #\hyperref[zSome]{Some}#(#\hyperref[zHCF]{HCF}#()) diff --git a/cheri/sail_latex/sailsailfndecodeSomeLoadv.tex b/cheri/sail_latex/sailsailfndecodeSomeLoadv.tex deleted file mode 100644 index 211a2f4a..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeLoadv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b100100 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(B, false, false, base, rt, offset)) /* LBU */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeMFCzerov.tex b/cheri/sail_latex/sailsailfndecodeSomeMFCzerov.tex deleted file mode 100644 index f54ffdfd..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeMFCzerov.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b00001 @ rt : regno @ rd : regno @ 0b00000000 @ sel : #\hyperref[zbits]{bits}#(3)) = - #\hyperref[zSome]{Some}#(#\hyperref[zMFCzero]{MFC0}#(rt, rd, sel, true)) /* DMFC0 */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeMTCzerov.tex b/cheri/sail_latex/sailsailfndecodeSomeMTCzerov.tex deleted file mode 100644 index ae848c1e..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeMTCzerov.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b00101 @ rt : regno @ rd : regno @ 0b00000000 @ sel : #\hyperref[zbits]{bits}#(3)) = - #\hyperref[zSome]{Some}#(#\hyperref[zMTCzero]{MTC0}#(rt, rd, sel, true)) /* DMTC0 */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeStorev.tex b/cheri/sail_latex/sailsailfndecodeSomeStorev.tex deleted file mode 100644 index 6ddb5562..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeStorev.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b101001 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zStore]{Store}#(H, false, base, rt, offset)) /* SH */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeTRAPIMMv.tex b/cheri/sail_latex/sailsailfndecodeSomeTRAPIMMv.tex deleted file mode 100644 index f899f0e7..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeTRAPIMMv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b01110 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, NE)) /* TNEI */ diff --git a/cheri/sail_latex/sailsailfndecodeSomeTRAPREGv.tex b/cheri/sail_latex/sailsailfndecodeSomeTRAPREGv.tex deleted file mode 100644 index 9909d5da..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomeTRAPREGv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ code : #\hyperref[zbits]{bits}#(10) @ 0b110001) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, GEU)) /* TGEU */ diff --git a/cheri/sail_latex/sailsailfndecodeSomev.tex b/cheri/sail_latex/sailsailfndecodeSomev.tex deleted file mode 100644 index bf842c52..00000000 --- a/cheri/sail_latex/sailsailfndecodeSomev.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b10000000000000000000 @ 0b000110) = #\hyperref[zSome]{Some}#(#\hyperref[zTLBWR]{TLBWR}#() : ast) diff --git a/cheri/sail_latex/sailsailfnexecuteCCallv.tex b/cheri/sail_latex/sailsailfnexecuteCCallv.tex deleted file mode 100644 index 6a11ddac..00000000 --- a/cheri/sail_latex/sailsailfnexecuteCCallv.tex +++ /dev/null @@ -1,46 +0,0 @@ -function clause #\hyperref[zexecute]{execute}# (#\hyperref[zCCall]{CCall}#(cs, cb, 0b00000000001)) = /* selector=1 */ -{ - /* Jump-like implementation of CCall that unseals arguments */ - #\hyperref[zcheckCPtwousable]{checkCP2usable}#(); - cs_val = #\hyperref[zreadCapReg]{readCapReg}#(cs); - cb_val = #\hyperref[zreadCapReg]{readCapReg}#(cb); - cs_cursor = #\hyperref[zgetCapCursor]{getCapCursor}#(cs_val); - if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cs)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cs) - else if (#\hyperref[zregisterzyinaccessible]{register\_inaccessible}#(cb)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.tag) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.sealed) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) - else if ((cs_val.otype) != (cb_val.otype)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) - else if #\hyperref[znot]{not}# (cs_val.permit_ccall) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitCCallViolation, cs) - else if #\hyperref[znot]{not}# (cb_val.permit_ccall) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitCCallViolation, cb) - else if #\hyperref[znot]{not}# (cs_val.permit_execute) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cs) - else if (cb_val.permit_execute) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cb) - else if (cs_cursor < #\hyperref[zgetCapBase]{getCapBase}#(cs_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) - else if (cs_cursor >= #\hyperref[zgetCapTop]{getCapTop}#(cs_val)) then - #\hyperref[zraisezyctwozyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) - else - { - #\hyperref[zexecutezybranchzypcc]{execute\_branch\_pcc}#({cs_val with - sealed=false, - otype=#\hyperref[zzzeros]{zeros}#() - }); - inCCallDelay = 0b1; - C26 = #\hyperref[zcapStructToCapReg]{capStructToCapReg}#({cb_val with - sealed=false, - otype=#\hyperref[zzzeros]{zeros}#() - }); - } -} diff --git a/cheri/sail_latex/sailsailmask.tex b/cheri/sail_latex/sailsailmask.tex deleted file mode 100644 index 45862747..00000000 --- a/cheri/sail_latex/sailsailmask.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_mask : forall 'len 'v, 'len >= 0 & 'v >= 0. (atom('len), vector('v, dec, bit)) -> vector('len, dec, bit) diff --git a/cheri/sail_latex/sailsailmaxv.tex b/cheri/sail_latex/sailsailmaxv.tex deleted file mode 100644 index 1ceed42c..00000000 --- a/cheri/sail_latex/sailsailmaxv.tex +++ /dev/null @@ -1 +0,0 @@ -overload max = {max_atom, max_nat, max_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailmodASIDv.tex b/cheri/sail_latex/sailsailmodASIDv.tex deleted file mode 100644 index 4e4c154c..00000000 --- a/cheri/sail_latex/sailsailmodASIDv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_ASID = {_get_TLBEntryHiReg_ASID, _set_TLBEntryHiReg_ASID}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailmodExcCodev.tex b/cheri/sail_latex/sailsailmodExcCodev.tex deleted file mode 100644 index 95bd4a1b..00000000 --- a/cheri/sail_latex/sailsailmodExcCodev.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_ExcCode = {_get_CauseReg_ExcCode, _set_CauseReg_ExcCode}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailmodGv.tex b/cheri/sail_latex/sailsailmodGv.tex deleted file mode 100644 index ddb88eaa..00000000 --- a/cheri/sail_latex/sailsailmodGv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_G = {_get_TLBEntryLoReg_G, _set_TLBEntryLoReg_G}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailmodRv.tex b/cheri/sail_latex/sailsailmodRv.tex deleted file mode 100644 index 85ef85fa..00000000 --- a/cheri/sail_latex/sailsailmodRv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_R = {_get_TLBEntryHiReg_R, _set_TLBEntryHiReg_R}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailmodVPNtwov.tex b/cheri/sail_latex/sailsailmodVPNtwov.tex deleted file mode 100644 index 7de971a8..00000000 --- a/cheri/sail_latex/sailsailmodVPNtwov.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_VPN2 = {_get_TLBEntryHiReg_VPN2, _set_TLBEntryHiReg_VPN2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailmodbitsv.tex b/cheri/sail_latex/sailsailmodbitsv.tex deleted file mode 100644 index f27daebb..00000000 --- a/cheri/sail_latex/sailsailmodbitsv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_StatusReg_bits, _set_StatusReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailnegatev.tex b/cheri/sail_latex/sailsailnegatev.tex deleted file mode 100644 index 4f7aea58..00000000 --- a/cheri/sail_latex/sailsailnegatev.tex +++ /dev/null @@ -1 +0,0 @@ -overload negate = {negate_atom, negate_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailregderefv.tex b/cheri/sail_latex/sailsailregderefv.tex deleted file mode 100644 index f5de92ca..00000000 --- a/cheri/sail_latex/sailsailregderefv.tex +++ /dev/null @@ -1 +0,0 @@ -val "reg_deref" : forall ('a : Type). #\hyperref[zregister]{register}#('a) -> 'a effect {rreg} diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeBCMPZvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeBCMPZvv.tex deleted file mode 100644 index 05919c54..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeBCMPZvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b00010 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, LT, false, true)) /* BLTZL */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeBEQvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeBEQvv.tex deleted file mode 100644 index 4ee94638..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeBEQvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000101 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBEQ]{BEQ}#(rs, rt, imm, true , false)) /* BNE */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeCJALRvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeCJALRvv.tex deleted file mode 100644 index a14bda16..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeCJALRvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cb : regno @ 0b00011 @ 0b11111 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCJALR]{CJALR}#(0b00000, cb, false)) /* CJR */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeCLCvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeCLCvv.tex deleted file mode 100644 index ec1bbddb..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeCLCvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b011101 @ cd : regno @ cb : regno @ offset : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zCLC]{CLC}#(cd, cb, 0b00000, offset, false)) /* CLCBI */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeCLoadvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeCLoadvv.tex deleted file mode 100644 index 59928bdf..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeCLoadvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b01) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, false, H, false)) /* CLHU */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeCMOVXvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeCMOVXvv.tex deleted file mode 100644 index 17ed8e64..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeCMOVXvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cs : regno @ rs : regno @ 0b011100) = #\hyperref[zSome]{Some}#(#\hyperref[zCMOVX]{CMOVX}#(cd, cs, rs, true)) /* CMOVN */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeCPtrCmpvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeCPtrCmpvv.tex deleted file mode 100644 index e89b161e..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeCPtrCmpvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b010) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLT)) diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeCStorevv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeCStorevv.tex deleted file mode 100644 index 16a0ca69..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeCStorevv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b10) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, rt, 0b00000, offset, W, false)) /* CSW */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeClearRegsvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeClearRegsvv.tex deleted file mode 100644 index 1f6face1..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeClearRegsvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01111 @ 0b00010 @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zClearRegs]{ClearRegs}#(CLo, imm)) diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeLoadvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeLoadvv.tex deleted file mode 100644 index 9158cc9a..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeLoadvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b100001 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(H, true, false, base, rt, offset)) /* LH */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeStorevv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeStorevv.tex deleted file mode 100644 index f71ec6a1..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeStorevv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b101011 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zStore]{Store}#(W, false, base, rt, offset)) /* SW */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeTRAPIMMvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeTRAPIMMvv.tex deleted file mode 100644 index 39d26d09..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeTRAPIMMvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b01000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, GE)) /* TGEI */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomeTRAPREGvv.tex b/cheri/sail_latex/sailsailsailfndecodeSomeTRAPREGvv.tex deleted file mode 100644 index 69135618..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomeTRAPREGvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ code : #\hyperref[zbits]{bits}#(10) @ 0b110010) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, LT)) /* TLT */ diff --git a/cheri/sail_latex/sailsailsailfndecodeSomevv.tex b/cheri/sail_latex/sailsailsailfndecodeSomevv.tex deleted file mode 100644 index 30e900f1..00000000 --- a/cheri/sail_latex/sailsailsailfndecodeSomevv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b10000000000000000000 @ 0b000001) = #\hyperref[zSome]{Some}#(#\hyperref[zTLBR]{TLBR}#() : ast) diff --git a/cheri/sail_latex/sailsailsailmodbitsvv.tex b/cheri/sail_latex/sailsailsailmodbitsvv.tex deleted file mode 100644 index 7f154d12..00000000 --- a/cheri/sail_latex/sailsailsailmodbitsvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_TLBEntry_bits, _set_TLBEntry_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeBCMPZvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeBCMPZvvv.tex deleted file mode 100644 index b58ee95f..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeBCMPZvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b10010 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, LT, true, true)) /* BLTZALL */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeBEQvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeBEQvvv.tex deleted file mode 100644 index c8be8d7f..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeBEQvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010101 @ rs : regno @ rt : regno @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBEQ]{BEQ}#(rs, rt, imm, true , true)) /* BNEL */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeCJALRvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeCJALRvvv.tex deleted file mode 100644 index bc34143b..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeCJALRvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ cd : regno @ cb : regno @ 0b01100 @ 0b111111) = #\hyperref[zSome]{Some}#(#\hyperref[zCJALR]{CJALR}#(cd, cb, true)) /* CJALR */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeCLoadvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeCLoadvvv.tex deleted file mode 100644 index a510352e..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeCLoadvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b1 @ 0b01) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, true, H, false)) /* CLH */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeCPtrCmpvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeCPtrCmpvvv.tex deleted file mode 100644 index 1cbb97ff..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeCPtrCmpvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b011) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLE)) diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeCStorevvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeCStorevvv.tex deleted file mode 100644 index 1ff7d0b3..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeCStorevvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111010 @ rs : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b11) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, rt, 0b00000, offset, D, false)) /* CSD */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeClearRegsvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeClearRegsvvv.tex deleted file mode 100644 index 21776cce..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeClearRegsvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01111 @ 0b00011 @ imm : #\hyperref[zbits]{bits}#(16)) = #\hyperref[zSome]{Some}#(#\hyperref[zClearRegs]{ClearRegs}#(CHi, imm)) diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeLoadvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeLoadvvv.tex deleted file mode 100644 index e0f61740..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeLoadvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b100101 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(H, false, false, base, rt, offset)) /* LHU */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeStorevvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeStorevvv.tex deleted file mode 100644 index 83e6bdf2..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeStorevvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111111 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zStore]{Store}#(D, false, base, rt, offset)) /* SD */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeTRAPIMMvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeTRAPIMMvvv.tex deleted file mode 100644 index 225ae50d..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeTRAPIMMvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b01001 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, GEU)) /* TGEIU */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomeTRAPREGvvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomeTRAPREGvvv.tex deleted file mode 100644 index 4cd33da5..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomeTRAPREGvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ code : #\hyperref[zbits]{bits}#(10) @ 0b110011) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, LTU)) /* TLTU */ diff --git a/cheri/sail_latex/sailsailsailsailfndecodeSomevvv.tex b/cheri/sail_latex/sailsailsailsailfndecodeSomevvv.tex deleted file mode 100644 index 2ef5d08d..00000000 --- a/cheri/sail_latex/sailsailsailsailfndecodeSomevvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010000 @ 0b10000000000000000000 @ 0b001000) = #\hyperref[zSome]{Some}#(#\hyperref[zTLBP]{TLBP}#() : ast) diff --git a/cheri/sail_latex/sailsailsailsailmodbitsvvv.tex b/cheri/sail_latex/sailsailsailsailmodbitsvvv.tex deleted file mode 100644 index bde40ee8..00000000 --- a/cheri/sail_latex/sailsailsailsailmodbitsvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_XContextReg_bits, _set_XContextReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeBCMPZvvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeBCMPZvvvv.tex deleted file mode 100644 index cf942540..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeBCMPZvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b00001 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, GE, false, false)) /* BGEZ */ diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCLoadvvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCLoadvvvv.tex deleted file mode 100644 index db208247..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCLoadvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b10) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, false, W, false)) /* CLWU */ diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCPtrCmpvvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCPtrCmpvvvv.tex deleted file mode 100644 index c49c5823..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCPtrCmpvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b100) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLTU)) diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCStorevvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCStorevvvv.tex deleted file mode 100644 index 50b5be16..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeCStorevvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b00) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, 0b00000, rd, 0b00000000, B, true)) /* CSCB */ diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeLoadvvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeLoadvvvv.tex deleted file mode 100644 index 4983e9f0..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeLoadvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b100011 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(W, true, false, base, rt, offset)) /* LW */ diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeStorevvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeStorevvvv.tex deleted file mode 100644 index 64711c35..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeStorevvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111000 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zStore]{Store}#(W, true, base, rt, offset)) /* SC */ diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeTRAPIMMvvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeTRAPIMMvvvv.tex deleted file mode 100644 index 369341e7..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeTRAPIMMvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b01010 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, LT)) /* TLTI */ diff --git a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeTRAPREGvvvv.tex b/cheri/sail_latex/sailsailsailsailsailfndecodeSomeTRAPREGvvvv.tex deleted file mode 100644 index ac4b2bdb..00000000 --- a/cheri/sail_latex/sailsailsailsailsailfndecodeSomeTRAPREGvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ code : #\hyperref[zbits]{bits}#(10) @ 0b110100) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, EQ)) /* TEQ */ diff --git a/cheri/sail_latex/sailsailsailsailsailmodbitsvvvv.tex b/cheri/sail_latex/sailsailsailsailsailmodbitsvvvv.tex deleted file mode 100644 index 8b2aac3e..00000000 --- a/cheri/sail_latex/sailsailsailsailsailmodbitsvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_ContextReg_bits, _set_ContextReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeBCMPZvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeBCMPZvvvvv.tex deleted file mode 100644 index 548182a5..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeBCMPZvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b10001 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, GE, true, false)) /* BGEZAL */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCLoadvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCLoadvvvvv.tex deleted file mode 100644 index 5f29eb1c..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCLoadvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b1 @ 0b10) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, true, W, false)) /* CLW */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvv.tex deleted file mode 100644 index 27f6c71c..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b101) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLEU)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCStorevvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCStorevvvvv.tex deleted file mode 100644 index 3b0a96ff..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeCStorevvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b01) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, 0b00000, rd, 0b00000000, H, true)) /* CSCH */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeLoadvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeLoadvvvvv.tex deleted file mode 100644 index 6bc11576..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeLoadvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b100111 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(W, false, false, base, rt, offset)) /* LWU */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeStorevvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeStorevvvvv.tex deleted file mode 100644 index e7f1c376..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeStorevvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b111100 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zStore]{Store}#(D, true, base, rt, offset)) /* SCD */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPIMMvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPIMMvvvvv.tex deleted file mode 100644 index ee21bf92..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPIMMvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b01011 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPIMM]{TRAPIMM}#(rs, imm, LTU)) /* TLTIU */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPREGvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPREGvvvvv.tex deleted file mode 100644 index 15cb09f9..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailfndecodeSomeTRAPREGvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000000 @ rs : regno @ rt : regno @ code : #\hyperref[zbits]{bits}#(10) @ 0b110110) = - #\hyperref[zSome]{Some}#(#\hyperref[zTRAPREG]{TRAPREG}#(rs, rt, NE)) /* TNE */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailmodbitsvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailmodbitsvvvvv.tex deleted file mode 100644 index d52fa2ec..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailmodbitsvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_TLBEntryHiReg_bits, _set_TLBEntryHiReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvv.tex deleted file mode 100644 index 1cadc33c..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b00011 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, GE, false, true)) /* BGEZL */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvv.tex deleted file mode 100644 index 187c70a2..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110010 @ rd : regno @ cb : regno@ rt : regno @ offset : #\hyperref[zbits]{bits}#(8) @ 0b0 @ 0b11) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, rt, offset, false, D, false)) /* CLD */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvv.tex deleted file mode 100644 index 26c46207..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b110) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CEXEQ)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCStorevvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCStorevvvvvv.tex deleted file mode 100644 index 1b2921e2..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeCStorevvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b10) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, 0b00000, rd, 0b00000000, W, true)) /* CSCW */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeLoadvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeLoadvvvvvv.tex deleted file mode 100644 index 1172d6d4..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailfndecodeSomeLoadvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110111 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(D, false, false, base, rt, offset)) /* LD */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailmodbitsvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailmodbitsvvvvvv.tex deleted file mode 100644 index 7ba9e37c..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailmodbitsvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_TLBEntryLoReg_bits, _set_TLBEntryLoReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvv.tex deleted file mode 100644 index 36b5eb5c..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000001 @ rs : regno @ 0b10011 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, GE, true, true)) /* BGEZALL */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvv.tex deleted file mode 100644 index 91fb7205..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b00) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, false, B, true)) /* CLLBU */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvv.tex deleted file mode 100644 index 644864c8..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b01110 @ rd : regno @ cb : regno @ ct : regno @ 0b000 @ 0b111) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, ct, CNEXEQ)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCStorevvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCStorevvvvvvv.tex deleted file mode 100644 index cd3cbe68..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeCStorevvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rs : regno @ cb : regno @ rd : regno @ 0b0000 @ 0b11) = #\hyperref[zSome]{Some}#(#\hyperref[zCStore]{CStore}#(rs, cb, 0b00000, rd, 0b00000000, D, true)) /* CSCD */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvv.tex deleted file mode 100644 index 61af3203..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110000 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(W, true, true, base, rt, offset)) /* LL */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailmodbitsvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailmodbitsvvvvvvv.tex deleted file mode 100644 index b9059538..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailmodbitsvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload _mod_bits = {_get_CauseReg_bits, _set_CauseReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvv.tex deleted file mode 100644 index 71d4e6a5..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000111 @ rs : regno @ 0b00000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, GT, false, false)) /* BGTZ */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvv.tex deleted file mode 100644 index 4b5608e4..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b1 @ 0b00) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, true, B, true)) /* CLLB */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvv.tex deleted file mode 100644 index 5649673e..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010100) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CEQ)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvvv.tex deleted file mode 100644 index 99da4355..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailfndecodeSomeLoadvvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b110100 @ base : regno @ rt : regno @ offset : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zLoad]{Load}#(D, false, true, base, rt, offset)) /* LLD */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvv.tex deleted file mode 100644 index 53bc8683..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010111 @ rs : regno @ 0b00000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, GT, false, true)) /* BGTZL */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvv.tex deleted file mode 100644 index fde00667..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b01) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, false, H, true)) /* CLLHU */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvv.tex deleted file mode 100644 index a6a71fee..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010101) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CNE)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvv.tex deleted file mode 100644 index 1718e9a8..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b000110 @ rs : regno @ 0b00000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, LE, false, false)) /* BLEZ */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvv.tex deleted file mode 100644 index 72c5c950..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b1 @ 0b01) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, true, H, true)) /* CLLH */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvv.tex deleted file mode 100644 index 0346ca8c..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010110) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLT)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvvv.tex deleted file mode 100644 index f0772815..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeBCMPZvvvvvvvvvvv.tex +++ /dev/null @@ -1,2 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010110 @ rs : regno @ 0b00000 @ imm : imm16) = - #\hyperref[zSome]{Some}#(#\hyperref[zBCMPZ]{BCMPZ}#(rs, imm, LE, false, true)) /* BLEZL */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvv.tex deleted file mode 100644 index 3378b72a..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b10) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, false, W, true)) /* CLLWU */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvv.tex deleted file mode 100644 index 133bc7e4..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b010111) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLE)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvv.tex deleted file mode 100644 index c9a4c20e..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b1 @ 0b10) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, true, W, true)) /* CLLW */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvv.tex deleted file mode 100644 index 0b8afa50..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b011000) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLTU)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvvv.tex deleted file mode 100644 index 791243c3..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCLoadvvvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b10000 @ rd : regno @ cb : regno @ 0b00000001 @ 0b0 @ 0b11) = #\hyperref[zSome]{Some}#(#\hyperref[zCLoad]{CLoad}#(rd, cb, 0b00000, 0b00000000, false, D, true)) /* CLLD */ diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvv.tex deleted file mode 100644 index f37b5e5a..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b011001) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLEU)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvv.tex deleted file mode 100644 index 709a6f6d..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b011010) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CEXEQ)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvvv.tex deleted file mode 100644 index ae2792ce..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailsailsailsailsailsailsailsailsailfndecodeSomeCPtrCmpvvvvvvvvvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -function clause #\hyperref[zdecode]{decode}# (0b010010 @ 0b00000 @ rd : regno @ cb : regno @ cs : regno @ 0b100001) = #\hyperref[zSome]{Some}#(#\hyperref[zCPtrCmp]{CPtrCmp}#(rd, cb, cs, CNEXEQ)) diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailsailupdatebitsvvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailsailupdatebitsvvvvvvv.tex deleted file mode 100644 index 1be74427..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailsailupdatebitsvvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_CauseReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailsailsailupdatebitsvvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailsailupdatebitsvvvvvv.tex deleted file mode 100644 index 60c5e7a6..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailsailupdatebitsvvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_TLBEntryLoReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailsailupdatebitsvvvvv.tex b/cheri/sail_latex/sailsailsailsailsailsailupdatebitsvvvvv.tex deleted file mode 100644 index efc2c5b0..00000000 --- a/cheri/sail_latex/sailsailsailsailsailsailupdatebitsvvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_TLBEntryHiReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailsailupdatebitsvvvv.tex b/cheri/sail_latex/sailsailsailsailsailupdatebitsvvvv.tex deleted file mode 100644 index c4d81402..00000000 --- a/cheri/sail_latex/sailsailsailsailsailupdatebitsvvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_ContextReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailupdatebitsvvv.tex b/cheri/sail_latex/sailsailsailsailupdatebitsvvv.tex deleted file mode 100644 index 28ee31f9..00000000 --- a/cheri/sail_latex/sailsailsailsailupdatebitsvvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_XContextReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailsailzeightoperatorzzerozJzJzninevvv.tex b/cheri/sail_latex/sailsailsailsailzeightoperatorzzerozJzJzninevvv.tex deleted file mode 100644 index 0f72fdc9..00000000 --- a/cheri/sail_latex/sailsailsailsailzeightoperatorzzerozJzJzninevvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_bit2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailupdatebitsvv.tex b/cheri/sail_latex/sailsailsailupdatebitsvv.tex deleted file mode 100644 index 64d81afd..00000000 --- a/cheri/sail_latex/sailsailsailupdatebitsvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_TLBEntry_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailzeightoperatorzzerozBzninevv.tex b/cheri/sail_latex/sailsailsailzeightoperatorzzerozBzninevv.tex deleted file mode 100644 index eacd556c..00000000 --- a/cheri/sail_latex/sailsailsailzeightoperatorzzerozBzninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator +) = {add_atom, add_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailzeightoperatorzzerozFzninevv.tex b/cheri/sail_latex/sailsailsailzeightoperatorzzerozFzninevv.tex deleted file mode 100644 index 73c40722..00000000 --- a/cheri/sail_latex/sailsailsailzeightoperatorzzerozFzninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator /) = {div}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailzeightoperatorzzerozJzJzninevv.tex b/cheri/sail_latex/sailsailsailzeightoperatorzzerozJzJzninevv.tex deleted file mode 100644 index 47b1d0f6..00000000 --- a/cheri/sail_latex/sailsailsailzeightoperatorzzerozJzJzninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_atom, eq_range, eq_int, eq_bool}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsailzeightoperatorzzerozfivezninevv.tex b/cheri/sail_latex/sailsailsailzeightoperatorzzerozfivezninevv.tex deleted file mode 100644 index 552e0c24..00000000 --- a/cheri/sail_latex/sailsailsailzeightoperatorzzerozfivezninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator %) = {mod}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailsignextend.tex b/cheri/sail_latex/sailsailsignextend.tex deleted file mode 100644 index dfaa5c86..00000000 --- a/cheri/sail_latex/sailsailsignextend.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_sign_extend = "sign_extend" : forall 'n 'm, 'm >= 'n. (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latex/sailsailupdateASIDv.tex b/cheri/sail_latex/sailsailupdateASIDv.tex deleted file mode 100644 index f415980a..00000000 --- a/cheri/sail_latex/sailsailupdateASIDv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_ASID = {_update_TLBEntryHiReg_ASID}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailupdateExcCodev.tex b/cheri/sail_latex/sailsailupdateExcCodev.tex deleted file mode 100644 index 041de51c..00000000 --- a/cheri/sail_latex/sailsailupdateExcCodev.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_ExcCode = {_update_CauseReg_ExcCode}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailupdateGv.tex b/cheri/sail_latex/sailsailupdateGv.tex deleted file mode 100644 index 23f7bf3c..00000000 --- a/cheri/sail_latex/sailsailupdateGv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_G = {_update_TLBEntryLoReg_G}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailupdateRv.tex b/cheri/sail_latex/sailsailupdateRv.tex deleted file mode 100644 index 03a3a143..00000000 --- a/cheri/sail_latex/sailsailupdateRv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_R = {_update_TLBEntryHiReg_R}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailupdateVPNtwov.tex b/cheri/sail_latex/sailsailupdateVPNtwov.tex deleted file mode 100644 index e2b42a9a..00000000 --- a/cheri/sail_latex/sailsailupdateVPNtwov.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_VPN2 = {_update_TLBEntryHiReg_VPN2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailupdatebitsv.tex b/cheri/sail_latex/sailsailupdatebitsv.tex deleted file mode 100644 index cc90c98a..00000000 --- a/cheri/sail_latex/sailsailupdatebitsv.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_StatusReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozAzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozAzninev.tex deleted file mode 100644 index afe7a721..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozAzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator *) = {mult_atom, mult_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozBzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozBzninev.tex deleted file mode 100644 index ddc56bfd..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozBzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator +) = {add_bits, add_bits_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozDzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozDzninev.tex deleted file mode 100644 index 5d12fdf1..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozDzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator -) = {sub_atom, sub_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozFzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozFzninev.tex deleted file mode 100644 index 38e9124b..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozFzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator /) = {div_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozJzJzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozJzJzninev.tex deleted file mode 100644 index 1314a962..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozJzJzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_bit, eq_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozQzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozQzninev.tex deleted file mode 100644 index 05769645..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozQzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ^) = {sail_mask}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozUzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozUzninev.tex deleted file mode 100644 index 1ebacbc4..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozUzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator |) = {or_bool}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozfivezninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozfivezninev.tex deleted file mode 100644 index 14fa73b8..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozfivezninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator %) = {mod_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozonezJzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozonezJzninev.tex deleted file mode 100644 index 527cf596..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozonezJzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator !=) = {neq_atom, neq_range, neq_int, neq_bool}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzeightoperatorzzerozsixzninev.tex b/cheri/sail_latex/sailsailzeightoperatorzzerozsixzninev.tex deleted file mode 100644 index be6f29ef..00000000 --- a/cheri/sail_latex/sailsailzeightoperatorzzerozsixzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator &) = {and_bool}
\ No newline at end of file diff --git a/cheri/sail_latex/sailsailzzeroextend.tex b/cheri/sail_latex/sailsailzzeroextend.tex deleted file mode 100644 index 53f6fff9..00000000 --- a/cheri/sail_latex/sailsailzzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_zero_extend = "zero_extend" : forall 'n 'm, 'm >= 'n. (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latex/sailsailzzeros.tex b/cheri/sail_latex/sailsailzzeros.tex deleted file mode 100644 index 9c60aa12..00000000 --- a/cheri/sail_latex/sailsailzzeros.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_zeros = "zeros" : forall 'n. atom('n) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailsealCap.tex b/cheri/sail_latex/sailsealCap.tex deleted file mode 100644 index 891ae279..00000000 --- a/cheri/sail_latex/sailsealCap.tex +++ /dev/null @@ -1 +0,0 @@ -val sealCap : (CapStruct, bits(24)) -> (bool, CapStruct) diff --git a/cheri/sail_latex/sailsetCapBounds.tex b/cheri/sail_latex/sailsetCapBounds.tex deleted file mode 100644 index 6984ccf1..00000000 --- a/cheri/sail_latex/sailsetCapBounds.tex +++ /dev/null @@ -1 +0,0 @@ -val setCapBounds : (CapStruct, #\hyperref[zbits]{bits}#(64), #\hyperref[zbits]{bits}#(65)) -> (bool, CapStruct) diff --git a/cheri/sail_latex/sailsetCapCauseRegExcCode.tex b/cheri/sail_latex/sailsetCapCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCapCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCapCauseRegRegNum.tex b/cheri/sail_latex/sailsetCapCauseRegRegNum.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCapCauseRegRegNum.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCapCauseRegbits.tex b/cheri/sail_latex/sailsetCapCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCapCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCapOffset.tex b/cheri/sail_latex/sailsetCapOffset.tex deleted file mode 100644 index d2fca67a..00000000 --- a/cheri/sail_latex/sailsetCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -val setCapOffset : (CapStruct, #\hyperref[zbits]{bits}#(64)) -> (bool, CapStruct) diff --git a/cheri/sail_latex/sailsetCapPerms.tex b/cheri/sail_latex/sailsetCapPerms.tex deleted file mode 100644 index 617f19fb..00000000 --- a/cheri/sail_latex/sailsetCapPerms.tex +++ /dev/null @@ -1 +0,0 @@ -val setCapPerms : (CapStruct, bits(31)) -> CapStruct diff --git a/cheri/sail_latex/sailsetCauseRegBD.tex b/cheri/sail_latex/sailsetCauseRegBD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegBD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCauseRegCE.tex b/cheri/sail_latex/sailsetCauseRegCE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegCE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCauseRegExcCode.tex b/cheri/sail_latex/sailsetCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCauseRegIP.tex b/cheri/sail_latex/sailsetCauseRegIP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegIP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCauseRegIV.tex b/cheri/sail_latex/sailsetCauseRegIV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegIV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCauseRegWP.tex b/cheri/sail_latex/sailsetCauseRegWP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegWP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetCauseRegbits.tex b/cheri/sail_latex/sailsetCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetContextRegBadVPNtwo.tex b/cheri/sail_latex/sailsetContextRegBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetContextRegBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetContextRegPTEBase.tex b/cheri/sail_latex/sailsetContextRegPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetContextRegPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetContextRegbits.tex b/cheri/sail_latex/sailsetContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegBEV.tex b/cheri/sail_latex/sailsetStatusRegBEV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegBEV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegCU.tex b/cheri/sail_latex/sailsetStatusRegCU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegCU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegERL.tex b/cheri/sail_latex/sailsetStatusRegERL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegERL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegEXL.tex b/cheri/sail_latex/sailsetStatusRegEXL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegEXL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegIE.tex b/cheri/sail_latex/sailsetStatusRegIE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegIE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegIM.tex b/cheri/sail_latex/sailsetStatusRegIM.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegIM.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegKSU.tex b/cheri/sail_latex/sailsetStatusRegKSU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegKSU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegKX.tex b/cheri/sail_latex/sailsetStatusRegKX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegKX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegSX.tex b/cheri/sail_latex/sailsetStatusRegSX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegSX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegUX.tex b/cheri/sail_latex/sailsetStatusRegUX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegUX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetStatusRegbits.tex b/cheri/sail_latex/sailsetStatusRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetStatusRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryHiRegASID.tex b/cheri/sail_latex/sailsetTLBEntryHiRegASID.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryHiRegASID.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryHiRegR.tex b/cheri/sail_latex/sailsetTLBEntryHiRegR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryHiRegR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryHiRegVPNtwo.tex b/cheri/sail_latex/sailsetTLBEntryHiRegVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryHiRegVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryHiRegbits.tex b/cheri/sail_latex/sailsetTLBEntryHiRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryHiRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegC.tex b/cheri/sail_latex/sailsetTLBEntryLoRegC.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegC.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegCapL.tex b/cheri/sail_latex/sailsetTLBEntryLoRegCapL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegCapL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegCapS.tex b/cheri/sail_latex/sailsetTLBEntryLoRegCapS.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegCapS.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegD.tex b/cheri/sail_latex/sailsetTLBEntryLoRegD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegG.tex b/cheri/sail_latex/sailsetTLBEntryLoRegG.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegG.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegPFN.tex b/cheri/sail_latex/sailsetTLBEntryLoRegPFN.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegPFN.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegV.tex b/cheri/sail_latex/sailsetTLBEntryLoRegV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryLoRegbits.tex b/cheri/sail_latex/sailsetTLBEntryLoRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryLoRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryasid.tex b/cheri/sail_latex/sailsetTLBEntryasid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryasid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrybits.tex b/cheri/sail_latex/sailsetTLBEntrybits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrybits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrycaplone.tex b/cheri/sail_latex/sailsetTLBEntrycaplone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrycaplone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrycaplzero.tex b/cheri/sail_latex/sailsetTLBEntrycaplzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrycaplzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrycapsone.tex b/cheri/sail_latex/sailsetTLBEntrycapsone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrycapsone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrycapszero.tex b/cheri/sail_latex/sailsetTLBEntrycapszero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrycapszero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrycone.tex b/cheri/sail_latex/sailsetTLBEntrycone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrycone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryczero.tex b/cheri/sail_latex/sailsetTLBEntryczero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryczero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrydone.tex b/cheri/sail_latex/sailsetTLBEntrydone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrydone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrydzero.tex b/cheri/sail_latex/sailsetTLBEntrydzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrydzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryg.tex b/cheri/sail_latex/sailsetTLBEntryg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrypagemask.tex b/cheri/sail_latex/sailsetTLBEntrypagemask.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrypagemask.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrypfnone.tex b/cheri/sail_latex/sailsetTLBEntrypfnone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrypfnone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntrypfnzero.tex b/cheri/sail_latex/sailsetTLBEntrypfnzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntrypfnzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryr.tex b/cheri/sail_latex/sailsetTLBEntryr.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryr.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryvalid.tex b/cheri/sail_latex/sailsetTLBEntryvalid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryvalid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryvone.tex b/cheri/sail_latex/sailsetTLBEntryvone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryvone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryvpntwo.tex b/cheri/sail_latex/sailsetTLBEntryvpntwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetTLBEntryvzero.tex b/cheri/sail_latex/sailsetTLBEntryvzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetTLBEntryvzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetXContextRegXBadVPNtwo.tex b/cheri/sail_latex/sailsetXContextRegXBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetXContextRegXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetXContextRegXPTEBase.tex b/cheri/sail_latex/sailsetXContextRegXPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetXContextRegXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetXContextRegXR.tex b/cheri/sail_latex/sailsetXContextRegXR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetXContextRegXR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetXContextRegbits.tex b/cheri/sail_latex/sailsetXContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailsetXContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailsetslicebits.tex b/cheri/sail_latex/sailsetslicebits.tex deleted file mode 100644 index 8a81bff5..00000000 --- a/cheri/sail_latex/sailsetslicebits.tex +++ /dev/null @@ -1,2 +0,0 @@ -val set_slice_bits = "set_slice" : forall 'n 'm. - (atom('n), atom('m), #\hyperref[zbits]{bits}#('n), int, #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailsetsliceint.tex b/cheri/sail_latex/sailsetsliceint.tex deleted file mode 100644 index 413bf721..00000000 --- a/cheri/sail_latex/sailsetsliceint.tex +++ /dev/null @@ -1 +0,0 @@ -val set_slice_int = "set_slice_int" : forall 'w. (atom('w), int, int, #\hyperref[zbits]{bits}#('w)) -> int diff --git a/cheri/sail_latex/sailshiftbitsleft.tex b/cheri/sail_latex/sailshiftbitsleft.tex deleted file mode 100644 index cdb2eb6a..00000000 --- a/cheri/sail_latex/sailshiftbitsleft.tex +++ /dev/null @@ -1 +0,0 @@ -val "shift_bits_left" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) effect {undef} diff --git a/cheri/sail_latex/sailshiftbitsright.tex b/cheri/sail_latex/sailshiftbitsright.tex deleted file mode 100644 index dbc72b11..00000000 --- a/cheri/sail_latex/sailshiftbitsright.tex +++ /dev/null @@ -1 +0,0 @@ -val "shift_bits_right" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) effect {undef} diff --git a/cheri/sail_latex/sailshiftl.tex b/cheri/sail_latex/sailshiftl.tex deleted file mode 100644 index b2c54c27..00000000 --- a/cheri/sail_latex/sailshiftl.tex +++ /dev/null @@ -1 +0,0 @@ -val "shiftl" : forall 'm 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('m), atom('n)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latex/sailshiftr.tex b/cheri/sail_latex/sailshiftr.tex deleted file mode 100644 index f282dcbe..00000000 --- a/cheri/sail_latex/sailshiftr.tex +++ /dev/null @@ -1 +0,0 @@ -val "shiftr" : forall 'm 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('m), atom('n)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latex/sailshlint.tex b/cheri/sail_latex/sailshlint.tex deleted file mode 100644 index 8ffbcf6c..00000000 --- a/cheri/sail_latex/sailshlint.tex +++ /dev/null @@ -1 +0,0 @@ -val shl_int = "shl_int" : (int, int) -> int diff --git a/cheri/sail_latex/sailshrint.tex b/cheri/sail_latex/sailshrint.tex deleted file mode 100644 index 087c17bb..00000000 --- a/cheri/sail_latex/sailshrint.tex +++ /dev/null @@ -1 +0,0 @@ -val shr_int = "shr_int" : (int, int) -> int diff --git a/cheri/sail_latex/sailsigned.tex b/cheri/sail_latex/sailsigned.tex deleted file mode 100644 index dcdc3049..00000000 --- a/cheri/sail_latex/sailsigned.tex +++ /dev/null @@ -1,4 +0,0 @@ -val signed = { - c: "sail_signed", - _: "sint" -} : forall 'n, 'n > 0. #\hyperref[zbits]{bits}#('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1) diff --git a/cheri/sail_latex/sailsignextend.tex b/cheri/sail_latex/sailsignextend.tex deleted file mode 100644 index 03f56369..00000000 --- a/cheri/sail_latex/sailsignextend.tex +++ /dev/null @@ -1 +0,0 @@ -overload sign_extend = {mips_sign_extend}
\ No newline at end of file diff --git a/cheri/sail_latex/sailskipbarr.tex b/cheri/sail_latex/sailskipbarr.tex deleted file mode 100644 index 52a6bedd..00000000 --- a/cheri/sail_latex/sailskipbarr.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_barr = "skip" : unit -> unit effect {barr} diff --git a/cheri/sail_latex/sailskipeamem.tex b/cheri/sail_latex/sailskipeamem.tex deleted file mode 100644 index b6199f85..00000000 --- a/cheri/sail_latex/sailskipeamem.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_eamem = "skip" : unit -> unit effect {eamem} diff --git a/cheri/sail_latex/sailskipescape.tex b/cheri/sail_latex/sailskipescape.tex deleted file mode 100644 index 413b5c1f..00000000 --- a/cheri/sail_latex/sailskipescape.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_escape = "skip" : unit -> unit effect {escape} diff --git a/cheri/sail_latex/sailskiprmemt.tex b/cheri/sail_latex/sailskiprmemt.tex deleted file mode 100644 index 97c88af4..00000000 --- a/cheri/sail_latex/sailskiprmemt.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_rmemt = "skip" : unit -> unit effect {rmemt} diff --git a/cheri/sail_latex/sailskiprreg.tex b/cheri/sail_latex/sailskiprreg.tex deleted file mode 100644 index 08804f54..00000000 --- a/cheri/sail_latex/sailskiprreg.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_rreg = "skip" : unit -> unit effect {rreg} diff --git a/cheri/sail_latex/sailskipwmvt.tex b/cheri/sail_latex/sailskipwmvt.tex deleted file mode 100644 index 8f991c20..00000000 --- a/cheri/sail_latex/sailskipwmvt.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_wmvt = "skip" : unit -> unit effect {wmvt} diff --git a/cheri/sail_latex/sailskipwreg.tex b/cheri/sail_latex/sailskipwreg.tex deleted file mode 100644 index e79f7c10..00000000 --- a/cheri/sail_latex/sailskipwreg.tex +++ /dev/null @@ -1 +0,0 @@ -val skip_wreg = "skip" : unit -> unit effect {wreg} diff --git a/cheri/sail_latex/sailslice.tex b/cheri/sail_latex/sailslice.tex deleted file mode 100644 index b9bb5a70..00000000 --- a/cheri/sail_latex/sailslice.tex +++ /dev/null @@ -1,2 +0,0 @@ -val slice = "slice" : forall 'n 'm 'o, 0 <= 'o < 'm & 'o + 'n <= 'm & 0 <= 'n. - (#\hyperref[zbits]{bits}#('m), atom('o), atom('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailstringofint.tex b/cheri/sail_latex/sailstringofint.tex deleted file mode 100644 index 05edaa20..00000000 --- a/cheri/sail_latex/sailstringofint.tex +++ /dev/null @@ -1 +0,0 @@ -val string_of_int = "string_of_int" : int -> string diff --git a/cheri/sail_latex/sailsubatom.tex b/cheri/sail_latex/sailsubatom.tex deleted file mode 100644 index 437e2d4c..00000000 --- a/cheri/sail_latex/sailsubatom.tex +++ /dev/null @@ -1,2 +0,0 @@ -val sub_atom = {ocaml: "sub_int", lem: "integerMinus", c: "sub_int", coq: "Z.sub"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n - 'm) diff --git a/cheri/sail_latex/sailsubint.tex b/cheri/sail_latex/sailsubint.tex deleted file mode 100644 index 11fdf922..00000000 --- a/cheri/sail_latex/sailsubint.tex +++ /dev/null @@ -1 +0,0 @@ -val sub_int = {ocaml: "sub_int", lem: "integerMinus", c: "sub_int", coq: "Z.sub"} : (int, int) -> int diff --git a/cheri/sail_latex/sailsubrange.tex b/cheri/sail_latex/sailsubrange.tex deleted file mode 100644 index 2aad56b6..00000000 --- a/cheri/sail_latex/sailsubrange.tex +++ /dev/null @@ -1,2 +0,0 @@ -val sub_range = {ocaml: "sub_int", lem: "integerMinus", coq: "sub_range"} : forall 'n 'm 'o 'p. - (range('n, 'm), range('o, 'p)) -> range('n - 'p, 'm - 'o) diff --git a/cheri/sail_latex/sailsubvec.tex b/cheri/sail_latex/sailsubvec.tex deleted file mode 100644 index b92f07a4..00000000 --- a/cheri/sail_latex/sailsubvec.tex +++ /dev/null @@ -1 +0,0 @@ -val sub_vec = {c : "sub_bits", _:"sub_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailsubvecint.tex b/cheri/sail_latex/sailsubvecint.tex deleted file mode 100644 index 70bf667e..00000000 --- a/cheri/sail_latex/sailsubvecint.tex +++ /dev/null @@ -1 +0,0 @@ -val sub_vec_int = {c:"sub_bits_int", _: "sub_vec_int"} : forall 'n. (#\hyperref[zbits]{bits}#('n), int) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailsupportedinstructions.tex b/cheri/sail_latex/sailsupportedinstructions.tex deleted file mode 100644 index 489c178d..00000000 --- a/cheri/sail_latex/sailsupportedinstructions.tex +++ /dev/null @@ -1 +0,0 @@ -val supported_instructions : ast -> #\hyperref[zoption]{option}#(ast) diff --git a/cheri/sail_latex/sailtlbEntryMatch.tex b/cheri/sail_latex/sailtlbEntryMatch.tex deleted file mode 100644 index c8461b89..00000000 --- a/cheri/sail_latex/sailtlbEntryMatch.tex +++ /dev/null @@ -1 +0,0 @@ -val tlbEntryMatch : (#\hyperref[zbits]{bits}#(2), #\hyperref[zbits]{bits}#(27), #\hyperref[zbits]{bits}#(8), TLBEntry) -> bool effect pure diff --git a/cheri/sail_latex/sailtlbSearch.tex b/cheri/sail_latex/sailtlbSearch.tex deleted file mode 100644 index 4e391617..00000000 --- a/cheri/sail_latex/sailtlbSearch.tex +++ /dev/null @@ -1 +0,0 @@ -val tlbSearch : #\hyperref[zbits]{bits}#(64) -> #\hyperref[zoption]{option}#(TLBIndexT) effect {rreg} diff --git a/cheri/sail_latex/sailtobits.tex b/cheri/sail_latex/sailtobits.tex deleted file mode 100644 index 9dd3c655..00000000 --- a/cheri/sail_latex/sailtobits.tex +++ /dev/null @@ -1 +0,0 @@ -val to_bits : forall 'l, 'l >= 0 .(atom('l), int) -> #\hyperref[zbits]{bits}#('l) diff --git a/cheri/sail_latex/sailtruncate.tex b/cheri/sail_latex/sailtruncate.tex deleted file mode 100644 index 5f7760f3..00000000 --- a/cheri/sail_latex/sailtruncate.tex +++ /dev/null @@ -1,6 +0,0 @@ -val truncate = { - ocaml: "vector_truncate", - lem: "vector_truncate", - coq: "vector_truncate", - c: "sail_truncate" -} : forall 'm 'n, 'm >= 0 & 'm <= 'n. (vector('n, dec, bit), atom('m)) -> vector('m, dec, bit) diff --git a/cheri/sail_latex/sailuintsixfour.tex b/cheri/sail_latex/sailuintsixfour.tex deleted file mode 100644 index a0d52c8f..00000000 --- a/cheri/sail_latex/sailuintsixfour.tex +++ /dev/null @@ -1 +0,0 @@ -type uint64 = range(0, (2 ^ 64) - 1) diff --git a/cheri/sail_latex/sailunsigned.tex b/cheri/sail_latex/sailunsigned.tex deleted file mode 100644 index 47867039..00000000 --- a/cheri/sail_latex/sailunsigned.tex +++ /dev/null @@ -1,7 +0,0 @@ -val unsigned = { - ocaml: "uint", - lem: "uint", - interpreter: "uint", - c: "sail_unsigned", - coq: "uint" -} : forall 'n. #\hyperref[zbits]{bits}#('n) -> range(0, 2 ^ 'n - 1) diff --git a/cheri/sail_latex/sailupdateBD.tex b/cheri/sail_latex/sailupdateBD.tex deleted file mode 100644 index db94f260..00000000 --- a/cheri/sail_latex/sailupdateBD.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_BD = {_update_CauseReg_BD}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateBEV.tex b/cheri/sail_latex/sailupdateBEV.tex deleted file mode 100644 index e45f5c7d..00000000 --- a/cheri/sail_latex/sailupdateBEV.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_BEV = {_update_StatusReg_BEV}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateBadVPNtwo.tex b/cheri/sail_latex/sailupdateBadVPNtwo.tex deleted file mode 100644 index 7b9f2827..00000000 --- a/cheri/sail_latex/sailupdateBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_BadVPN2 = {_update_ContextReg_BadVPN2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateC.tex b/cheri/sail_latex/sailupdateC.tex deleted file mode 100644 index 4e4756e3..00000000 --- a/cheri/sail_latex/sailupdateC.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_C = {_update_TLBEntryLoReg_C}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateCE.tex b/cheri/sail_latex/sailupdateCE.tex deleted file mode 100644 index 12be67a2..00000000 --- a/cheri/sail_latex/sailupdateCE.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_CE = {_update_CauseReg_CE}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateCU.tex b/cheri/sail_latex/sailupdateCU.tex deleted file mode 100644 index fcc82986..00000000 --- a/cheri/sail_latex/sailupdateCU.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_CU = {_update_StatusReg_CU}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateCapCauseRegExcCode.tex b/cheri/sail_latex/sailupdateCapCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCapCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCapCauseRegRegNum.tex b/cheri/sail_latex/sailupdateCapCauseRegRegNum.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCapCauseRegRegNum.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCapCauseRegbits.tex b/cheri/sail_latex/sailupdateCapCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCapCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCapL.tex b/cheri/sail_latex/sailupdateCapL.tex deleted file mode 100644 index 7b0d8471..00000000 --- a/cheri/sail_latex/sailupdateCapL.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_CapL = {_update_TLBEntryLoReg_CapL}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateCapS.tex b/cheri/sail_latex/sailupdateCapS.tex deleted file mode 100644 index dfe685ee..00000000 --- a/cheri/sail_latex/sailupdateCapS.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_CapS = {_update_TLBEntryLoReg_CapS}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateCauseRegBD.tex b/cheri/sail_latex/sailupdateCauseRegBD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegBD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCauseRegCE.tex b/cheri/sail_latex/sailupdateCauseRegCE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegCE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCauseRegExcCode.tex b/cheri/sail_latex/sailupdateCauseRegExcCode.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegExcCode.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCauseRegIP.tex b/cheri/sail_latex/sailupdateCauseRegIP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegIP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCauseRegIV.tex b/cheri/sail_latex/sailupdateCauseRegIV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegIV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCauseRegWP.tex b/cheri/sail_latex/sailupdateCauseRegWP.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegWP.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateCauseRegbits.tex b/cheri/sail_latex/sailupdateCauseRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateCauseRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateContextRegBadVPNtwo.tex b/cheri/sail_latex/sailupdateContextRegBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateContextRegBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateContextRegPTEBase.tex b/cheri/sail_latex/sailupdateContextRegPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateContextRegPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateContextRegbits.tex b/cheri/sail_latex/sailupdateContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateD.tex b/cheri/sail_latex/sailupdateD.tex deleted file mode 100644 index 2f367d1e..00000000 --- a/cheri/sail_latex/sailupdateD.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_D = {_update_TLBEntryLoReg_D}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateERL.tex b/cheri/sail_latex/sailupdateERL.tex deleted file mode 100644 index d1f9da12..00000000 --- a/cheri/sail_latex/sailupdateERL.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_ERL = {_update_StatusReg_ERL}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateEXL.tex b/cheri/sail_latex/sailupdateEXL.tex deleted file mode 100644 index 9d82b64d..00000000 --- a/cheri/sail_latex/sailupdateEXL.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_EXL = {_update_StatusReg_EXL}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateExcCode.tex b/cheri/sail_latex/sailupdateExcCode.tex deleted file mode 100644 index 38736fe7..00000000 --- a/cheri/sail_latex/sailupdateExcCode.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_ExcCode = {_update_CapCauseReg_ExcCode}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateIE.tex b/cheri/sail_latex/sailupdateIE.tex deleted file mode 100644 index 421e8744..00000000 --- a/cheri/sail_latex/sailupdateIE.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_IE = {_update_StatusReg_IE}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateIM.tex b/cheri/sail_latex/sailupdateIM.tex deleted file mode 100644 index 6128559a..00000000 --- a/cheri/sail_latex/sailupdateIM.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_IM = {_update_StatusReg_IM}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateIP.tex b/cheri/sail_latex/sailupdateIP.tex deleted file mode 100644 index 1b855a0b..00000000 --- a/cheri/sail_latex/sailupdateIP.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_IP = {_update_CauseReg_IP}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateIV.tex b/cheri/sail_latex/sailupdateIV.tex deleted file mode 100644 index 7cfa3a60..00000000 --- a/cheri/sail_latex/sailupdateIV.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_IV = {_update_CauseReg_IV}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateKSU.tex b/cheri/sail_latex/sailupdateKSU.tex deleted file mode 100644 index b5688537..00000000 --- a/cheri/sail_latex/sailupdateKSU.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_KSU = {_update_StatusReg_KSU}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateKX.tex b/cheri/sail_latex/sailupdateKX.tex deleted file mode 100644 index ff23da68..00000000 --- a/cheri/sail_latex/sailupdateKX.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_KX = {_update_StatusReg_KX}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatePFN.tex b/cheri/sail_latex/sailupdatePFN.tex deleted file mode 100644 index fa32c59b..00000000 --- a/cheri/sail_latex/sailupdatePFN.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_PFN = {_update_TLBEntryLoReg_PFN}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatePTEBase.tex b/cheri/sail_latex/sailupdatePTEBase.tex deleted file mode 100644 index 8826eee7..00000000 --- a/cheri/sail_latex/sailupdatePTEBase.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_PTEBase = {_update_ContextReg_PTEBase}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateRegNum.tex b/cheri/sail_latex/sailupdateRegNum.tex deleted file mode 100644 index 61c4abe6..00000000 --- a/cheri/sail_latex/sailupdateRegNum.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_RegNum = {_update_CapCauseReg_RegNum}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateSX.tex b/cheri/sail_latex/sailupdateSX.tex deleted file mode 100644 index 4e416154..00000000 --- a/cheri/sail_latex/sailupdateSX.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_SX = {_update_StatusReg_SX}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateStatusRegBEV.tex b/cheri/sail_latex/sailupdateStatusRegBEV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegBEV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegCU.tex b/cheri/sail_latex/sailupdateStatusRegCU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegCU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegERL.tex b/cheri/sail_latex/sailupdateStatusRegERL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegERL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegEXL.tex b/cheri/sail_latex/sailupdateStatusRegEXL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegEXL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegIE.tex b/cheri/sail_latex/sailupdateStatusRegIE.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegIE.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegIM.tex b/cheri/sail_latex/sailupdateStatusRegIM.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegIM.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegKSU.tex b/cheri/sail_latex/sailupdateStatusRegKSU.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegKSU.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegKX.tex b/cheri/sail_latex/sailupdateStatusRegKX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegKX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegSX.tex b/cheri/sail_latex/sailupdateStatusRegSX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegSX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegUX.tex b/cheri/sail_latex/sailupdateStatusRegUX.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegUX.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateStatusRegbits.tex b/cheri/sail_latex/sailupdateStatusRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateStatusRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryHiRegASID.tex b/cheri/sail_latex/sailupdateTLBEntryHiRegASID.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryHiRegASID.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryHiRegR.tex b/cheri/sail_latex/sailupdateTLBEntryHiRegR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryHiRegR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryHiRegVPNtwo.tex b/cheri/sail_latex/sailupdateTLBEntryHiRegVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryHiRegVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryHiRegbits.tex b/cheri/sail_latex/sailupdateTLBEntryHiRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryHiRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegC.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegC.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegC.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegCapL.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegCapL.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegCapL.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegCapS.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegCapS.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegCapS.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegD.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegD.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegD.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegG.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegG.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegG.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegPFN.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegPFN.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegPFN.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegV.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegV.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegV.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryLoRegbits.tex b/cheri/sail_latex/sailupdateTLBEntryLoRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryLoRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryasid.tex b/cheri/sail_latex/sailupdateTLBEntryasid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryasid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrybits.tex b/cheri/sail_latex/sailupdateTLBEntrybits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrybits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrycaplone.tex b/cheri/sail_latex/sailupdateTLBEntrycaplone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrycaplone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrycaplzero.tex b/cheri/sail_latex/sailupdateTLBEntrycaplzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrycaplzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrycapsone.tex b/cheri/sail_latex/sailupdateTLBEntrycapsone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrycapsone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrycapszero.tex b/cheri/sail_latex/sailupdateTLBEntrycapszero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrycapszero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrycone.tex b/cheri/sail_latex/sailupdateTLBEntrycone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrycone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryczero.tex b/cheri/sail_latex/sailupdateTLBEntryczero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryczero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrydone.tex b/cheri/sail_latex/sailupdateTLBEntrydone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrydone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrydzero.tex b/cheri/sail_latex/sailupdateTLBEntrydzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrydzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryg.tex b/cheri/sail_latex/sailupdateTLBEntryg.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryg.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrypagemask.tex b/cheri/sail_latex/sailupdateTLBEntrypagemask.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrypagemask.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrypfnone.tex b/cheri/sail_latex/sailupdateTLBEntrypfnone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrypfnone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntrypfnzero.tex b/cheri/sail_latex/sailupdateTLBEntrypfnzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntrypfnzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryr.tex b/cheri/sail_latex/sailupdateTLBEntryr.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryr.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryvalid.tex b/cheri/sail_latex/sailupdateTLBEntryvalid.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryvalid.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryvone.tex b/cheri/sail_latex/sailupdateTLBEntryvone.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryvone.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryvpntwo.tex b/cheri/sail_latex/sailupdateTLBEntryvpntwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryvpntwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateTLBEntryvzero.tex b/cheri/sail_latex/sailupdateTLBEntryvzero.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateTLBEntryvzero.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateUX.tex b/cheri/sail_latex/sailupdateUX.tex deleted file mode 100644 index d0d2a663..00000000 --- a/cheri/sail_latex/sailupdateUX.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_UX = {_update_StatusReg_UX}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateV.tex b/cheri/sail_latex/sailupdateV.tex deleted file mode 100644 index 336f76d5..00000000 --- a/cheri/sail_latex/sailupdateV.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_V = {_update_TLBEntryLoReg_V}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateWP.tex b/cheri/sail_latex/sailupdateWP.tex deleted file mode 100644 index d4528672..00000000 --- a/cheri/sail_latex/sailupdateWP.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_WP = {_update_CauseReg_WP}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateXBadVPNtwo.tex b/cheri/sail_latex/sailupdateXBadVPNtwo.tex deleted file mode 100644 index 9bb69796..00000000 --- a/cheri/sail_latex/sailupdateXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_XBadVPN2 = {_update_XContextReg_XBadVPN2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateXContextRegXBadVPNtwo.tex b/cheri/sail_latex/sailupdateXContextRegXBadVPNtwo.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateXContextRegXBadVPNtwo.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateXContextRegXPTEBase.tex b/cheri/sail_latex/sailupdateXContextRegXPTEBase.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateXContextRegXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateXContextRegXR.tex b/cheri/sail_latex/sailupdateXContextRegXR.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateXContextRegXR.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateXContextRegbits.tex b/cheri/sail_latex/sailupdateXContextRegbits.tex deleted file mode 100644 index 8b137891..00000000 --- a/cheri/sail_latex/sailupdateXContextRegbits.tex +++ /dev/null @@ -1 +0,0 @@ - diff --git a/cheri/sail_latex/sailupdateXPTEBase.tex b/cheri/sail_latex/sailupdateXPTEBase.tex deleted file mode 100644 index 8a203d30..00000000 --- a/cheri/sail_latex/sailupdateXPTEBase.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_XPTEBase = {_update_XContextReg_XPTEBase}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateXR.tex b/cheri/sail_latex/sailupdateXR.tex deleted file mode 100644 index 1854ca65..00000000 --- a/cheri/sail_latex/sailupdateXR.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_XR = {_update_XContextReg_XR}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateasid.tex b/cheri/sail_latex/sailupdateasid.tex deleted file mode 100644 index 8fa9f60a..00000000 --- a/cheri/sail_latex/sailupdateasid.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_asid = {_update_TLBEntry_asid}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatebits.tex b/cheri/sail_latex/sailupdatebits.tex deleted file mode 100644 index 84c93c53..00000000 --- a/cheri/sail_latex/sailupdatebits.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_bits = {_update_CapCauseReg_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatecaplone.tex b/cheri/sail_latex/sailupdatecaplone.tex deleted file mode 100644 index a0ce007c..00000000 --- a/cheri/sail_latex/sailupdatecaplone.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_capl1 = {_update_TLBEntry_capl1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatecaplzero.tex b/cheri/sail_latex/sailupdatecaplzero.tex deleted file mode 100644 index 11747581..00000000 --- a/cheri/sail_latex/sailupdatecaplzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_capl0 = {_update_TLBEntry_capl0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatecapsone.tex b/cheri/sail_latex/sailupdatecapsone.tex deleted file mode 100644 index 6449364e..00000000 --- a/cheri/sail_latex/sailupdatecapsone.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_caps1 = {_update_TLBEntry_caps1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatecapszero.tex b/cheri/sail_latex/sailupdatecapszero.tex deleted file mode 100644 index 1791d720..00000000 --- a/cheri/sail_latex/sailupdatecapszero.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_caps0 = {_update_TLBEntry_caps0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatecone.tex b/cheri/sail_latex/sailupdatecone.tex deleted file mode 100644 index f8e39aea..00000000 --- a/cheri/sail_latex/sailupdatecone.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_c1 = {_update_TLBEntry_c1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateczero.tex b/cheri/sail_latex/sailupdateczero.tex deleted file mode 100644 index ccb2da58..00000000 --- a/cheri/sail_latex/sailupdateczero.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_c0 = {_update_TLBEntry_c0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatedone.tex b/cheri/sail_latex/sailupdatedone.tex deleted file mode 100644 index ee303126..00000000 --- a/cheri/sail_latex/sailupdatedone.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_d1 = {_update_TLBEntry_d1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatedzero.tex b/cheri/sail_latex/sailupdatedzero.tex deleted file mode 100644 index 799b9f2f..00000000 --- a/cheri/sail_latex/sailupdatedzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_d0 = {_update_TLBEntry_d0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdateg.tex b/cheri/sail_latex/sailupdateg.tex deleted file mode 100644 index 988d87b6..00000000 --- a/cheri/sail_latex/sailupdateg.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_g = {_update_TLBEntry_g}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatepagemask.tex b/cheri/sail_latex/sailupdatepagemask.tex deleted file mode 100644 index e57ea1df..00000000 --- a/cheri/sail_latex/sailupdatepagemask.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_pagemask = {_update_TLBEntry_pagemask}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatepfnone.tex b/cheri/sail_latex/sailupdatepfnone.tex deleted file mode 100644 index a6e7a80d..00000000 --- a/cheri/sail_latex/sailupdatepfnone.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_pfn1 = {_update_TLBEntry_pfn1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatepfnzero.tex b/cheri/sail_latex/sailupdatepfnzero.tex deleted file mode 100644 index 54244083..00000000 --- a/cheri/sail_latex/sailupdatepfnzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_pfn0 = {_update_TLBEntry_pfn0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdater.tex b/cheri/sail_latex/sailupdater.tex deleted file mode 100644 index 485fdf99..00000000 --- a/cheri/sail_latex/sailupdater.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_r = {_update_TLBEntry_r}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatevalid.tex b/cheri/sail_latex/sailupdatevalid.tex deleted file mode 100644 index 9c19b5b5..00000000 --- a/cheri/sail_latex/sailupdatevalid.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_valid = {_update_TLBEntry_valid}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatevone.tex b/cheri/sail_latex/sailupdatevone.tex deleted file mode 100644 index 5da0a4e9..00000000 --- a/cheri/sail_latex/sailupdatevone.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_v1 = {_update_TLBEntry_v1}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatevpntwo.tex b/cheri/sail_latex/sailupdatevpntwo.tex deleted file mode 100644 index b4743a0c..00000000 --- a/cheri/sail_latex/sailupdatevpntwo.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_vpn2 = {_update_TLBEntry_vpn2}
\ No newline at end of file diff --git a/cheri/sail_latex/sailupdatevzero.tex b/cheri/sail_latex/sailupdatevzero.tex deleted file mode 100644 index 0405f0c0..00000000 --- a/cheri/sail_latex/sailupdatevzero.tex +++ /dev/null @@ -1 +0,0 @@ -overload update_v0 = {_update_TLBEntry_v0}
\ No newline at end of file diff --git a/cheri/sail_latex/sailvectoraccess.tex b/cheri/sail_latex/sailvectoraccess.tex deleted file mode 100644 index a8e8074f..00000000 --- a/cheri/sail_latex/sailvectoraccess.tex +++ /dev/null @@ -1 +0,0 @@ -overload vector_access = {bitvector_access, plain_vector_access}
\ No newline at end of file diff --git a/cheri/sail_latex/sailvectorlength.tex b/cheri/sail_latex/sailvectorlength.tex deleted file mode 100644 index f41d5bfa..00000000 --- a/cheri/sail_latex/sailvectorlength.tex +++ /dev/null @@ -1,6 +0,0 @@ -val vector_length = { - ocaml: "length", - lem: "length_list", - c: "length", - coq: "vec_length" -} : forall '#\hyperref[zn]{n}# ('a : Type). vector('n, dec, 'a) -> atom('n) diff --git a/cheri/sail_latex/sailvectorsubrange.tex b/cheri/sail_latex/sailvectorsubrange.tex deleted file mode 100644 index c069c7b6..00000000 --- a/cheri/sail_latex/sailvectorsubrange.tex +++ /dev/null @@ -1,7 +0,0 @@ -val vector_subrange = { - ocaml: "subrange", - lem: "subrange_vec_dec", - c: "vector_subrange", - coq: "subrange_vec_dec" -} : forall ('n : Int) ('m : Int) ('o : Int), 0 <= 'o <= 'm < 'n. - (#\hyperref[zbits]{bits}#('n), atom('m), atom('o)) -> #\hyperref[zbits]{bits}#('m - 'o + 1) diff --git a/cheri/sail_latex/sailvectorupdate.tex b/cheri/sail_latex/sailvectorupdate.tex deleted file mode 100644 index 1ec4aaef..00000000 --- a/cheri/sail_latex/sailvectorupdate.tex +++ /dev/null @@ -1 +0,0 @@ -overload vector_update = {bitvector_update, plain_vector_update}
\ No newline at end of file diff --git a/cheri/sail_latex/sailvectorupdatesubrange.tex b/cheri/sail_latex/sailvectorupdatesubrange.tex deleted file mode 100644 index 6ff4f9f6..00000000 --- a/cheri/sail_latex/sailvectorupdatesubrange.tex +++ /dev/null @@ -1,6 +0,0 @@ -val vector_update_subrange = { - ocaml: "update_subrange", - lem: "update_subrange_vec_dec", - c: "vector_update_subrange", - coq: "update_subrange_vec_dec" -} : forall 'n 'm 'o. (#\hyperref[zbits]{bits}#('n), atom('m), atom('o), #\hyperref[zbits]{bits}#('m - ('o - 1))) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailwGPR.tex b/cheri/sail_latex/sailwGPR.tex deleted file mode 100644 index bf78e005..00000000 --- a/cheri/sail_latex/sailwGPR.tex +++ /dev/null @@ -1 +0,0 @@ -val wGPR : (#\hyperref[zbits]{bits}#(5), #\hyperref[zbits]{bits}#(64)) -> unit effect {wreg} diff --git a/cheri/sail_latex/sailwordWidthBytes.tex b/cheri/sail_latex/sailwordWidthBytes.tex deleted file mode 100644 index aa5bbe5f..00000000 --- a/cheri/sail_latex/sailwordWidthBytes.tex +++ /dev/null @@ -1 +0,0 @@ -val wordWidthBytes : WordType -> range(1, 8) diff --git a/cheri/sail_latex/sailwriteCapReg.tex b/cheri/sail_latex/sailwriteCapReg.tex deleted file mode 100644 index 44b9d466..00000000 --- a/cheri/sail_latex/sailwriteCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -val writeCapReg : (regno, CapStruct) -> unit effect {wreg} diff --git a/cheri/sail_latex/sailxorvec.tex b/cheri/sail_latex/sailxorvec.tex deleted file mode 100644 index b3aa7372..00000000 --- a/cheri/sail_latex/sailxorvec.tex +++ /dev/null @@ -1 +0,0 @@ -val xor_vec = {c: "xor_bits" , _: "xor_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latex/sailzW.tex b/cheri/sail_latex/sailzW.tex deleted file mode 100644 index a29ec93f..00000000 --- a/cheri/sail_latex/sailzW.tex +++ /dev/null @@ -1 +0,0 @@ -overload ~ = {not_bool, not_vec}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozAsznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozAsznine.tex deleted file mode 100644 index 0b0a46e2..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozAsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator *_s = "mults_vec" : forall 'n . (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#(2 * 'n) diff --git a/cheri/sail_latex/sailzeightoperatorzzerozAuznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozAuznine.tex deleted file mode 100644 index 5b762ba7..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozAuznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator *_u = "mult_vec" : forall 'n . (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#(2 * 'n) diff --git a/cheri/sail_latex/sailzeightoperatorzzerozAznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozAznine.tex deleted file mode 100644 index 2d188f63..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozAznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator *) = {mult_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozBznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozBznine.tex deleted file mode 100644 index 432e85e5..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozBznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator +) = {add_range, add_int, add_vec, add_vec_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozDznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozDznine.tex deleted file mode 100644 index d671e6b0..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozDznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator -) = {sub_range, sub_int, sub_vec, sub_vec_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozFznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozFznine.tex deleted file mode 100644 index 3c2e441c..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozFznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator /) = {quotient_nat, quotient}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozIsznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozIsznine.tex deleted file mode 100644 index 9b4ebe19..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozIsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator <_s : forall 'n, 'n > 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latex/sailzeightoperatorzzerozIuznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozIuznine.tex deleted file mode 100644 index 5b54235e..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozIuznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator <_u : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latex/sailzeightoperatorzzerozIzIznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozIzIznine.tex deleted file mode 100644 index 51ff2b6c..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozIzIznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator <<) = {shift_bits_left, shiftl}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozIzJznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozIzJznine.tex deleted file mode 100644 index d23f28dd..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozIzJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator <=) = {lteq_atom, lteq_range_atom, lteq_atom_range, lteq_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozIznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozIznine.tex deleted file mode 100644 index 8e5e3fe9..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozIznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator <) = {lt_atom, lt_range_atom, lt_atom_range, lt_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozJzJznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozJzJznine.tex deleted file mode 100644 index 57ea823c..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozJzJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_anything}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozKzJsznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozKzJsznine.tex deleted file mode 100644 index 032e8600..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozKzJsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator >=_s : forall 'n, 'n > 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latex/sailzeightoperatorzzerozKzJuznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozKzJuznine.tex deleted file mode 100644 index eaa72e60..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozKzJuznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator >=_u : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latex/sailzeightoperatorzzerozKzJznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozKzJznine.tex deleted file mode 100644 index 5733b740..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozKzJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator >=) = {gteq_atom, gteq_range_atom, gteq_atom_range, gteq_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozKzKsznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozKzKsznine.tex deleted file mode 100644 index 0f0793a6..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozKzKsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator >>_s = "shift_bits_right_arith" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) effect {undef} diff --git a/cheri/sail_latex/sailzeightoperatorzzerozKzKznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozKzKznine.tex deleted file mode 100644 index b129e9d2..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozKzKznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator >>) = {shift_bits_right, shiftr}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozKznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozKznine.tex deleted file mode 100644 index a8da7e48..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozKznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator >) = {gt_atom, gt_range_atom, gt_atom_range, gt_int}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozQzQznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozQzQznine.tex deleted file mode 100644 index 185f501e..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozQzQznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator ^^ = {lem: "replicate_bits"} : forall 'n 'm, 'm >= 0 . (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('n * 'm) diff --git a/cheri/sail_latex/sailzeightoperatorzzerozQznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozQznine.tex deleted file mode 100644 index 106b6064..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozQznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ^) = {xor_vec, int_power}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozUznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozUznine.tex deleted file mode 100644 index 4de737e0..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozUznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator |) = {or_bool, or_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozfiveznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozfiveznine.tex deleted file mode 100644 index 8d6b54c3..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozfiveznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator %) = {modulus}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozonezJznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozonezJznine.tex deleted file mode 100644 index 22052668..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozonezJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator !=) = {neq_atom, neq_int, neq_vec, neq_anything}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzeightoperatorzzerozsixznine.tex b/cheri/sail_latex/sailzeightoperatorzzerozsixznine.tex deleted file mode 100644 index 248fb15e..00000000 --- a/cheri/sail_latex/sailzeightoperatorzzerozsixznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator &) = {and_bool, and_bits}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzzeroextend.tex b/cheri/sail_latex/sailzzeroextend.tex deleted file mode 100644 index 0f754d44..00000000 --- a/cheri/sail_latex/sailzzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -overload zero_extend = {mips_zero_extend}
\ No newline at end of file diff --git a/cheri/sail_latex/sailzzeros.tex b/cheri/sail_latex/sailzzeros.tex deleted file mode 100644 index 1c251eda..00000000 --- a/cheri/sail_latex/sailzzeros.tex +++ /dev/null @@ -1 +0,0 @@ -val zeros : forall 'n, 'n >= 0 . unit -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/commands.tex b/cheri/sail_latexcc/commands.tex deleted file mode 100644 index 8b9678a1..00000000 --- a/cheri/sail_latexcc/commands.tex +++ /dev/null @@ -1,544 +0,0 @@ -\newcommand{\sailccsailccregderefv}{\label{zregzyderef} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccregderefv.tex}} - -\newcommand{\sailccregderef}{\label{zzyregzyderef} \lstinputlisting[language=sail]{sail_latexcc/sailccregderef.tex}} - -\newcommand{\sailcceqbittwo}{\label{zeqzybittwo} \lstinputlisting[language=sail]{sail_latexcc/sailcceqbittwo.tex}} - -\newcommand{\sailccsailccsailccsailcczeightoperatorzzerozJzJzninevvv}{\label{zzeightoperatorzzerozJzJznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccsailccsailcczeightoperatorzzerozJzJzninevvv.tex}} - -\newcommand{\sailccdiv}{\label{zdiv} \lstinputlisting[language=sail]{sail_latexcc/sailccdiv.tex}} - -\newcommand{\sailccsailccsailcczeightoperatorzzerozFzninevv}{\label{zzeightoperatorzzerozFznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccsailcczeightoperatorzzerozFzninevv.tex}} - -\newcommand{\sailccmod}{\label{zmod} \lstinputlisting[language=sail]{sail_latexcc/sailccmod.tex}} - -\newcommand{\sailccsailccsailcczeightoperatorzzerozfivezninevv}{\label{zzeightoperatorzzerozfiveznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccsailcczeightoperatorzzerozfivezninevv.tex}} - -\newcommand{\sailccabsatom}{\label{zabszyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccabsatom.tex}} - -\newcommand{\sailccnotbool}{\label{znotzybool} \lstinputlisting[language=sail]{sail_latexcc/sailccnotbool.tex}} - -\newcommand{\sailccandbool}{\label{zandzybool} \lstinputlisting[language=sail]{sail_latexcc/sailccandbool.tex}} - -\newcommand{\sailccorbool}{\label{zorzybool} \lstinputlisting[language=sail]{sail_latexcc/sailccorbool.tex}} - -\newcommand{\sailcceqatom}{\label{zeqzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailcceqatom.tex}} - -\newcommand{\sailccneqatom}{\label{zneqzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccneqatom.tex}} - -\newcommand{\sailccfnneqatom}{\label{zneqzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccfnneqatom.tex}} - -\newcommand{\sailcclteqatom}{\label{zlteqzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailcclteqatom.tex}} - -\newcommand{\sailccgteqatom}{\label{zgteqzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccgteqatom.tex}} - -\newcommand{\sailccltatom}{\label{zltzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccltatom.tex}} - -\newcommand{\sailccgtatom}{\label{zgtzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccgtatom.tex}} - -\newcommand{\sailccltrangeatom}{\label{zltzyrangezyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccltrangeatom.tex}} - -\newcommand{\sailcclteqrangeatom}{\label{zlteqzyrangezyatom} \lstinputlisting[language=sail]{sail_latexcc/sailcclteqrangeatom.tex}} - -\newcommand{\sailccgtrangeatom}{\label{zgtzyrangezyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccgtrangeatom.tex}} - -\newcommand{\sailccgteqrangeatom}{\label{zgteqzyrangezyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccgteqrangeatom.tex}} - -\newcommand{\sailccltatomrange}{\label{zltzyatomzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccltatomrange.tex}} - -\newcommand{\sailcclteqatomrange}{\label{zlteqzyatomzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailcclteqatomrange.tex}} - -\newcommand{\sailccgtatomrange}{\label{zgtzyatomzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccgtatomrange.tex}} - -\newcommand{\sailccgteqatomrange}{\label{zgteqzyatomzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccgteqatomrange.tex}} - -\newcommand{\sailcceqrange}{\label{zeqzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailcceqrange.tex}} - -\newcommand{\sailcceqint}{\label{zeqzyint} \lstinputlisting[language=sail]{sail_latexcc/sailcceqint.tex}} - -\newcommand{\sailcceqbool}{\label{zeqzybool} \lstinputlisting[language=sail]{sail_latexcc/sailcceqbool.tex}} - -\newcommand{\sailccneqrange}{\label{zneqzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccneqrange.tex}} - -\newcommand{\sailccfnneqrange}{\label{zneqzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccfnneqrange.tex}} - -\newcommand{\sailccneqint}{\label{zneqzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccneqint.tex}} - -\newcommand{\sailccfnneqint}{\label{zneqzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccfnneqint.tex}} - -\newcommand{\sailccneqbool}{\label{zneqzybool} \lstinputlisting[language=sail]{sail_latexcc/sailccneqbool.tex}} - -\newcommand{\sailccfnneqbool}{\label{zneqzybool} \lstinputlisting[language=sail]{sail_latexcc/sailccfnneqbool.tex}} - -\newcommand{\sailcclteqint}{\label{zlteqzyint} \lstinputlisting[language=sail]{sail_latexcc/sailcclteqint.tex}} - -\newcommand{\sailccgteqint}{\label{zgteqzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccgteqint.tex}} - -\newcommand{\sailccltint}{\label{zltzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccltint.tex}} - -\newcommand{\sailccgtint}{\label{zgtzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccgtint.tex}} - -\newcommand{\sailccsailccsailcczeightoperatorzzerozJzJzninevv}{\label{zzeightoperatorzzerozJzJznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccsailcczeightoperatorzzerozJzJzninevv.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozonezJzninev}{\label{zzeightoperatorzzerozonezJznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozonezJzninev.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozUzninev}{\label{zzeightoperatorzzerozUznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozUzninev.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozsixzninev}{\label{zzeightoperatorzzerozsixznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozsixzninev.tex}} - -\newcommand{\sailcczeightoperatorzzerozIzJznine}{\label{zzeightoperatorzzerozIzJznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozIzJznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozIznine}{\label{zzeightoperatorzzerozIznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozIznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozKzJznine}{\label{zzeightoperatorzzerozKzJznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozKzJznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozKznine}{\label{zzeightoperatorzzerozKznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozKznine.tex}} - -\newcommand{\sailccaddatom}{\label{zaddzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccaddatom.tex}} - -\newcommand{\sailccaddint}{\label{zaddzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccaddint.tex}} - -\newcommand{\sailccsailccsailcczeightoperatorzzerozBzninevv}{\label{zzeightoperatorzzerozBznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccsailcczeightoperatorzzerozBzninevv.tex}} - -\newcommand{\sailccsubatom}{\label{zsubzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccsubatom.tex}} - -\newcommand{\sailccsubint}{\label{zsubzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccsubint.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozDzninev}{\label{zzeightoperatorzzerozDznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozDzninev.tex}} - -\newcommand{\sailccnegateatom}{\label{znegatezyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccnegateatom.tex}} - -\newcommand{\sailccnegateint}{\label{znegatezyint} \lstinputlisting[language=sail]{sail_latexcc/sailccnegateint.tex}} - -\newcommand{\sailccsailccnegatev}{\label{znegate} \lstinputlisting[language=sail]{sail_latexcc/sailccsailccnegatev.tex}} - -\newcommand{\sailccmultatom}{\label{zmultzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccmultatom.tex}} - -\newcommand{\sailccmultint}{\label{zmultzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccmultint.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozAzninev}{\label{zzeightoperatorzzerozAznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozAzninev.tex}} - -\newcommand{\sailccprintint}{\label{zprintzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccprintint.tex}} - -\newcommand{\sailccprerrint}{\label{zprerrzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccprerrint.tex}} - -\newcommand{\sailccshlint}{\label{zshlzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccshlint.tex}} - -\newcommand{\sailccshrint}{\label{zshrzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccshrint.tex}} - -\newcommand{\sailccdivint}{\label{zdivzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccdivint.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozFzninev}{\label{zzeightoperatorzzerozFznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozFzninev.tex}} - -\newcommand{\sailccmodint}{\label{zmodzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccmodint.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozfivezninev}{\label{zzeightoperatorzzerozfiveznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozfivezninev.tex}} - -\newcommand{\sailccabsint}{\label{zabszyint} \lstinputlisting[language=sail]{sail_latexcc/sailccabsint.tex}} - -\newcommand{\sailccisnone}{\label{ziszynone} \lstinputlisting[language=sail]{sail_latexcc/sailccisnone.tex}} - -\newcommand{\sailccfnisnone}{\label{ziszynone} \lstinputlisting[language=sail]{sail_latexcc/sailccfnisnone.tex}} - -\newcommand{\sailccissome}{\label{ziszysome} \lstinputlisting[language=sail]{sail_latexcc/sailccissome.tex}} - -\newcommand{\sailccfnissome}{\label{ziszysome} \lstinputlisting[language=sail]{sail_latexcc/sailccfnissome.tex}} - -\newcommand{\sailccbits}{\label{zbits} \lstinputlisting[language=sail]{sail_latexcc/sailccbits.tex}} - -\newcommand{\sailcceqbit}{\label{zeqzybit} \lstinputlisting[language=sail]{sail_latexcc/sailcceqbit.tex}} - -\newcommand{\sailcceqbits}{\label{zeqzybits} \lstinputlisting[language=sail]{sail_latexcc/sailcceqbits.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozJzJzninev}{\label{zzeightoperatorzzerozJzJznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozJzJzninev.tex}} - -\newcommand{\sailccbitvectorlength}{\label{zbitvectorzylength} \lstinputlisting[language=sail]{sail_latexcc/sailccbitvectorlength.tex}} - -\newcommand{\sailccvectorlength}{\label{zvectorzylength} \lstinputlisting[language=sail]{sail_latexcc/sailccvectorlength.tex}} - -\newcommand{\sailcclength}{\label{zlength} \lstinputlisting[language=sail]{sail_latexcc/sailcclength.tex}} - -\newcommand{\sailccsailzzeros}{\label{zsailzyzzeros} \lstinputlisting[language=sail]{sail_latexcc/sailccsailzzeros.tex}} - -\newcommand{\sailccprintbits}{\label{zprintzybits} \lstinputlisting[language=sail]{sail_latexcc/sailccprintbits.tex}} - -\newcommand{\sailccprerrbits}{\label{zprerrzybits} \lstinputlisting[language=sail]{sail_latexcc/sailccprerrbits.tex}} - -\newcommand{\sailccsailsignextend}{\label{zsailzysignzyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccsailsignextend.tex}} - -\newcommand{\sailccsailzzeroextend}{\label{zsailzyzzerozyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccsailzzeroextend.tex}} - -\newcommand{\sailcctruncate}{\label{ztruncate} \lstinputlisting[language=sail]{sail_latexcc/sailcctruncate.tex}} - -\newcommand{\sailccsailmask}{\label{zsailzymask} \lstinputlisting[language=sail]{sail_latexcc/sailccsailmask.tex}} - -\newcommand{\sailccfnsailmask}{\label{zsailzymask} \lstinputlisting[language=sail]{sail_latexcc/sailccfnsailmask.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozQzninev}{\label{zzeightoperatorzzerozQznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozQzninev.tex}} - -\newcommand{\sailccbitvectorconcat}{\label{zbitvectorzyconcat} \lstinputlisting[language=sail]{sail_latexcc/sailccbitvectorconcat.tex}} - -\newcommand{\sailccappend}{\label{zappend} \lstinputlisting[language=sail]{sail_latexcc/sailccappend.tex}} - -\newcommand{\sailccappendsixfour}{\label{zappendzysixfour} \lstinputlisting[language=sail]{sail_latexcc/sailccappendsixfour.tex}} - -\newcommand{\sailccbitvectoraccess}{\label{zbitvectorzyaccess} \lstinputlisting[language=sail]{sail_latexcc/sailccbitvectoraccess.tex}} - -\newcommand{\sailccplainvectoraccess}{\label{zplainzyvectorzyaccess} \lstinputlisting[language=sail]{sail_latexcc/sailccplainvectoraccess.tex}} - -\newcommand{\sailccvectoraccess}{\label{zvectorzyaccess} \lstinputlisting[language=sail]{sail_latexcc/sailccvectoraccess.tex}} - -\newcommand{\sailccbitvectorupdate}{\label{zbitvectorzyupdate} \lstinputlisting[language=sail]{sail_latexcc/sailccbitvectorupdate.tex}} - -\newcommand{\sailccplainvectorupdate}{\label{zplainzyvectorzyupdate} \lstinputlisting[language=sail]{sail_latexcc/sailccplainvectorupdate.tex}} - -\newcommand{\sailccvectorupdate}{\label{zvectorzyupdate} \lstinputlisting[language=sail]{sail_latexcc/sailccvectorupdate.tex}} - -\newcommand{\sailccaddbits}{\label{zaddzybits} \lstinputlisting[language=sail]{sail_latexcc/sailccaddbits.tex}} - -\newcommand{\sailccaddbitsint}{\label{zaddzybitszyint} \lstinputlisting[language=sail]{sail_latexcc/sailccaddbitsint.tex}} - -\newcommand{\sailccsailcczeightoperatorzzerozBzninev}{\label{zzeightoperatorzzerozBznine} \lstinputlisting[language=sail]{sail_latexcc/sailccsailcczeightoperatorzzerozBzninev.tex}} - -\newcommand{\sailccvectorsubrange}{\label{zvectorzysubrange} \lstinputlisting[language=sail]{sail_latexcc/sailccvectorsubrange.tex}} - -\newcommand{\sailccvectorupdatesubrange}{\label{zvectorzyupdatezysubrange} \lstinputlisting[language=sail]{sail_latexcc/sailccvectorupdatesubrange.tex}} - -\newcommand{\sailccgetsliceint}{\label{zgetzyslicezyint} \lstinputlisting[language=sail]{sail_latexcc/sailccgetsliceint.tex}} - -\newcommand{\sailccsetsliceint}{\label{zsetzyslicezyint} \lstinputlisting[language=sail]{sail_latexcc/sailccsetsliceint.tex}} - -\newcommand{\sailccsetslicebits}{\label{zsetzyslicezybits} \lstinputlisting[language=sail]{sail_latexcc/sailccsetslicebits.tex}} - -\newcommand{\sailccslice}{\label{zslice} \lstinputlisting[language=sail]{sail_latexcc/sailccslice.tex}} - -\newcommand{\sailccreplicatebits}{\label{zreplicatezybits} \lstinputlisting[language=sail]{sail_latexcc/sailccreplicatebits.tex}} - -\newcommand{\sailccunsigned}{\label{zunsigned} \lstinputlisting[language=sail]{sail_latexcc/sailccunsigned.tex}} - -\newcommand{\sailccsigned}{\label{zsigned} \lstinputlisting[language=sail]{sail_latexcc/sailccsigned.tex}} - -\newcommand{\sailcceqanything}{\label{zeqzyanything} \lstinputlisting[language=sail]{sail_latexcc/sailcceqanything.tex}} - -\newcommand{\sailcczeightoperatorzzerozJzJznine}{\label{zzeightoperatorzzerozJzJznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozJzJznine.tex}} - -\newcommand{\sailccnotvec}{\label{znotzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccnotvec.tex}} - -\newcommand{\sailcczW}{\label{zzW} \lstinputlisting[language=sail]{sail_latexcc/sailcczW.tex}} - -\newcommand{\sailccnot}{\label{znot} \lstinputlisting[language=sail]{sail_latexcc/sailccnot.tex}} - -\newcommand{\sailccneqvec}{\label{zneqzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccneqvec.tex}} - -\newcommand{\sailccfnneqvec}{\label{zneqzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccfnneqvec.tex}} - -\newcommand{\sailccneqanything}{\label{zneqzyanything} \lstinputlisting[language=sail]{sail_latexcc/sailccneqanything.tex}} - -\newcommand{\sailccfnneqanything}{\label{zneqzyanything} \lstinputlisting[language=sail]{sail_latexcc/sailccfnneqanything.tex}} - -\newcommand{\sailcczeightoperatorzzerozonezJznine}{\label{zzeightoperatorzzerozonezJznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozonezJznine.tex}} - -\newcommand{\sailccandbits}{\label{zandzybits} \lstinputlisting[language=sail]{sail_latexcc/sailccandbits.tex}} - -\newcommand{\sailcczeightoperatorzzerozsixznine}{\label{zzeightoperatorzzerozsixznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozsixznine.tex}} - -\newcommand{\sailccorbits}{\label{zorzybits} \lstinputlisting[language=sail]{sail_latexcc/sailccorbits.tex}} - -\newcommand{\sailcczeightoperatorzzerozUznine}{\label{zzeightoperatorzzerozUznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozUznine.tex}} - -\newcommand{\sailcccastunitvec}{\label{zcastzyunitzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailcccastunitvec.tex}} - -\newcommand{\sailccfncastunitvec}{\label{zcastzyunitzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccfncastunitvec.tex}} - -\newcommand{\sailccprint}{\label{zprint} \lstinputlisting[language=sail]{sail_latexcc/sailccprint.tex}} - -\newcommand{\sailccprerrendline}{\label{zprerrzyendline} \lstinputlisting[language=sail]{sail_latexcc/sailccprerrendline.tex}} - -\newcommand{\sailccprerrstring}{\label{zprerrzystring} \lstinputlisting[language=sail]{sail_latexcc/sailccprerrstring.tex}} - -\newcommand{\sailccputchar}{\label{zputchar} \lstinputlisting[language=sail]{sail_latexcc/sailccputchar.tex}} - -\newcommand{\sailccconcatstr}{\label{zconcatzystr} \lstinputlisting[language=sail]{sail_latexcc/sailccconcatstr.tex}} - -\newcommand{\sailccstringofint}{\label{zstringzyofzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccstringofint.tex}} - -\newcommand{\sailccBitStr}{\label{zBitStr} \lstinputlisting[language=sail]{sail_latexcc/sailccBitStr.tex}} - -\newcommand{\sailccxorvec}{\label{zxorzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccxorvec.tex}} - -\newcommand{\sailccintpower}{\label{zintzypower} \lstinputlisting[language=sail]{sail_latexcc/sailccintpower.tex}} - -\newcommand{\sailcczeightoperatorzzerozQznine}{\label{zzeightoperatorzzerozQznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozQznine.tex}} - -\newcommand{\sailccaddrange}{\label{zaddzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccaddrange.tex}} - -\newcommand{\sailccaddvec}{\label{zaddzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccaddvec.tex}} - -\newcommand{\sailccaddvecint}{\label{zaddzyveczyint} \lstinputlisting[language=sail]{sail_latexcc/sailccaddvecint.tex}} - -\newcommand{\sailcczeightoperatorzzerozBznine}{\label{zzeightoperatorzzerozBznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozBznine.tex}} - -\newcommand{\sailccsubrange}{\label{zsubzyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccsubrange.tex}} - -\newcommand{\sailccsubvec}{\label{zsubzyvec} \lstinputlisting[language=sail]{sail_latexcc/sailccsubvec.tex}} - -\newcommand{\sailccsubvecint}{\label{zsubzyveczyint} \lstinputlisting[language=sail]{sail_latexcc/sailccsubvecint.tex}} - -\newcommand{\sailccnegaterange}{\label{znegatezyrange} \lstinputlisting[language=sail]{sail_latexcc/sailccnegaterange.tex}} - -\newcommand{\sailcczeightoperatorzzerozDznine}{\label{zzeightoperatorzzerozDznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozDznine.tex}} - -\newcommand{\sailccnegate}{\label{znegate} \lstinputlisting[language=sail]{sail_latexcc/sailccnegate.tex}} - -\newcommand{\sailcczeightoperatorzzerozAznine}{\label{zzeightoperatorzzerozAznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozAznine.tex}} - -\newcommand{\sailccquotientnat}{\label{zquotientzynat} \lstinputlisting[language=sail]{sail_latexcc/sailccquotientnat.tex}} - -\newcommand{\sailccquotient}{\label{zquotient} \lstinputlisting[language=sail]{sail_latexcc/sailccquotient.tex}} - -\newcommand{\sailcczeightoperatorzzerozFznine}{\label{zzeightoperatorzzerozFznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozFznine.tex}} - -\newcommand{\sailccquotroundzzero}{\label{zquotzyroundzyzzero} \lstinputlisting[language=sail]{sail_latexcc/sailccquotroundzzero.tex}} - -\newcommand{\sailccremroundzzero}{\label{zremzyroundzyzzero} \lstinputlisting[language=sail]{sail_latexcc/sailccremroundzzero.tex}} - -\newcommand{\sailccmodulus}{\label{zmodulus} \lstinputlisting[language=sail]{sail_latexcc/sailccmodulus.tex}} - -\newcommand{\sailcczeightoperatorzzerozfiveznine}{\label{zzeightoperatorzzerozfiveznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozfiveznine.tex}} - -\newcommand{\sailccminnat}{\label{zminzynat} \lstinputlisting[language=sail]{sail_latexcc/sailccminnat.tex}} - -\newcommand{\sailccminint}{\label{zminzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccminint.tex}} - -\newcommand{\sailccmaxnat}{\label{zmaxzynat} \lstinputlisting[language=sail]{sail_latexcc/sailccmaxnat.tex}} - -\newcommand{\sailccmaxint}{\label{zmaxzyint} \lstinputlisting[language=sail]{sail_latexcc/sailccmaxint.tex}} - -\newcommand{\sailccminatom}{\label{zminzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccminatom.tex}} - -\newcommand{\sailccmaxatom}{\label{zmaxzyatom} \lstinputlisting[language=sail]{sail_latexcc/sailccmaxatom.tex}} - -\newcommand{\sailccmin}{\label{zmin} \lstinputlisting[language=sail]{sail_latexcc/sailccmin.tex}} - -\newcommand{\sailccmax}{\label{zmax} \lstinputlisting[language=sail]{sail_latexcc/sailccmax.tex}} - -\newcommand{\sailccWriteRAM}{\label{zzyzyWriteRAM} \lstinputlisting[language=sail]{sail_latexcc/sailccWriteRAM.tex}} - -\newcommand{\sailccMIPSwrite}{\label{zzyzyMIPSzywrite} \lstinputlisting[language=sail]{sail_latexcc/sailccMIPSwrite.tex}} - -\newcommand{\sailccfnMIPSwrite}{\label{zzyzyMIPSzywrite} \lstinputlisting[language=sail]{sail_latexcc/sailccfnMIPSwrite.tex}} - -\newcommand{\sailccReadRAM}{\label{zzyzyReadRAM} \lstinputlisting[language=sail]{sail_latexcc/sailccReadRAM.tex}} - -\newcommand{\sailccMIPSread}{\label{zzyzyMIPSzyread} \lstinputlisting[language=sail]{sail_latexcc/sailccMIPSread.tex}} - -\newcommand{\sailccfnMIPSread}{\label{zzyzyMIPSzyread} \lstinputlisting[language=sail]{sail_latexcc/sailccfnMIPSread.tex}} - -\newcommand{\sailcczeightoperatorzzerozQzQznine}{\label{zzeightoperatorzzerozQzQznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozQzQznine.tex}} - -\newcommand{\sailccfnzeightoperatorzzerozQzQznine}{\label{zzeightoperatorzzerozQzQznine} \lstinputlisting[language=sail]{sail_latexcc/sailccfnzeightoperatorzzerozQzQznine.tex}} - -\newcommand{\sailccpowtwo}{\label{zpowtwo} \lstinputlisting[language=sail]{sail_latexcc/sailccpowtwo.tex}} - -\newcommand{\sailccmipssignextend}{\label{zmipszysignzyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccmipssignextend.tex}} - -\newcommand{\sailccmipszzeroextend}{\label{zmipszyzzerozyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccmipszzeroextend.tex}} - -\newcommand{\sailccfnmipssignextend}{\label{zmipszysignzyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccfnmipssignextend.tex}} - -\newcommand{\sailccfnmipszzeroextend}{\label{zmipszyzzerozyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccfnmipszzeroextend.tex}} - -\newcommand{\sailccsignextend}{\label{zsignzyextend} \lstinputlisting[language=sail]{sail_latexcc/sailccsignextend.tex}} - -\newcommand{\sailcczzeroextend}{\label{zzzerozyextend} \lstinputlisting[language=sail]{sail_latexcc/sailcczzeroextend.tex}} - -\newcommand{\sailcczzeros}{\label{zzzeros} \lstinputlisting[language=sail]{sail_latexcc/sailcczzeros.tex}} - -\newcommand{\sailccfnzzeros}{\label{zzzeros} \lstinputlisting[language=sail]{sail_latexcc/sailccfnzzeros.tex}} - -\newcommand{\sailccones}{\label{zones} \lstinputlisting[language=sail]{sail_latexcc/sailccones.tex}} - -\newcommand{\sailccfnones}{\label{zones} \lstinputlisting[language=sail]{sail_latexcc/sailccfnones.tex}} - -\newcommand{\sailcczeightoperatorzzerozIsznine}{\label{zzeightoperatorzzerozIzysznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozIsznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozKzJsznine}{\label{zzeightoperatorzzerozKzJzysznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozKzJsznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozIuznine}{\label{zzeightoperatorzzerozIzyuznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozIuznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozKzJuznine}{\label{zzeightoperatorzzerozKzJzyuznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozKzJuznine.tex}} - -\newcommand{\sailccfnzeightoperatorzzerozIsznine}{\label{zzeightoperatorzzerozIzysznine} \lstinputlisting[language=sail]{sail_latexcc/sailccfnzeightoperatorzzerozIsznine.tex}} - -\newcommand{\sailccfnzeightoperatorzzerozKzJsznine}{\label{zzeightoperatorzzerozKzJzysznine} \lstinputlisting[language=sail]{sail_latexcc/sailccfnzeightoperatorzzerozKzJsznine.tex}} - -\newcommand{\sailccfnzeightoperatorzzerozIuznine}{\label{zzeightoperatorzzerozIzyuznine} \lstinputlisting[language=sail]{sail_latexcc/sailccfnzeightoperatorzzerozIuznine.tex}} - -\newcommand{\sailccfnzeightoperatorzzerozKzJuznine}{\label{zzeightoperatorzzerozKzJzyuznine} \lstinputlisting[language=sail]{sail_latexcc/sailccfnzeightoperatorzzerozKzJuznine.tex}} - -\newcommand{\sailccbooltobits}{\label{zboolzytozybits} \lstinputlisting[language=sail]{sail_latexcc/sailccbooltobits.tex}} - -\newcommand{\sailccfnbooltobits}{\label{zboolzytozybits} \lstinputlisting[language=sail]{sail_latexcc/sailccfnbooltobits.tex}} - -\newcommand{\sailccbittobool}{\label{zbitzytozybool} \lstinputlisting[language=sail]{sail_latexcc/sailccbittobool.tex}} - -\newcommand{\sailccfnbittobool}{\label{zbitzytozybool} \lstinputlisting[language=sail]{sail_latexcc/sailccfnbittobool.tex}} - -\newcommand{\sailccbitstobool}{\label{zbitszytozybool} \lstinputlisting[language=sail]{sail_latexcc/sailccbitstobool.tex}} - -\newcommand{\sailccfnbitstobool}{\label{zbitszytozybool} \lstinputlisting[language=sail]{sail_latexcc/sailccfnbitstobool.tex}} - -\newcommand{\sailccshiftbitsright}{\label{zshiftzybitszyright} \lstinputlisting[language=sail]{sail_latexcc/sailccshiftbitsright.tex}} - -\newcommand{\sailccshiftbitsleft}{\label{zshiftzybitszyleft} \lstinputlisting[language=sail]{sail_latexcc/sailccshiftbitsleft.tex}} - -\newcommand{\sailccshiftl}{\label{zshiftl} \lstinputlisting[language=sail]{sail_latexcc/sailccshiftl.tex}} - -\newcommand{\sailccshiftr}{\label{zshiftr} \lstinputlisting[language=sail]{sail_latexcc/sailccshiftr.tex}} - -\newcommand{\sailcczeightoperatorzzerozKzKznine}{\label{zzeightoperatorzzerozKzKznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozKzKznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozIzIznine}{\label{zzeightoperatorzzerozIzIznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozIzIznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozKzKsznine}{\label{zzeightoperatorzzerozKzKzysznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozKzKsznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozAsznine}{\label{zzeightoperatorzzerozAzysznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozAsznine.tex}} - -\newcommand{\sailcczeightoperatorzzerozAuznine}{\label{zzeightoperatorzzerozAzyuznine} \lstinputlisting[language=sail]{sail_latexcc/sailcczeightoperatorzzerozAuznine.tex}} - -\newcommand{\sailcctobits}{\label{ztozybits} -\function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. -\lstinputlisting[language=sail]{sail_latexcc/sailcctobits.tex}} - -\newcommand{\sailccfntobits}{\label{ztozybits} \lstinputlisting[language=sail]{sail_latexcc/sailccfntobits.tex}} - -\newcommand{\sailccmask}{\label{zmask} \lstinputlisting[language=sail]{sail_latexcc/sailccmask.tex}} - -\newcommand{\sailccfnmask}{\label{zmask} \lstinputlisting[language=sail]{sail_latexcc/sailccfnmask.tex}} - -\newcommand{\sailccgettimens}{\label{zgetzytimezyns} \lstinputlisting[language=sail]{sail_latexcc/sailccgettimens.tex}} - -\newcommand{\sailccCapLen}{\label{zCapLen} \lstinputlisting[language=sail]{sail_latexcc/sailccCapLen.tex}} - -\newcommand{\sailccuintsixfour}{\label{zuintsixfour} \lstinputlisting[language=sail]{sail_latexcc/sailccuintsixfour.tex}} - -\newcommand{\sailccCPtrCmpOp}{\label{zCPtrCmpOp} \lstinputlisting[language=sail]{sail_latexcc/sailccCPtrCmpOp.tex}} - -\newcommand{\sailccCPtrCmpOpofnum}{\label{zCPtrCmpOpzyofzynum} \lstinputlisting[language=sail]{sail_latexcc/sailccCPtrCmpOpofnum.tex}} - -\newcommand{\sailccfnCPtrCmpOpofnum}{\label{zCPtrCmpOpzyofzynum} \lstinputlisting[language=sail]{sail_latexcc/sailccfnCPtrCmpOpofnum.tex}} - -\newcommand{\sailccnumofCPtrCmpOp}{\label{znumzyofzyCPtrCmpOp} \lstinputlisting[language=sail]{sail_latexcc/sailccnumofCPtrCmpOp.tex}} - -\newcommand{\sailccfnnumofCPtrCmpOp}{\label{znumzyofzyCPtrCmpOp} \lstinputlisting[language=sail]{sail_latexcc/sailccfnnumofCPtrCmpOp.tex}} - -\newcommand{\sailccClearRegSet}{\label{zClearRegSet} \lstinputlisting[language=sail]{sail_latexcc/sailccClearRegSet.tex}} - -\newcommand{\sailccClearRegSetofnum}{\label{zClearRegSetzyofzynum} \lstinputlisting[language=sail]{sail_latexcc/sailccClearRegSetofnum.tex}} - -\newcommand{\sailccfnClearRegSetofnum}{\label{zClearRegSetzyofzynum} \lstinputlisting[language=sail]{sail_latexcc/sailccfnClearRegSetofnum.tex}} - -\newcommand{\sailccnumofClearRegSet}{\label{znumzyofzyClearRegSet} \lstinputlisting[language=sail]{sail_latexcc/sailccnumofClearRegSet.tex}} - -\newcommand{\sailccfnnumofClearRegSet}{\label{znumzyofzyClearRegSet} \lstinputlisting[language=sail]{sail_latexcc/sailccfnnumofClearRegSet.tex}} - -\newcommand{\sailccCapReg}{\label{zCapReg} \lstinputlisting[language=sail]{sail_latexcc/sailccCapReg.tex}} - -\newcommand{\sailccCapStruct}{\label{zCapStruct} \lstinputlisting[language=sail]{sail_latexcc/sailccCapStruct.tex}} - -\newcommand{\sailcccapRegToCapStruct}{\label{zcapRegToCapStruct} \lstinputlisting[language=sail]{sail_latexcc/sailcccapRegToCapStruct.tex}} - -\newcommand{\sailccfncapRegToCapStruct}{\label{zcapRegToCapStruct} \lstinputlisting[language=sail]{sail_latexcc/sailccfncapRegToCapStruct.tex}} - -\newcommand{\sailccgetCapHardPerms}{\label{zgetCapHardPerms} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapHardPerms.tex}} - -\newcommand{\sailccfngetCapHardPerms}{\label{zgetCapHardPerms} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapHardPerms.tex}} - -\newcommand{\sailcccapStructToMemBitsonetwoeight}{\label{zcapStructToMemBitsonetwoeight} \lstinputlisting[language=sail]{sail_latexcc/sailcccapStructToMemBitsonetwoeight.tex}} - -\newcommand{\sailccfncapStructToMemBitsonetwoeight}{\label{zcapStructToMemBitsonetwoeight} \lstinputlisting[language=sail]{sail_latexcc/sailccfncapStructToMemBitsonetwoeight.tex}} - -\newcommand{\sailcccapStructToCapReg}{\label{zcapStructToCapReg} \lstinputlisting[language=sail]{sail_latexcc/sailcccapStructToCapReg.tex}} - -\newcommand{\sailccfncapStructToCapReg}{\label{zcapStructToCapReg} \lstinputlisting[language=sail]{sail_latexcc/sailccfncapStructToCapReg.tex}} - -\newcommand{\sailccmemBitsToCapBitsonetwoeight}{\label{zmemBitsToCapBitsonetwoeight} \lstinputlisting[language=sail]{sail_latexcc/sailccmemBitsToCapBitsonetwoeight.tex}} - -\newcommand{\sailccfnmemBitsToCapBitsonetwoeight}{\label{zmemBitsToCapBitsonetwoeight} \lstinputlisting[language=sail]{sail_latexcc/sailccfnmemBitsToCapBitsonetwoeight.tex}} - -\newcommand{\sailcccapStructToMemBits}{\label{zcapStructToMemBits} \lstinputlisting[language=sail]{sail_latexcc/sailcccapStructToMemBits.tex}} - -\newcommand{\sailccfncapStructToMemBits}{\label{zcapStructToMemBits} \lstinputlisting[language=sail]{sail_latexcc/sailccfncapStructToMemBits.tex}} - -\newcommand{\sailccmemBitsToCapBits}{\label{zmemBitsToCapBits} \lstinputlisting[language=sail]{sail_latexcc/sailccmemBitsToCapBits.tex}} - -\newcommand{\sailccfnmemBitsToCapBits}{\label{zmemBitsToCapBits} \lstinputlisting[language=sail]{sail_latexcc/sailccfnmemBitsToCapBits.tex}} - -\newcommand{\sailccgetCapPerms}{\label{zgetCapPerms} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapPerms.tex}} - -\newcommand{\sailccfngetCapPerms}{\label{zgetCapPerms} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapPerms.tex}} - -\newcommand{\sailccsetCapPerms}{\label{zsetCapPerms} \lstinputlisting[language=sail]{sail_latexcc/sailccsetCapPerms.tex}} - -\newcommand{\sailccfnsetCapPerms}{\label{zsetCapPerms} \lstinputlisting[language=sail]{sail_latexcc/sailccfnsetCapPerms.tex}} - -\newcommand{\sailccsealCap}{\label{zsealCap} \lstinputlisting[language=sail]{sail_latexcc/sailccsealCap.tex}} - -\newcommand{\sailccfnsealCap}{\label{zsealCap} \lstinputlisting[language=sail]{sail_latexcc/sailccfnsealCap.tex}} - -\newcommand{\sailccatopcorrection}{\label{zazytopzycorrection} \lstinputlisting[language=sail]{sail_latexcc/sailccatopcorrection.tex}} - -\newcommand{\sailccfnatopcorrection}{\label{zazytopzycorrection} \lstinputlisting[language=sail]{sail_latexcc/sailccfnatopcorrection.tex}} - -\newcommand{\sailccgetCapBase}{\label{zgetCapBase} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapBase.tex}} - -\newcommand{\sailccfngetCapBase}{\label{zgetCapBase} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapBase.tex}} - -\newcommand{\sailccgetCapTop}{\label{zgetCapTop} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapTop.tex}} - -\newcommand{\sailccfngetCapTop}{\label{zgetCapTop} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapTop.tex}} - -\newcommand{\sailccgetCapOffset}{\label{zgetCapOffset} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapOffset.tex}} - -\newcommand{\sailccfngetCapOffset}{\label{zgetCapOffset} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapOffset.tex}} - -\newcommand{\sailccgetCapLength}{\label{zgetCapLength} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapLength.tex}} - -\newcommand{\sailccfngetCapLength}{\label{zgetCapLength} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapLength.tex}} - -\newcommand{\sailccgetCapCursor}{\label{zgetCapCursor} \lstinputlisting[language=sail]{sail_latexcc/sailccgetCapCursor.tex}} - -\newcommand{\sailccfngetCapCursor}{\label{zgetCapCursor} \lstinputlisting[language=sail]{sail_latexcc/sailccfngetCapCursor.tex}} - -\newcommand{\sailccfastRepCheck}{\label{zfastRepCheck} \lstinputlisting[language=sail]{sail_latexcc/sailccfastRepCheck.tex}} - -\newcommand{\sailccfnfastRepCheck}{\label{zfastRepCheck} \lstinputlisting[language=sail]{sail_latexcc/sailccfnfastRepCheck.tex}} - -\newcommand{\sailccsetCapOffset}{\label{zsetCapOffset} \lstinputlisting[language=sail]{sail_latexcc/sailccsetCapOffset.tex}} - -\newcommand{\sailccfnsetCapOffset}{\label{zsetCapOffset} \lstinputlisting[language=sail]{sail_latexcc/sailccfnsetCapOffset.tex}} - -\newcommand{\sailccincCapOffset}{\label{zincCapOffset} \lstinputlisting[language=sail]{sail_latexcc/sailccincCapOffset.tex}} - -\newcommand{\sailccfnincCapOffset}{\label{zincCapOffset} \lstinputlisting[language=sail]{sail_latexcc/sailccfnincCapOffset.tex}} - -\newcommand{\sailccHighestSetBit}{\label{zHighestSetBit} \lstinputlisting[language=sail]{sail_latexcc/sailccHighestSetBit.tex}} - -\newcommand{\sailccfnHighestSetBit}{\label{zHighestSetBit} \lstinputlisting[language=sail]{sail_latexcc/sailccfnHighestSetBit.tex}} - -\newcommand{\sailccroundUp}{\label{zroundUp} \lstinputlisting[language=sail]{sail_latexcc/sailccroundUp.tex}} - -\newcommand{\sailccfnroundUp}{\label{zroundUp} \lstinputlisting[language=sail]{sail_latexcc/sailccfnroundUp.tex}} - -\newcommand{\sailcccomputeE}{\label{zcomputeE} \lstinputlisting[language=sail]{sail_latexcc/sailcccomputeE.tex}} - -\newcommand{\sailccfncomputeE}{\label{zcomputeE} \lstinputlisting[language=sail]{sail_latexcc/sailccfncomputeE.tex}} - -\newcommand{\sailccsetCapBounds}{\label{zsetCapBounds} \lstinputlisting[language=sail]{sail_latexcc/sailccsetCapBounds.tex}} - -\newcommand{\sailccfnsetCapBounds}{\label{zsetCapBounds} \lstinputlisting[language=sail]{sail_latexcc/sailccfnsetCapBounds.tex}} - -\newcommand{\sailccinttocap}{\label{zintzytozycap} \lstinputlisting[language=sail]{sail_latexcc/sailccinttocap.tex}} - -\newcommand{\sailccfninttocap}{\label{zintzytozycap} \lstinputlisting[language=sail]{sail_latexcc/sailccfninttocap.tex}} - diff --git a/cheri/sail_latexcc/sailccBitStr.tex b/cheri/sail_latexcc/sailccBitStr.tex deleted file mode 100644 index a0d408ab..00000000 --- a/cheri/sail_latexcc/sailccBitStr.tex +++ /dev/null @@ -1 +0,0 @@ -val BitStr = "string_of_bits" : forall 'n. #\hyperref[zbits]{bits}#('n) -> string diff --git a/cheri/sail_latexcc/sailccCPtrCmpOp.tex b/cheri/sail_latexcc/sailccCPtrCmpOp.tex deleted file mode 100644 index cb0a73ae..00000000 --- a/cheri/sail_latexcc/sailccCPtrCmpOp.tex +++ /dev/null @@ -1,10 +0,0 @@ -enum CPtrCmpOp = { - CEQ, - CNE, - CLT, - CLE, - CLTU, - CLEU, - CEXEQ, - CNEXEQ -} diff --git a/cheri/sail_latexcc/sailccCPtrCmpOpofnum.tex b/cheri/sail_latexcc/sailccCPtrCmpOpofnum.tex deleted file mode 100644 index bd6ca31c..00000000 --- a/cheri/sail_latexcc/sailccCPtrCmpOpofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val CPtrCmpOp_of_num : forall ('e : Int), 0 <= 'e & 'e <= 7. atom('e) -> CPtrCmpOp diff --git a/cheri/sail_latexcc/sailccCapLen.tex b/cheri/sail_latexcc/sailccCapLen.tex deleted file mode 100644 index 812f45ff..00000000 --- a/cheri/sail_latexcc/sailccCapLen.tex +++ /dev/null @@ -1 +0,0 @@ -type CapLen = range(0, 2 ^ 65) diff --git a/cheri/sail_latexcc/sailccCapReg.tex b/cheri/sail_latexcc/sailccCapReg.tex deleted file mode 100644 index 702141d9..00000000 --- a/cheri/sail_latexcc/sailccCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -type CapReg = #\hyperref[zbits]{bits}#(129) diff --git a/cheri/sail_latexcc/sailccCapStruct.tex b/cheri/sail_latexcc/sailccCapStruct.tex deleted file mode 100644 index b1df7ec5..00000000 --- a/cheri/sail_latexcc/sailccCapStruct.tex +++ /dev/null @@ -1,22 +0,0 @@ -struct CapStruct = { - tag : bool , - uperms : #\hyperref[zbits]{bits}#(4) , - access_system_regs : bool , - permit_unseal : bool , - permit_ccall : bool , - permit_seal : bool , - permit_store_local_cap : bool , - permit_store_cap : bool , - permit_load_cap : bool , - permit_store : bool , - permit_load : bool , - permit_execute : bool , - global : bool , - reserved : #\hyperref[zbits]{bits}#(2) , - E : #\hyperref[zbits]{bits}#(6) , - sealed : bool , - B : #\hyperref[zbits]{bits}#(20), - T : #\hyperref[zbits]{bits}#(20), - otype : #\hyperref[zbits]{bits}#(24), - address : #\hyperref[zbits]{bits}#(64) -} diff --git a/cheri/sail_latexcc/sailccClearRegSet.tex b/cheri/sail_latexcc/sailccClearRegSet.tex deleted file mode 100644 index c04ea7d4..00000000 --- a/cheri/sail_latexcc/sailccClearRegSet.tex +++ /dev/null @@ -1,6 +0,0 @@ -enum ClearRegSet = { -GPLo, -GPHi, -CLo, -CHi -} diff --git a/cheri/sail_latexcc/sailccClearRegSetofnum.tex b/cheri/sail_latexcc/sailccClearRegSetofnum.tex deleted file mode 100644 index c73d36d9..00000000 --- a/cheri/sail_latexcc/sailccClearRegSetofnum.tex +++ /dev/null @@ -1 +0,0 @@ -val ClearRegSet_of_num : forall ('e : Int), 0 <= 'e & 'e <= 3. atom('e) -> ClearRegSet diff --git a/cheri/sail_latexcc/sailccHighestSetBit.tex b/cheri/sail_latexcc/sailccHighestSetBit.tex deleted file mode 100644 index eb8a5e36..00000000 --- a/cheri/sail_latexcc/sailccHighestSetBit.tex +++ /dev/null @@ -1 +0,0 @@ -val HighestSetBit : forall 'N , 'N >= 2. #\hyperref[zbits]{bits}#('N) -> {'n, 0 <= 'n < 'N . (bool, atom('n))} diff --git a/cheri/sail_latexcc/sailccMIPSread.tex b/cheri/sail_latexcc/sailccMIPSread.tex deleted file mode 100644 index 92ca59cc..00000000 --- a/cheri/sail_latexcc/sailccMIPSread.tex +++ /dev/null @@ -1 +0,0 @@ -val __MIPS_read : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#(64), atom('n)) -> #\hyperref[zbits]{bits}#(8 * 'n) effect {rmem} diff --git a/cheri/sail_latexcc/sailccMIPSwrite.tex b/cheri/sail_latexcc/sailccMIPSwrite.tex deleted file mode 100644 index cc67fa20..00000000 --- a/cheri/sail_latexcc/sailccMIPSwrite.tex +++ /dev/null @@ -1 +0,0 @@ -val __MIPS_write : forall 'n. (#\hyperref[zbits]{bits}#(64), atom('n), #\hyperref[zbits]{bits}#(8 * 'n)) -> unit effect {wmv} diff --git a/cheri/sail_latexcc/sailccReadRAM.tex b/cheri/sail_latexcc/sailccReadRAM.tex deleted file mode 100644 index 68d629a6..00000000 --- a/cheri/sail_latexcc/sailccReadRAM.tex +++ /dev/null @@ -1,2 +0,0 @@ -val __ReadRAM = "read_ram" : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), #\hyperref[zbits]{bits}#('m), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#(8 * 'n) effect {rmem} diff --git a/cheri/sail_latexcc/sailccWriteRAM.tex b/cheri/sail_latexcc/sailccWriteRAM.tex deleted file mode 100644 index 2ed4aca2..00000000 --- a/cheri/sail_latexcc/sailccWriteRAM.tex +++ /dev/null @@ -1,2 +0,0 @@ -val __WriteRAM = "write_ram" : forall 'n 'm. - (atom('m), atom('n), #\hyperref[zbits]{bits}#('m), #\hyperref[zbits]{bits}#('m), #\hyperref[zbits]{bits}#(8 * 'n)) -> bool effect {wmv} diff --git a/cheri/sail_latexcc/sailccabsatom.tex b/cheri/sail_latexcc/sailccabsatom.tex deleted file mode 100644 index 5164ef32..00000000 --- a/cheri/sail_latexcc/sailccabsatom.tex +++ /dev/null @@ -1,7 +0,0 @@ -val abs_atom = { - smt : "abs", - ocaml: "abs_int", - lem: "abs_int", - c: "abs_int", - coq: "abs_with_eq" -} : forall 'n. atom('n) -> {'o, 'o = #\hyperref[zabszyatom]{abs\_atom}#('n). atom('o)} diff --git a/cheri/sail_latexcc/sailccabsint.tex b/cheri/sail_latexcc/sailccabsint.tex deleted file mode 100644 index d3b67cfb..00000000 --- a/cheri/sail_latexcc/sailccabsint.tex +++ /dev/null @@ -1,6 +0,0 @@ -val abs_int = { - smt : "abs", - ocaml: "abs_int", - lem: "abs_int", - coq: "Z.abs" -} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccaddatom.tex b/cheri/sail_latexcc/sailccaddatom.tex deleted file mode 100644 index 8b6ac810..00000000 --- a/cheri/sail_latexcc/sailccaddatom.tex +++ /dev/null @@ -1,2 +0,0 @@ -val add_atom = {ocaml: "add_int", lem: "integerAdd", c: "add_int", coq: "Z.add"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n + 'm) diff --git a/cheri/sail_latexcc/sailccaddbits.tex b/cheri/sail_latexcc/sailccaddbits.tex deleted file mode 100644 index 95f653d1..00000000 --- a/cheri/sail_latexcc/sailccaddbits.tex +++ /dev/null @@ -1,6 +0,0 @@ -val add_bits = { - ocaml: "add_vec", - lem: "add_vec", - c: "add_bits", - coq: "add_vec" -} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccaddbitsint.tex b/cheri/sail_latexcc/sailccaddbitsint.tex deleted file mode 100644 index ee9a8aa2..00000000 --- a/cheri/sail_latexcc/sailccaddbitsint.tex +++ /dev/null @@ -1,6 +0,0 @@ -val add_bits_int = { - ocaml: "add_vec_int", - lem: "add_vec_int", - c: "add_bits_int", - coq: "add_vec_int" -} : forall 'n. (#\hyperref[zbits]{bits}#('n), int) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccaddint.tex b/cheri/sail_latexcc/sailccaddint.tex deleted file mode 100644 index 9fe5b078..00000000 --- a/cheri/sail_latexcc/sailccaddint.tex +++ /dev/null @@ -1 +0,0 @@ -val add_int = {ocaml: "add_int", lem: "integerAdd", c: "add_int", coq: "Z.add"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccaddrange.tex b/cheri/sail_latexcc/sailccaddrange.tex deleted file mode 100644 index fbf498b1..00000000 --- a/cheri/sail_latexcc/sailccaddrange.tex +++ /dev/null @@ -1,2 +0,0 @@ -val add_range = {ocaml: "add_int", lem: "integerAdd", coq: "add_range", c: "add_int"} : forall 'n 'm 'o 'p. - (range('n, 'm), range('o, 'p)) -> range('n + 'o, 'm + 'p) diff --git a/cheri/sail_latexcc/sailccaddvec.tex b/cheri/sail_latexcc/sailccaddvec.tex deleted file mode 100644 index bb625afe..00000000 --- a/cheri/sail_latexcc/sailccaddvec.tex +++ /dev/null @@ -1 +0,0 @@ -val add_vec = "add_vec" : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccaddvecint.tex b/cheri/sail_latexcc/sailccaddvecint.tex deleted file mode 100644 index 189ad4aa..00000000 --- a/cheri/sail_latexcc/sailccaddvecint.tex +++ /dev/null @@ -1 +0,0 @@ -val add_vec_int = "add_vec_int" : forall 'n. (#\hyperref[zbits]{bits}#('n), int) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccandbits.tex b/cheri/sail_latexcc/sailccandbits.tex deleted file mode 100644 index 8e35bd5b..00000000 --- a/cheri/sail_latexcc/sailccandbits.tex +++ /dev/null @@ -1 +0,0 @@ -val and_bits = {c:"and_bits", _: "and_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccandbool.tex b/cheri/sail_latexcc/sailccandbool.tex deleted file mode 100644 index 926dce9f..00000000 --- a/cheri/sail_latexcc/sailccandbool.tex +++ /dev/null @@ -1 +0,0 @@ -val and_bool = {coq: "andb", _: "and_bool"} : (bool, bool) -> bool diff --git a/cheri/sail_latexcc/sailccappend.tex b/cheri/sail_latexcc/sailccappend.tex deleted file mode 100644 index 56c12116..00000000 --- a/cheri/sail_latexcc/sailccappend.tex +++ /dev/null @@ -1 +0,0 @@ -overload append = {bitvector_concat}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccappendsixfour.tex b/cheri/sail_latexcc/sailccappendsixfour.tex deleted file mode 100644 index 633593b3..00000000 --- a/cheri/sail_latexcc/sailccappendsixfour.tex +++ /dev/null @@ -1 +0,0 @@ -val "append_64" : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#(64)) -> #\hyperref[zbits]{bits}#('n + 64) diff --git a/cheri/sail_latexcc/sailccatopcorrection.tex b/cheri/sail_latexcc/sailccatopcorrection.tex deleted file mode 100644 index 13bbaf7b..00000000 --- a/cheri/sail_latexcc/sailccatopcorrection.tex +++ /dev/null @@ -1 +0,0 @@ -val a_top_correction : (bits(20), bits(20), bits(20)) -> bits(65) diff --git a/cheri/sail_latexcc/sailccbits.tex b/cheri/sail_latexcc/sailccbits.tex deleted file mode 100644 index 88255b5a..00000000 --- a/cheri/sail_latexcc/sailccbits.tex +++ /dev/null @@ -1 +0,0 @@ -type #\hyperref[zbits]{bits}# ('n : Int) = vector('n, dec, bit) diff --git a/cheri/sail_latexcc/sailccbitstobool.tex b/cheri/sail_latexcc/sailccbitstobool.tex deleted file mode 100644 index 17cb3483..00000000 --- a/cheri/sail_latexcc/sailccbitstobool.tex +++ /dev/null @@ -1 +0,0 @@ -val cast bits_to_bool : #\hyperref[zbits]{bits}#(1) -> bool diff --git a/cheri/sail_latexcc/sailccbittobool.tex b/cheri/sail_latexcc/sailccbittobool.tex deleted file mode 100644 index 13a2dfb8..00000000 --- a/cheri/sail_latexcc/sailccbittobool.tex +++ /dev/null @@ -1 +0,0 @@ -val cast bit_to_bool : bit -> bool diff --git a/cheri/sail_latexcc/sailccbitvectoraccess.tex b/cheri/sail_latexcc/sailccbitvectoraccess.tex deleted file mode 100644 index 4bb98eb8..00000000 --- a/cheri/sail_latexcc/sailccbitvectoraccess.tex +++ /dev/null @@ -1,6 +0,0 @@ -val bitvector_access = { - ocaml: "access", - lem: "access_vec_dec", - coq: "access_vec_dec", - c: "vector_access" -} : forall ('n : Int), 'n >= 0. (#\hyperref[zbits]{bits}#('n), int) -> bit diff --git a/cheri/sail_latexcc/sailccbitvectorconcat.tex b/cheri/sail_latexcc/sailccbitvectorconcat.tex deleted file mode 100644 index afc03901..00000000 --- a/cheri/sail_latexcc/sailccbitvectorconcat.tex +++ /dev/null @@ -1,2 +0,0 @@ -val bitvector_concat = {ocaml: "append", lem: "concat_vec", c: "append", coq: "concat_vec"} : forall ('n : Int) ('m : Int). - (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n + 'm) diff --git a/cheri/sail_latexcc/sailccbitvectorlength.tex b/cheri/sail_latexcc/sailccbitvectorlength.tex deleted file mode 100644 index ac601acd..00000000 --- a/cheri/sail_latexcc/sailccbitvectorlength.tex +++ /dev/null @@ -1 +0,0 @@ -val bitvector_length = {coq: "length_mword", _:"length"} : forall 'n. #\hyperref[zbits]{bits}#('n) -> atom('n) diff --git a/cheri/sail_latexcc/sailccbitvectorupdate.tex b/cheri/sail_latexcc/sailccbitvectorupdate.tex deleted file mode 100644 index 6524146e..00000000 --- a/cheri/sail_latexcc/sailccbitvectorupdate.tex +++ /dev/null @@ -1,6 +0,0 @@ -val bitvector_update = { - ocaml: "update", - lem: "update_vec_dec", - coq: "update_vec_dec", - c: "vector_update" -} : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('n), int, bit) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccbooltobits.tex b/cheri/sail_latexcc/sailccbooltobits.tex deleted file mode 100644 index 711ab763..00000000 --- a/cheri/sail_latexcc/sailccbooltobits.tex +++ /dev/null @@ -1 +0,0 @@ -val cast bool_to_bits : bool -> #\hyperref[zbits]{bits}#(1) diff --git a/cheri/sail_latexcc/sailcccapRegToCapStruct.tex b/cheri/sail_latexcc/sailcccapRegToCapStruct.tex deleted file mode 100644 index bd64d554..00000000 --- a/cheri/sail_latexcc/sailcccapRegToCapStruct.tex +++ /dev/null @@ -1 +0,0 @@ -val capRegToCapStruct : CapReg -> CapStruct diff --git a/cheri/sail_latexcc/sailcccapStructToCapReg.tex b/cheri/sail_latexcc/sailcccapStructToCapReg.tex deleted file mode 100644 index b5409845..00000000 --- a/cheri/sail_latexcc/sailcccapStructToCapReg.tex +++ /dev/null @@ -1 +0,0 @@ -val capStructToCapReg : CapStruct -> CapReg diff --git a/cheri/sail_latexcc/sailcccapStructToMemBits.tex b/cheri/sail_latexcc/sailcccapStructToMemBits.tex deleted file mode 100644 index 4a49e9c0..00000000 --- a/cheri/sail_latexcc/sailcccapStructToMemBits.tex +++ /dev/null @@ -1 +0,0 @@ -val capStructToMemBits : CapStruct -> bits(128) diff --git a/cheri/sail_latexcc/sailcccapStructToMemBitsonetwoeight.tex b/cheri/sail_latexcc/sailcccapStructToMemBitsonetwoeight.tex deleted file mode 100644 index 8f3a8d0f..00000000 --- a/cheri/sail_latexcc/sailcccapStructToMemBitsonetwoeight.tex +++ /dev/null @@ -1 +0,0 @@ -val capStructToMemBits128 : CapStruct -> bits(128) diff --git a/cheri/sail_latexcc/sailcccastunitvec.tex b/cheri/sail_latexcc/sailcccastunitvec.tex deleted file mode 100644 index e0391ded..00000000 --- a/cheri/sail_latexcc/sailcccastunitvec.tex +++ /dev/null @@ -1 +0,0 @@ -val cast cast_unit_vec : bit -> #\hyperref[zbits]{bits}#(1) diff --git a/cheri/sail_latexcc/sailcccomputeE.tex b/cheri/sail_latexcc/sailcccomputeE.tex deleted file mode 100644 index 893cea49..00000000 --- a/cheri/sail_latexcc/sailcccomputeE.tex +++ /dev/null @@ -1 +0,0 @@ -val computeE : bits(65) -> range(0, 48) effect {escape} diff --git a/cheri/sail_latexcc/sailccconcatstr.tex b/cheri/sail_latexcc/sailccconcatstr.tex deleted file mode 100644 index 07556728..00000000 --- a/cheri/sail_latexcc/sailccconcatstr.tex +++ /dev/null @@ -1 +0,0 @@ -val concat_str = {lem: "stringAppend", coq: "String.append", _: "concat_str"} : (string, string) -> string diff --git a/cheri/sail_latexcc/sailccdiv.tex b/cheri/sail_latexcc/sailccdiv.tex deleted file mode 100644 index 58318fe9..00000000 --- a/cheri/sail_latexcc/sailccdiv.tex +++ /dev/null @@ -1,7 +0,0 @@ -val div = { - smt: "div", - ocaml: "quotient", - lem: "integerDiv", - c: "tdiv_int", - coq: "div_with_eq" -} : forall 'n 'm. (atom('n), atom('m)) -> {'o, 'o = #\hyperref[zdiv]{div}#('n, 'm). atom('o)} diff --git a/cheri/sail_latexcc/sailccdivint.tex b/cheri/sail_latexcc/sailccdivint.tex deleted file mode 100644 index 34ae6121..00000000 --- a/cheri/sail_latexcc/sailccdivint.tex +++ /dev/null @@ -1,7 +0,0 @@ -val div_int = { - smt: "div", - ocaml: "quotient", - lem: "integerDiv", - c: "tdiv_int", - coq: "Z.quot" -} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailcceqanything.tex b/cheri/sail_latexcc/sailcceqanything.tex deleted file mode 100644 index 9b5d3c92..00000000 --- a/cheri/sail_latexcc/sailcceqanything.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_anything = {ocaml: "(#\hyperref[zfun]{fun}# (x, y) -> x = y)", lem: "eq", coq: "generic_eq", _:"eq_anything"} : forall ('a : Type). ('a, 'a) -> bool diff --git a/cheri/sail_latexcc/sailcceqatom.tex b/cheri/sail_latexcc/sailcceqatom.tex deleted file mode 100644 index 0325ab15..00000000 --- a/cheri/sail_latexcc/sailcceqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_atom = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latexcc/sailcceqbit.tex b/cheri/sail_latexcc/sailcceqbit.tex deleted file mode 100644 index 205d3436..00000000 --- a/cheri/sail_latexcc/sailcceqbit.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_bit = { lem : "eq", _ : "eq_bit" } : (bit, bit) -> bool diff --git a/cheri/sail_latexcc/sailcceqbits.tex b/cheri/sail_latexcc/sailcceqbits.tex deleted file mode 100644 index e78ed19a..00000000 --- a/cheri/sail_latexcc/sailcceqbits.tex +++ /dev/null @@ -1,6 +0,0 @@ -val eq_bits = { - ocaml: "eq_list", - lem: "eq_vec", - c: "eq_bits", - coq: "eq_vec" -} : forall 'n. (vector('n, dec, bit), vector('n, dec, bit)) -> bool diff --git a/cheri/sail_latexcc/sailcceqbittwo.tex b/cheri/sail_latexcc/sailcceqbittwo.tex deleted file mode 100644 index 59353940..00000000 --- a/cheri/sail_latexcc/sailcceqbittwo.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_bit2 = "eq_bit" : (bit, bit) -> bool diff --git a/cheri/sail_latexcc/sailcceqbool.tex b/cheri/sail_latexcc/sailcceqbool.tex deleted file mode 100644 index 4d2c346b..00000000 --- a/cheri/sail_latexcc/sailcceqbool.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_bool = {ocaml: "eq_bool", lem: "eq", c: "eq_bool", coq: "Bool.eqb"} : (bool, bool) -> bool diff --git a/cheri/sail_latexcc/sailcceqint.tex b/cheri/sail_latexcc/sailcceqint.tex deleted file mode 100644 index 4c0462c1..00000000 --- a/cheri/sail_latexcc/sailcceqint.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_int = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "Z.eqb"} : (int, int) -> bool diff --git a/cheri/sail_latexcc/sailcceqrange.tex b/cheri/sail_latexcc/sailcceqrange.tex deleted file mode 100644 index 7f1cd5f2..00000000 --- a/cheri/sail_latexcc/sailcceqrange.tex +++ /dev/null @@ -1 +0,0 @@ -val eq_range = {ocaml: "eq_int", lem: "eq", c: "eq_int", coq: "eq_range"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool diff --git a/cheri/sail_latexcc/sailccfastRepCheck.tex b/cheri/sail_latexcc/sailccfastRepCheck.tex deleted file mode 100644 index 2dd665fb..00000000 --- a/cheri/sail_latexcc/sailccfastRepCheck.tex +++ /dev/null @@ -1 +0,0 @@ -val fastRepCheck : (CapStruct, bits(64)) -> bool diff --git a/cheri/sail_latexcc/sailccfnCPtrCmpOpofnum.tex b/cheri/sail_latexcc/sailccfnCPtrCmpOpofnum.tex deleted file mode 100644 index 6ab563f3..00000000 --- a/cheri/sail_latexcc/sailccfnCPtrCmpOpofnum.tex +++ /dev/null @@ -1,10 +0,0 @@ -function CPtrCmpOp_of_num arg# = match arg# { - 0 => CEQ, - 1 => CNE, - 2 => CLT, - 3 => CLE, - 4 => CLTU, - 5 => CLEU, - 6 => CEXEQ, - _ => CNEXEQ -} diff --git a/cheri/sail_latexcc/sailccfnClearRegSetofnum.tex b/cheri/sail_latexcc/sailccfnClearRegSetofnum.tex deleted file mode 100644 index edfe64e3..00000000 --- a/cheri/sail_latexcc/sailccfnClearRegSetofnum.tex +++ /dev/null @@ -1,6 +0,0 @@ -function ClearRegSet_of_num arg# = match arg# { - 0 => GPLo, - 1 => GPHi, - 2 => CLo, - _ => CHi -} diff --git a/cheri/sail_latexcc/sailccfnHighestSetBit.tex b/cheri/sail_latexcc/sailccfnHighestSetBit.tex deleted file mode 100644 index dbbc5b49..00000000 --- a/cheri/sail_latexcc/sailccfnHighestSetBit.tex +++ /dev/null @@ -1,5 +0,0 @@ -function HighestSetBit x = { - foreach (i #\hyperref[zfrom]{from}# ('N - 1) to 0 by 1 in dec) - if [x[i]] == 0b1 then return (true, i); - return (false, 0) -} diff --git a/cheri/sail_latexcc/sailccfnMIPSread.tex b/cheri/sail_latexcc/sailccfnMIPSread.tex deleted file mode 100644 index ee937856..00000000 --- a/cheri/sail_latexcc/sailccfnMIPSread.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zzyzyMIPSzyread]{\_\_MIPS\_read}# (addr, width) = #\hyperref[zzyzyReadRAM]{\_\_ReadRAM}#(64, width, 0x0000_0000_0000_0000, addr) diff --git a/cheri/sail_latexcc/sailccfnMIPSwrite.tex b/cheri/sail_latexcc/sailccfnMIPSwrite.tex deleted file mode 100644 index 5e81f335..00000000 --- a/cheri/sail_latexcc/sailccfnMIPSwrite.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zzyzyMIPSzywrite]{\_\_MIPS\_write}# (addr, width, data) = let _ = #\hyperref[zzyzyWriteRAM]{\_\_WriteRAM}#(64, width, 0x0000_0000_0000_0000, addr, data) in () diff --git a/cheri/sail_latexcc/sailccfnatopcorrection.tex b/cheri/sail_latexcc/sailccfnatopcorrection.tex deleted file mode 100644 index 3a6be173..00000000 --- a/cheri/sail_latexcc/sailccfnatopcorrection.tex +++ /dev/null @@ -1,7 +0,0 @@ -function #\hyperref[zazytopzycorrection]{a\_top\_correction}#(a_mid, R, bound) : (#\hyperref[zbits]{bits}#(20), #\hyperref[zbits]{bits}#(20), #\hyperref[zbits]{bits}#(20)) -> #\hyperref[zbits]{bits}#(65) = - match (a_mid <_u R, bound <_u R) { - (false, false) => #\hyperref[zzzeros]{zeros}#(), - (false, true) => #\hyperref[zzzerozyextend]{zero\_extend}#(0b1), - (true, false) => #\hyperref[zones]{ones}#(), - (true, true) => #\hyperref[zzzeros]{zeros}#() - } diff --git a/cheri/sail_latexcc/sailccfnbitstobool.tex b/cheri/sail_latexcc/sailccfnbitstobool.tex deleted file mode 100644 index 1cb33076..00000000 --- a/cheri/sail_latexcc/sailccfnbitstobool.tex +++ /dev/null @@ -1 +0,0 @@ -function bits_to_bool x = #\hyperref[zbitzytozybool]{bit\_to\_bool}#(x[0]) diff --git a/cheri/sail_latexcc/sailccfnbittobool.tex b/cheri/sail_latexcc/sailccfnbittobool.tex deleted file mode 100644 index a5eea578..00000000 --- a/cheri/sail_latexcc/sailccfnbittobool.tex +++ /dev/null @@ -1,4 +0,0 @@ -function bit_to_bool b = match b { - bitone => true, - _ => false -} diff --git a/cheri/sail_latexcc/sailccfnbooltobits.tex b/cheri/sail_latexcc/sailccfnbooltobits.tex deleted file mode 100644 index 99075369..00000000 --- a/cheri/sail_latexcc/sailccfnbooltobits.tex +++ /dev/null @@ -1 +0,0 @@ -function bool_to_bits x = if x then 0b1 else 0b0 diff --git a/cheri/sail_latexcc/sailccfncapRegToCapStruct.tex b/cheri/sail_latexcc/sailccfncapRegToCapStruct.tex deleted file mode 100644 index 4af338b9..00000000 --- a/cheri/sail_latexcc/sailccfncapRegToCapStruct.tex +++ /dev/null @@ -1,27 +0,0 @@ -function #\hyperref[zcapRegToCapStruct]{capRegToCapStruct}#(c) : CapReg -> CapStruct = - let s : bool = c[104] in - let Bc : #\hyperref[zbits]{bits}#(20) = if s then c[103..96] @ 0x000 else c[103..84] in - let Tc : #\hyperref[zbits]{bits}#(20) = if s then c[83..76] @ 0x000 else c[83..64] in - let otype : #\hyperref[zbits]{bits}#(24) = if s then c[95..84] @ c[75..64] else #\hyperref[zzzeros]{zeros}#() in - struct { - tag = c[128], - uperms = c[127..124], - access_system_regs = c[123], - permit_unseal = c[122], - permit_ccall = c[121], - permit_seal = c[120], - permit_store_local_cap = c[119], - permit_store_cap = c[118], - permit_load_cap = c[117], - permit_store = c[116], - permit_load = c[115], - permit_execute = c[114], - global = c[113], - reserved = c[112..111], - E = c[110..105], - sealed = s, - B = Bc, - T = Tc, - otype = otype, - address = c[63..0] - } diff --git a/cheri/sail_latexcc/sailccfncapStructToCapReg.tex b/cheri/sail_latexcc/sailccfncapStructToCapReg.tex deleted file mode 100644 index f6b02365..00000000 --- a/cheri/sail_latexcc/sailccfncapStructToCapReg.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zcapStructToCapReg]{capStructToCapReg}#(cap) : CapStruct -> CapReg = - (cap.tag @ #\hyperref[zcapStructToMemBitsonetwoeight]{capStructToMemBits128}#(cap)) diff --git a/cheri/sail_latexcc/sailccfncapStructToMemBits.tex b/cheri/sail_latexcc/sailccfncapStructToMemBits.tex deleted file mode 100644 index ea19467f..00000000 --- a/cheri/sail_latexcc/sailccfncapStructToMemBits.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zcapStructToMemBits]{capStructToMemBits}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(128) = - #\hyperref[zcapStructToMemBitsonetwoeight]{capStructToMemBits128}#(cap) ^ null_cap_bits diff --git a/cheri/sail_latexcc/sailccfncapStructToMemBitsonetwoeight.tex b/cheri/sail_latexcc/sailccfncapStructToMemBitsonetwoeight.tex deleted file mode 100644 index 08da637f..00000000 --- a/cheri/sail_latexcc/sailccfncapStructToMemBitsonetwoeight.tex +++ /dev/null @@ -1,12 +0,0 @@ -function #\hyperref[zcapStructToMemBitsonetwoeight]{capStructToMemBits128}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(128) = - let b : #\hyperref[zbits]{bits}#(20) = if cap.sealed then (cap.B)[19..12] @ (cap.otype)[23..12] else cap.B in - let t : #\hyperref[zbits]{bits}#(20) = if cap.sealed then (cap.T)[19..12] @ (cap.otype)[11..0] else cap.T in - ( cap.uperms - @ #\hyperref[zgetCapHardPerms]{getCapHardPerms}#(cap) - @ cap.reserved - @ cap.E - @ cap.sealed - @ b - @ t - @ cap.address - ) diff --git a/cheri/sail_latexcc/sailccfncastunitvec.tex b/cheri/sail_latexcc/sailccfncastunitvec.tex deleted file mode 100644 index 1bb7a9e0..00000000 --- a/cheri/sail_latexcc/sailccfncastunitvec.tex +++ /dev/null @@ -1,4 +0,0 @@ -function cast_unit_vec b = match b { - bitzero => 0b0, - _ => 0b1 -} diff --git a/cheri/sail_latexcc/sailccfncomputeE.tex b/cheri/sail_latexcc/sailccfncomputeE.tex deleted file mode 100644 index ef4cb71b..00000000 --- a/cheri/sail_latexcc/sailccfncomputeE.tex +++ /dev/null @@ -1,7 +0,0 @@ -function #\hyperref[zcomputeE]{computeE}# (rlength) : #\hyperref[zbits]{bits}#(65) -> range(0, 48) = - let (nonzero, 'msb) = #\hyperref[zHighestSetBit]{HighestSetBit}#((rlength + (rlength >> 6)) >> 19) in - if nonzero then - /* above will always return <= 45 because 19 bits of zero are shifted in from right */ - {assert(0 <= msb & msb <= 45); #\hyperref[zroundUp]{roundUp}# (#\hyperref[zmin]{min}#(msb,45)) } - else - 0 diff --git a/cheri/sail_latexcc/sailccfnfastRepCheck.tex b/cheri/sail_latexcc/sailccfnfastRepCheck.tex deleted file mode 100644 index 3e4d2111..00000000 --- a/cheri/sail_latexcc/sailccfnfastRepCheck.tex +++ /dev/null @@ -1,23 +0,0 @@ -function #\hyperref[zfastRepCheck]{fastRepCheck}#(c, i) : (CapStruct, #\hyperref[zbits]{bits}#(64)) -> bool= - let 'E = #\hyperref[zunsigned]{unsigned}#(c.E) in - if (E >= 44) then - true /* in this case representable region is whole address space */ - else - let E' = #\hyperref[zmin]{min}#(E, 43) in - let i_top = #\hyperref[zsigned]{signed}#(i[63..E+20]) in - let i_mid : #\hyperref[zbits]{bits}#(20) = i[E+19..E] in - let a_mid : #\hyperref[zbits]{bits}#(20) = (c.address)[E+19..E] in - let R : #\hyperref[zbits]{bits}#(20) = (c.B) - 0x01000 in - let diff : #\hyperref[zbits]{bits}#(20) = R - a_mid in - let diff1 : #\hyperref[zbits]{bits}#(20) = diff - 1 in - /* i_top determines 1. whether the increment is inRange - i.e. less than the size of the representable region - (2**(E+20)) and 2. whether it is positive or negative. To - satisfy 1. all top bits must be the same so we are - interested in the cases i_top is 0 or -1 */ - if (i_top == 0) then - i_mid <_u diff1 - else if (i_top == -1) then - (i_mid >=_u diff) & (R != a_mid) - else - false diff --git a/cheri/sail_latexcc/sailccfngetCapBase.tex b/cheri/sail_latexcc/sailccfngetCapBase.tex deleted file mode 100644 index 51677965..00000000 --- a/cheri/sail_latexcc/sailccfngetCapBase.tex +++ /dev/null @@ -1,10 +0,0 @@ -function #\hyperref[zgetCapBase]{getCapBase}#(c) : CapStruct -> uint64 = - let E = #\hyperref[zmin]{min}#(#\hyperref[zunsigned]{unsigned}#(c.E), 48) in - let Bc : #\hyperref[zbits]{bits}#(20) = c.B in - let a : #\hyperref[zbits]{bits}#(65) = #\hyperref[zzzerozyextend]{zero\_extend}#(c.address) in - let R : #\hyperref[zbits]{bits}#(20) = Bc - 0x01000 in /* wraps */ - let a_mid : #\hyperref[zbits]{bits}#(20) = #\hyperref[zmask]{mask}#(a >> E) in - let correction = #\hyperref[zazytopzycorrection]{a\_top\_correction}#(a_mid, R, Bc) in - let a_top = a >> E+20 in - let base : #\hyperref[zbits]{bits}#(64) = #\hyperref[zmask]{mask}#(((a_top + correction) @ Bc) << E) in - #\hyperref[zunsigned]{unsigned}#(base) diff --git a/cheri/sail_latexcc/sailccfngetCapCursor.tex b/cheri/sail_latexcc/sailccfngetCapCursor.tex deleted file mode 100644 index 9f5d5757..00000000 --- a/cheri/sail_latexcc/sailccfngetCapCursor.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zgetCapCursor]{getCapCursor}#(cap) : CapStruct -> uint64 = #\hyperref[zunsigned]{unsigned}#(cap.address) diff --git a/cheri/sail_latexcc/sailccfngetCapHardPerms.tex b/cheri/sail_latexcc/sailccfngetCapHardPerms.tex deleted file mode 100644 index 0b86b980..00000000 --- a/cheri/sail_latexcc/sailccfngetCapHardPerms.tex +++ /dev/null @@ -1,12 +0,0 @@ -function #\hyperref[zgetCapHardPerms]{getCapHardPerms}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(11) = - (cap.access_system_regs - @ cap.permit_unseal - @ cap.permit_ccall - @ cap.permit_seal - @ cap.permit_store_local_cap - @ cap.permit_store_cap - @ cap.permit_load_cap - @ cap.permit_store - @ cap.permit_load - @ cap.permit_execute - @ cap.global) diff --git a/cheri/sail_latexcc/sailccfngetCapLength.tex b/cheri/sail_latexcc/sailccfngetCapLength.tex deleted file mode 100644 index e9ce6566..00000000 --- a/cheri/sail_latexcc/sailccfngetCapLength.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zgetCapLength]{getCapLength}#(c) : CapStruct -> CapLen = - let 'top = #\hyperref[zgetCapTop]{getCapTop}#(c) in - let 'base = #\hyperref[zgetCapBase]{getCapBase}#(c) in { - assert (top >= base); - top - base - } diff --git a/cheri/sail_latexcc/sailccfngetCapOffset.tex b/cheri/sail_latexcc/sailccfngetCapOffset.tex deleted file mode 100644 index 8bf83916..00000000 --- a/cheri/sail_latexcc/sailccfngetCapOffset.tex +++ /dev/null @@ -1,3 +0,0 @@ -function #\hyperref[zgetCapOffset]{getCapOffset}#(c) : CapStruct -> uint64 = - let base = #\hyperref[zgetCapBase]{getCapBase}#(c) in - (#\hyperref[zunsigned]{unsigned}#(c.address) - base) % #\hyperref[zpowtwo]{pow2}#(64) diff --git a/cheri/sail_latexcc/sailccfngetCapPerms.tex b/cheri/sail_latexcc/sailccfngetCapPerms.tex deleted file mode 100644 index 9701e163..00000000 --- a/cheri/sail_latexcc/sailccfngetCapPerms.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zgetCapPerms]{getCapPerms}#(cap) : CapStruct -> #\hyperref[zbits]{bits}#(31) = - let perms : #\hyperref[zbits]{bits}#(15) = #\hyperref[zzzerozyextend]{zero\_extend}#(#\hyperref[zgetCapHardPerms]{getCapHardPerms}#(cap)) in - (0x000 /* uperms 30-19 */ - @ cap.uperms - @ perms) diff --git a/cheri/sail_latexcc/sailccfngetCapTop.tex b/cheri/sail_latexcc/sailccfngetCapTop.tex deleted file mode 100644 index 1be5af24..00000000 --- a/cheri/sail_latexcc/sailccfngetCapTop.tex +++ /dev/null @@ -1,11 +0,0 @@ -function #\hyperref[zgetCapTop]{getCapTop}# (c) : CapStruct -> CapLen = - let E = #\hyperref[zmin]{min}#(#\hyperref[zunsigned]{unsigned}#(c.E), 48) in - let Bc : #\hyperref[zbits]{bits}#(20) = c.B in - let T : #\hyperref[zbits]{bits}#(20) = c.T in - let a : #\hyperref[zbits]{bits}#(65) = #\hyperref[zzzerozyextend]{zero\_extend}#(c.address) in - let R : #\hyperref[zbits]{bits}#(20) = Bc - 0x01000 in /* wraps */ - let a_mid : #\hyperref[zbits]{bits}#(20) = #\hyperref[zmask]{mask}#(a >> E) in - let correction = #\hyperref[zazytopzycorrection]{a\_top\_correction}#(a_mid, R, T) in - let a_top = a >> E+20 in - let top1 : #\hyperref[zbits]{bits}#(65) = #\hyperref[zmask]{mask}#((a_top + correction) @ T) in - #\hyperref[zunsigned]{unsigned}#(top1 << E) diff --git a/cheri/sail_latexcc/sailccfnincCapOffset.tex b/cheri/sail_latexcc/sailccfnincCapOffset.tex deleted file mode 100644 index 59d3237e..00000000 --- a/cheri/sail_latexcc/sailccfnincCapOffset.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zincCapOffset]{incCapOffset}#(c, delta) : (CapStruct, #\hyperref[zbits]{bits}#(64)) -> (bool, CapStruct) = - let newAddress : #\hyperref[zbits]{bits}#(64) = c.address + delta in - let newCap = { c with address = newAddress } in - let representable = #\hyperref[zfastRepCheck]{fastRepCheck}#(c, delta) in - (representable, newCap) diff --git a/cheri/sail_latexcc/sailccfninttocap.tex b/cheri/sail_latexcc/sailccfninttocap.tex deleted file mode 100644 index 31bb2bec..00000000 --- a/cheri/sail_latexcc/sailccfninttocap.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zintzytozycap]{int\_to\_cap}# (offset) : #\hyperref[zbits]{bits}#(64) -> CapStruct = - {null_cap with address = offset} diff --git a/cheri/sail_latexcc/sailccfnisnone.tex b/cheri/sail_latexcc/sailccfnisnone.tex deleted file mode 100644 index 877cc2a0..00000000 --- a/cheri/sail_latexcc/sailccfnisnone.tex +++ /dev/null @@ -1,4 +0,0 @@ -function is_none opt = match opt { - #\hyperref[zSome]{Some}#(_) => false, - #\hyperref[zNone]{None}#() => true -} diff --git a/cheri/sail_latexcc/sailccfnissome.tex b/cheri/sail_latexcc/sailccfnissome.tex deleted file mode 100644 index f1f5f655..00000000 --- a/cheri/sail_latexcc/sailccfnissome.tex +++ /dev/null @@ -1,4 +0,0 @@ -function is_some opt = match opt { - #\hyperref[zSome]{Some}#(_) => true, - #\hyperref[zNone]{None}#() => false -} diff --git a/cheri/sail_latexcc/sailccfnmask.tex b/cheri/sail_latexcc/sailccfnmask.tex deleted file mode 100644 index e62ea529..00000000 --- a/cheri/sail_latexcc/sailccfnmask.tex +++ /dev/null @@ -1 +0,0 @@ -function mask bs = bs['n - 1 .. 0] diff --git a/cheri/sail_latexcc/sailccfnmemBitsToCapBits.tex b/cheri/sail_latexcc/sailccfnmemBitsToCapBits.tex deleted file mode 100644 index 198cf984..00000000 --- a/cheri/sail_latexcc/sailccfnmemBitsToCapBits.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zmemBitsToCapBits]{memBitsToCapBits}#(tag, b) : (bool, #\hyperref[zbits]{bits}#(128)) -> #\hyperref[zbits]{bits}#(129) = - #\hyperref[zmemBitsToCapBitsonetwoeight]{memBitsToCapBits128}#(tag, b ^ null_cap_bits) diff --git a/cheri/sail_latexcc/sailccfnmemBitsToCapBitsonetwoeight.tex b/cheri/sail_latexcc/sailccfnmemBitsToCapBitsonetwoeight.tex deleted file mode 100644 index 723571e9..00000000 --- a/cheri/sail_latexcc/sailccfnmemBitsToCapBitsonetwoeight.tex +++ /dev/null @@ -1,2 +0,0 @@ -function #\hyperref[zmemBitsToCapBitsonetwoeight]{memBitsToCapBits128}#(tag, b) : (bool, #\hyperref[zbits]{bits}#(128)) -> CapReg= - (tag @ b) diff --git a/cheri/sail_latexcc/sailccfnmipssignextend.tex b/cheri/sail_latexcc/sailccfnmipssignextend.tex deleted file mode 100644 index 80945b61..00000000 --- a/cheri/sail_latexcc/sailccfnmipssignextend.tex +++ /dev/null @@ -1 +0,0 @@ -function mips_sign_extend v = #\hyperref[zsailzysignzyextend]{sail\_sign\_extend}#(v, sizeof('m)) diff --git a/cheri/sail_latexcc/sailccfnmipszzeroextend.tex b/cheri/sail_latexcc/sailccfnmipszzeroextend.tex deleted file mode 100644 index 6c9914d9..00000000 --- a/cheri/sail_latexcc/sailccfnmipszzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -function mips_zero_extend v = #\hyperref[zsailzyzzerozyextend]{sail\_zero\_extend}#(v, sizeof('m)) diff --git a/cheri/sail_latexcc/sailccfnneqanything.tex b/cheri/sail_latexcc/sailccfnneqanything.tex deleted file mode 100644 index 1605ed05..00000000 --- a/cheri/sail_latexcc/sailccfnneqanything.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyanything]{neq\_anything}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(x == y) diff --git a/cheri/sail_latexcc/sailccfnneqatom.tex b/cheri/sail_latexcc/sailccfnneqatom.tex deleted file mode 100644 index e9a9f93f..00000000 --- a/cheri/sail_latexcc/sailccfnneqatom.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyatom]{neq\_atom}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzyatom]{eq\_atom}#(x, y)) diff --git a/cheri/sail_latexcc/sailccfnneqbool.tex b/cheri/sail_latexcc/sailccfnneqbool.tex deleted file mode 100644 index 65007b8e..00000000 --- a/cheri/sail_latexcc/sailccfnneqbool.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzybool]{neq\_bool}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzybool]{eq\_bool}#(x, y)) diff --git a/cheri/sail_latexcc/sailccfnneqint.tex b/cheri/sail_latexcc/sailccfnneqint.tex deleted file mode 100644 index 952a7735..00000000 --- a/cheri/sail_latexcc/sailccfnneqint.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyint]{neq\_int}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzyint]{eq\_int}#(x, y)) diff --git a/cheri/sail_latexcc/sailccfnneqrange.tex b/cheri/sail_latexcc/sailccfnneqrange.tex deleted file mode 100644 index 43f49e9e..00000000 --- a/cheri/sail_latexcc/sailccfnneqrange.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyrange]{neq\_range}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzyrange]{eq\_range}#(x, y)) diff --git a/cheri/sail_latexcc/sailccfnneqvec.tex b/cheri/sail_latexcc/sailccfnneqvec.tex deleted file mode 100644 index c446df08..00000000 --- a/cheri/sail_latexcc/sailccfnneqvec.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zneqzyvec]{neq\_vec}# (x, y) = #\hyperref[znotzybool]{not\_bool}#(#\hyperref[zeqzybits]{eq\_bits}#(x, y)) diff --git a/cheri/sail_latexcc/sailccfnnumofCPtrCmpOp.tex b/cheri/sail_latexcc/sailccfnnumofCPtrCmpOp.tex deleted file mode 100644 index 4d20546b..00000000 --- a/cheri/sail_latexcc/sailccfnnumofCPtrCmpOp.tex +++ /dev/null @@ -1,10 +0,0 @@ -function num_of_CPtrCmpOp arg# = match arg# { - CEQ => 0, - CNE => 1, - CLT => 2, - CLE => 3, - CLTU => 4, - CLEU => 5, - CEXEQ => 6, - CNEXEQ => 7 -} diff --git a/cheri/sail_latexcc/sailccfnnumofClearRegSet.tex b/cheri/sail_latexcc/sailccfnnumofClearRegSet.tex deleted file mode 100644 index 3dd58b89..00000000 --- a/cheri/sail_latexcc/sailccfnnumofClearRegSet.tex +++ /dev/null @@ -1,6 +0,0 @@ -function num_of_ClearRegSet arg# = match arg# { - GPLo => 0, - GPHi => 1, - CLo => 2, - CHi => 3 -} diff --git a/cheri/sail_latexcc/sailccfnones.tex b/cheri/sail_latexcc/sailccfnones.tex deleted file mode 100644 index e58040d7..00000000 --- a/cheri/sail_latexcc/sailccfnones.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zones]{ones}#() = #\hyperref[zreplicatezybits]{replicate\_bits}# (0b1,'n) diff --git a/cheri/sail_latexcc/sailccfnroundUp.tex b/cheri/sail_latexcc/sailccfnroundUp.tex deleted file mode 100644 index 1ed68a59..00000000 --- a/cheri/sail_latexcc/sailccfnroundUp.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zroundUp]{roundUp}#(e) : range(0, 45) -> range(0, 48) = - let 'r = e % 4 in - if (r == 0) - then e - else (e - r + 4) diff --git a/cheri/sail_latexcc/sailccfnsailmask.tex b/cheri/sail_latexcc/sailccfnsailmask.tex deleted file mode 100644 index 37ede658..00000000 --- a/cheri/sail_latexcc/sailccfnsailmask.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zsailzymask]{sail\_mask}#(len, v) = if len <= #\hyperref[zlength]{length}#(v) then #\hyperref[ztruncate]{truncate}#(v, len) else #\hyperref[zsailzyzzerozyextend]{sail\_zero\_extend}#(v, len) diff --git a/cheri/sail_latexcc/sailccfnsealCap.tex b/cheri/sail_latexcc/sailccfnsealCap.tex deleted file mode 100644 index 55c55014..00000000 --- a/cheri/sail_latexcc/sailccfnsealCap.tex +++ /dev/null @@ -1,5 +0,0 @@ -function #\hyperref[zsealCap]{sealCap}#(cap, otype) : (CapStruct, #\hyperref[zbits]{bits}#(24)) -> (bool, CapStruct) = - if (((cap.T)[11..0] == #\hyperref[zzzeros]{zeros}#()) & ((cap.B)[11..0] == #\hyperref[zzzeros]{zeros}#())) then - (true, {cap with sealed=true, otype=otype}) - else - (false, cap /* XXX should be undefined? */ ) diff --git a/cheri/sail_latexcc/sailccfnsetCapBounds.tex b/cheri/sail_latexcc/sailccfnsetCapBounds.tex deleted file mode 100644 index 44808068..00000000 --- a/cheri/sail_latexcc/sailccfnsetCapBounds.tex +++ /dev/null @@ -1,13 +0,0 @@ -function #\hyperref[zsetCapBounds]{setCapBounds}#(cap, base, top) : (CapStruct, #\hyperref[zbits]{bits}#(64), #\hyperref[zbits]{bits}#(65)) -> (bool, CapStruct) = - /* {cap with base=base; length=(#\hyperref[zbits]{bits}#(64)) length; offset=0} */ - let 'e = #\hyperref[zcomputeE]{computeE}#(top - (0b0 @ base)) in - let Bc : #\hyperref[zbits]{bits}#(20) = #\hyperref[zmask]{mask}#(base >> e) in - let T : #\hyperref[zbits]{bits}#(20) = #\hyperref[zmask]{mask}#(top >> e) in - let e_mask : #\hyperref[zbits]{bits}#(65) = #\hyperref[zzzerozyextend]{zero\_extend}#(#\hyperref[zreplicatezybits]{replicate\_bits}#(0b1, e)) in - let e_bits = top & e_mask in - let T2 : #\hyperref[zbits]{bits}#(20) = T + (if #\hyperref[zunsigned]{unsigned}#(e_bits) == 0 then 0x00000 else 0x00001) in - let newCap = {cap with address=base, E=#\hyperref[ztozybits]{to\_bits}#(6, e), B=Bc, T=T2} in - let newBase = #\hyperref[zgetCapBase]{getCapBase}#(newCap) in - let newTop = #\hyperref[zgetCapTop]{getCapTop}#(newCap) in - let exact = (#\hyperref[zunsigned]{unsigned}#(base) == newBase) & (#\hyperref[zunsigned]{unsigned}#(top) == newTop) in - (exact, newCap) diff --git a/cheri/sail_latexcc/sailccfnsetCapOffset.tex b/cheri/sail_latexcc/sailccfnsetCapOffset.tex deleted file mode 100644 index f272f7d3..00000000 --- a/cheri/sail_latexcc/sailccfnsetCapOffset.tex +++ /dev/null @@ -1,6 +0,0 @@ -function #\hyperref[zsetCapOffset]{setCapOffset}#(c, offset) : (CapStruct, #\hyperref[zbits]{bits}#(64)) -> (bool, CapStruct) = - let base : #\hyperref[zbits]{bits}#(64) = #\hyperref[ztozybits]{to\_bits}#(64, #\hyperref[zgetCapBase]{getCapBase}#(c)) in - let newAddress : #\hyperref[zbits]{bits}#(64) = base + offset in - let newCap = { c with address = newAddress } in - let representable = #\hyperref[zfastRepCheck]{fastRepCheck}#(c, (newAddress - c.address)) in - (representable, newCap) diff --git a/cheri/sail_latexcc/sailccfnsetCapPerms.tex b/cheri/sail_latexcc/sailccfnsetCapPerms.tex deleted file mode 100644 index 5af9e7f6..00000000 --- a/cheri/sail_latexcc/sailccfnsetCapPerms.tex +++ /dev/null @@ -1,16 +0,0 @@ -function #\hyperref[zsetCapPerms]{setCapPerms}#(cap, perms) : (CapStruct, #\hyperref[zbits]{bits}#(31)) -> CapStruct = - { cap with - uperms = perms[18..15], - /* 14..11 reserved -- ignore */ - access_system_regs = perms[10], - permit_unseal = perms[9], - permit_ccall = perms[8], - permit_seal = perms[7], - permit_store_local_cap = perms[6], - permit_store_cap = perms[5], - permit_load_cap = perms[4], - permit_store = perms[3], - permit_load = perms[2], - permit_execute = perms[1], - global = perms[0] - } diff --git a/cheri/sail_latexcc/sailccfntobits.tex b/cheri/sail_latexcc/sailccfntobits.tex deleted file mode 100644 index d1df5e83..00000000 --- a/cheri/sail_latexcc/sailccfntobits.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[ztozybits]{to\_bits}# (l, n) = #\hyperref[zgetzyslicezyint]{get\_slice\_int}#(l, n, 0) diff --git a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozIsznine.tex b/cheri/sail_latexcc/sailccfnzeightoperatorzzerozIsznine.tex deleted file mode 100644 index 62e5a2e4..00000000 --- a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozIsznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator <#\hyperref[zzys]{\_s}# (x, y) = #\hyperref[zsigned]{signed}#(x) < #\hyperref[zsigned]{signed}#(y) diff --git a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozIuznine.tex b/cheri/sail_latexcc/sailccfnzeightoperatorzzerozIuznine.tex deleted file mode 100644 index 3f946820..00000000 --- a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozIuznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator <#\hyperref[zzyu]{\_u}# (x, y) = #\hyperref[zunsigned]{unsigned}#(x) < #\hyperref[zunsigned]{unsigned}#(y) diff --git a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozKzJsznine.tex b/cheri/sail_latexcc/sailccfnzeightoperatorzzerozKzJsznine.tex deleted file mode 100644 index 57ecf181..00000000 --- a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozKzJsznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator >=#\hyperref[zzys]{\_s}# (x, y) = #\hyperref[zsigned]{signed}#(x) >= #\hyperref[zsigned]{signed}#(y) diff --git a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozKzJuznine.tex b/cheri/sail_latexcc/sailccfnzeightoperatorzzerozKzJuznine.tex deleted file mode 100644 index 6df36c6f..00000000 --- a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozKzJuznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator >=#\hyperref[zzyu]{\_u}# (x, y) = #\hyperref[zunsigned]{unsigned}#(x) >= #\hyperref[zunsigned]{unsigned}#(y) diff --git a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozQzQznine.tex b/cheri/sail_latexcc/sailccfnzeightoperatorzzerozQzQznine.tex deleted file mode 100644 index 2c372e1b..00000000 --- a/cheri/sail_latexcc/sailccfnzeightoperatorzzerozQzQznine.tex +++ /dev/null @@ -1 +0,0 @@ -function operator ^^ (bs, n) = #\hyperref[zreplicatezybits]{replicate\_bits}# (bs, n) diff --git a/cheri/sail_latexcc/sailccfnzzeros.tex b/cheri/sail_latexcc/sailccfnzzeros.tex deleted file mode 100644 index 38d463fb..00000000 --- a/cheri/sail_latexcc/sailccfnzzeros.tex +++ /dev/null @@ -1 +0,0 @@ -function #\hyperref[zzzeros]{zeros}#() = #\hyperref[zreplicatezybits]{replicate\_bits}# (0b0,'n) diff --git a/cheri/sail_latexcc/sailccgetCapBase.tex b/cheri/sail_latexcc/sailccgetCapBase.tex deleted file mode 100644 index c7044d1d..00000000 --- a/cheri/sail_latexcc/sailccgetCapBase.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapBase : CapStruct -> uint64 diff --git a/cheri/sail_latexcc/sailccgetCapCursor.tex b/cheri/sail_latexcc/sailccgetCapCursor.tex deleted file mode 100644 index fd5d72d8..00000000 --- a/cheri/sail_latexcc/sailccgetCapCursor.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapCursor : CapStruct -> uint64 diff --git a/cheri/sail_latexcc/sailccgetCapHardPerms.tex b/cheri/sail_latexcc/sailccgetCapHardPerms.tex deleted file mode 100644 index 3b65a7c0..00000000 --- a/cheri/sail_latexcc/sailccgetCapHardPerms.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapHardPerms : CapStruct -> bits(11) diff --git a/cheri/sail_latexcc/sailccgetCapLength.tex b/cheri/sail_latexcc/sailccgetCapLength.tex deleted file mode 100644 index be84bfb5..00000000 --- a/cheri/sail_latexcc/sailccgetCapLength.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapLength : CapStruct -> CapLen effect {escape} diff --git a/cheri/sail_latexcc/sailccgetCapOffset.tex b/cheri/sail_latexcc/sailccgetCapOffset.tex deleted file mode 100644 index 668c3df1..00000000 --- a/cheri/sail_latexcc/sailccgetCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapOffset : CapStruct -> uint64 diff --git a/cheri/sail_latexcc/sailccgetCapPerms.tex b/cheri/sail_latexcc/sailccgetCapPerms.tex deleted file mode 100644 index b2dabf89..00000000 --- a/cheri/sail_latexcc/sailccgetCapPerms.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapPerms : CapStruct -> bits(31) diff --git a/cheri/sail_latexcc/sailccgetCapTop.tex b/cheri/sail_latexcc/sailccgetCapTop.tex deleted file mode 100644 index ff0e5f95..00000000 --- a/cheri/sail_latexcc/sailccgetCapTop.tex +++ /dev/null @@ -1 +0,0 @@ -val getCapTop : CapStruct -> CapLen diff --git a/cheri/sail_latexcc/sailccgetsliceint.tex b/cheri/sail_latexcc/sailccgetsliceint.tex deleted file mode 100644 index 2b30d096..00000000 --- a/cheri/sail_latexcc/sailccgetsliceint.tex +++ /dev/null @@ -1 +0,0 @@ -val get_slice_int = "get_slice_int" : forall 'w. (atom('w), int, int) -> #\hyperref[zbits]{bits}#('w) diff --git a/cheri/sail_latexcc/sailccgettimens.tex b/cheri/sail_latexcc/sailccgettimens.tex deleted file mode 100644 index 74cfd526..00000000 --- a/cheri/sail_latexcc/sailccgettimens.tex +++ /dev/null @@ -1 +0,0 @@ -val "get_time_ns" : unit -> int diff --git a/cheri/sail_latexcc/sailccgtatom.tex b/cheri/sail_latexcc/sailccgtatom.tex deleted file mode 100644 index b2147a8f..00000000 --- a/cheri/sail_latexcc/sailccgtatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_atom = {coq: "Z.gtb", _: "gt"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latexcc/sailccgtatomrange.tex b/cheri/sail_latexcc/sailccgtatomrange.tex deleted file mode 100644 index 3c520181..00000000 --- a/cheri/sail_latexcc/sailccgtatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_atom_range = {coq: "gtb_range_r", _: "gt"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latexcc/sailccgteqatom.tex b/cheri/sail_latexcc/sailccgteqatom.tex deleted file mode 100644 index fb3b66b2..00000000 --- a/cheri/sail_latexcc/sailccgteqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_atom = {coq: "Z.geb", _: "gteq"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latexcc/sailccgteqatomrange.tex b/cheri/sail_latexcc/sailccgteqatomrange.tex deleted file mode 100644 index 7aaf633f..00000000 --- a/cheri/sail_latexcc/sailccgteqatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_atom_range = {coq: "geb_range_r", _: "gteq"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latexcc/sailccgteqint.tex b/cheri/sail_latexcc/sailccgteqint.tex deleted file mode 100644 index 77271d1f..00000000 --- a/cheri/sail_latexcc/sailccgteqint.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_int = {coq: "Z.geb", _:"gteq"} : (int, int) -> bool diff --git a/cheri/sail_latexcc/sailccgteqrangeatom.tex b/cheri/sail_latexcc/sailccgteqrangeatom.tex deleted file mode 100644 index fda25265..00000000 --- a/cheri/sail_latexcc/sailccgteqrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gteq_range_atom = {coq: "geb_range_l", _: "gteq"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latexcc/sailccgtint.tex b/cheri/sail_latexcc/sailccgtint.tex deleted file mode 100644 index 2d953eec..00000000 --- a/cheri/sail_latexcc/sailccgtint.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_int = {coq: "Z.gtb", _:"gt"} : (int, int) -> bool diff --git a/cheri/sail_latexcc/sailccgtrangeatom.tex b/cheri/sail_latexcc/sailccgtrangeatom.tex deleted file mode 100644 index b8635909..00000000 --- a/cheri/sail_latexcc/sailccgtrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val gt_range_atom = {coq: "gtb_range_l", _: "gt"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latexcc/sailccincCapOffset.tex b/cheri/sail_latexcc/sailccincCapOffset.tex deleted file mode 100644 index 21c08cb5..00000000 --- a/cheri/sail_latexcc/sailccincCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -val incCapOffset : (CapStruct, bits(64)) -> (bool, CapStruct) diff --git a/cheri/sail_latexcc/sailccintpower.tex b/cheri/sail_latexcc/sailccintpower.tex deleted file mode 100644 index 0aa13188..00000000 --- a/cheri/sail_latexcc/sailccintpower.tex +++ /dev/null @@ -1 +0,0 @@ -val int_power = {ocaml: "int_power", lem: "pow", coq: "Z.pow"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccinttocap.tex b/cheri/sail_latexcc/sailccinttocap.tex deleted file mode 100644 index 0f4cd328..00000000 --- a/cheri/sail_latexcc/sailccinttocap.tex +++ /dev/null @@ -1 +0,0 @@ -val int_to_cap : bits(64) -> CapStruct diff --git a/cheri/sail_latexcc/sailccisnone.tex b/cheri/sail_latexcc/sailccisnone.tex deleted file mode 100644 index 76688d37..00000000 --- a/cheri/sail_latexcc/sailccisnone.tex +++ /dev/null @@ -1 +0,0 @@ -val is_none : forall ('a : Type). #\hyperref[zoption]{option}#('a) -> bool diff --git a/cheri/sail_latexcc/sailccissome.tex b/cheri/sail_latexcc/sailccissome.tex deleted file mode 100644 index 071ac6b6..00000000 --- a/cheri/sail_latexcc/sailccissome.tex +++ /dev/null @@ -1 +0,0 @@ -val is_some : forall ('a : Type). #\hyperref[zoption]{option}#('a) -> bool diff --git a/cheri/sail_latexcc/sailcclength.tex b/cheri/sail_latexcc/sailcclength.tex deleted file mode 100644 index 248c8507..00000000 --- a/cheri/sail_latexcc/sailcclength.tex +++ /dev/null @@ -1 +0,0 @@ -overload length = {bitvector_length, vector_length}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccltatom.tex b/cheri/sail_latexcc/sailccltatom.tex deleted file mode 100644 index 5cca54df..00000000 --- a/cheri/sail_latexcc/sailccltatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_atom = {coq: "Z.ltb", _: "lt"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latexcc/sailccltatomrange.tex b/cheri/sail_latexcc/sailccltatomrange.tex deleted file mode 100644 index 19d3375d..00000000 --- a/cheri/sail_latexcc/sailccltatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_atom_range = {coq: "ltb_range_r", _: "lt"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latexcc/sailcclteqatom.tex b/cheri/sail_latexcc/sailcclteqatom.tex deleted file mode 100644 index 26e27e2d..00000000 --- a/cheri/sail_latexcc/sailcclteqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_atom = {coq: "Z.leb", _: "lteq"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latexcc/sailcclteqatomrange.tex b/cheri/sail_latexcc/sailcclteqatomrange.tex deleted file mode 100644 index 6e951cf7..00000000 --- a/cheri/sail_latexcc/sailcclteqatomrange.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_atom_range = {coq: "leb_range_r", _: "lteq"} : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool diff --git a/cheri/sail_latexcc/sailcclteqint.tex b/cheri/sail_latexcc/sailcclteqint.tex deleted file mode 100644 index 555176be..00000000 --- a/cheri/sail_latexcc/sailcclteqint.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_int = {coq: "Z.leb", _:"lteq"} : (int, int) -> bool diff --git a/cheri/sail_latexcc/sailcclteqrangeatom.tex b/cheri/sail_latexcc/sailcclteqrangeatom.tex deleted file mode 100644 index f8fcd32d..00000000 --- a/cheri/sail_latexcc/sailcclteqrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lteq_range_atom = {coq: "leb_range_l", _: "lteq"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latexcc/sailccltint.tex b/cheri/sail_latexcc/sailccltint.tex deleted file mode 100644 index 40bd4e85..00000000 --- a/cheri/sail_latexcc/sailccltint.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_int = {coq: "Z.ltb", _:"lt"} : (int, int) -> bool diff --git a/cheri/sail_latexcc/sailccltrangeatom.tex b/cheri/sail_latexcc/sailccltrangeatom.tex deleted file mode 100644 index d8495496..00000000 --- a/cheri/sail_latexcc/sailccltrangeatom.tex +++ /dev/null @@ -1 +0,0 @@ -val lt_range_atom = {coq: "ltb_range_l", _: "lt"} : forall 'n 'm 'o. (range('n, 'm), atom('o)) -> bool diff --git a/cheri/sail_latexcc/sailccmask.tex b/cheri/sail_latexcc/sailccmask.tex deleted file mode 100644 index 35d052db..00000000 --- a/cheri/sail_latexcc/sailccmask.tex +++ /dev/null @@ -1 +0,0 @@ -val mask : forall 'm 'n , 'm >= 'n > 0 . #\hyperref[zbits]{bits}#('m) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccmax.tex b/cheri/sail_latexcc/sailccmax.tex deleted file mode 100644 index 1ceed42c..00000000 --- a/cheri/sail_latexcc/sailccmax.tex +++ /dev/null @@ -1 +0,0 @@ -overload max = {max_atom, max_nat, max_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccmaxatom.tex b/cheri/sail_latexcc/sailccmaxatom.tex deleted file mode 100644 index 6cbdfa7f..00000000 --- a/cheri/sail_latexcc/sailccmaxatom.tex +++ /dev/null @@ -1 +0,0 @@ -val max_atom = {ocaml: "max_int", lem: "max", coq: "max_atom", c:"max_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c >= 'a & 'c >= 'b . atom('c)} diff --git a/cheri/sail_latexcc/sailccmaxint.tex b/cheri/sail_latexcc/sailccmaxint.tex deleted file mode 100644 index c537babb..00000000 --- a/cheri/sail_latexcc/sailccmaxint.tex +++ /dev/null @@ -1 +0,0 @@ -val max_int = {lem: "max", coq: "Z.max", _: "max_int"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccmaxnat.tex b/cheri/sail_latexcc/sailccmaxnat.tex deleted file mode 100644 index 1b62334a..00000000 --- a/cheri/sail_latexcc/sailccmaxnat.tex +++ /dev/null @@ -1 +0,0 @@ -val max_nat = {lem: "max", coq: "Z.max", _: "max_int"} : (nat, nat) -> nat diff --git a/cheri/sail_latexcc/sailccmemBitsToCapBits.tex b/cheri/sail_latexcc/sailccmemBitsToCapBits.tex deleted file mode 100644 index a5c86272..00000000 --- a/cheri/sail_latexcc/sailccmemBitsToCapBits.tex +++ /dev/null @@ -1 +0,0 @@ -val memBitsToCapBits : (bool, bits(128)) -> bits(129) diff --git a/cheri/sail_latexcc/sailccmemBitsToCapBitsonetwoeight.tex b/cheri/sail_latexcc/sailccmemBitsToCapBitsonetwoeight.tex deleted file mode 100644 index 4eb94a3d..00000000 --- a/cheri/sail_latexcc/sailccmemBitsToCapBitsonetwoeight.tex +++ /dev/null @@ -1 +0,0 @@ -val memBitsToCapBits128 : (bool, bits(128)) -> CapReg diff --git a/cheri/sail_latexcc/sailccmin.tex b/cheri/sail_latexcc/sailccmin.tex deleted file mode 100644 index 94097198..00000000 --- a/cheri/sail_latexcc/sailccmin.tex +++ /dev/null @@ -1 +0,0 @@ -overload min = {min_atom, min_nat, min_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccminatom.tex b/cheri/sail_latexcc/sailccminatom.tex deleted file mode 100644 index acfea384..00000000 --- a/cheri/sail_latexcc/sailccminatom.tex +++ /dev/null @@ -1 +0,0 @@ -val min_atom = {ocaml: "min_int", lem: "min", coq: "min_atom", c:"min_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c <= 'a & 'c <= 'b . atom('c)} diff --git a/cheri/sail_latexcc/sailccminint.tex b/cheri/sail_latexcc/sailccminint.tex deleted file mode 100644 index 3d633d08..00000000 --- a/cheri/sail_latexcc/sailccminint.tex +++ /dev/null @@ -1 +0,0 @@ -val min_int = {lem: "min", coq: "Z.min", _: "min_int"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccminnat.tex b/cheri/sail_latexcc/sailccminnat.tex deleted file mode 100644 index 85409bd8..00000000 --- a/cheri/sail_latexcc/sailccminnat.tex +++ /dev/null @@ -1 +0,0 @@ -val min_nat = {lem: "min", coq: "Z.min", _: "min_int"} : (nat, nat) -> nat diff --git a/cheri/sail_latexcc/sailccmipssignextend.tex b/cheri/sail_latexcc/sailccmipssignextend.tex deleted file mode 100644 index e613567d..00000000 --- a/cheri/sail_latexcc/sailccmipssignextend.tex +++ /dev/null @@ -1 +0,0 @@ -val mips_sign_extend : forall 'n 'm , 'm >= 'n . #\hyperref[zbits]{bits}#('n) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latexcc/sailccmipszzeroextend.tex b/cheri/sail_latexcc/sailccmipszzeroextend.tex deleted file mode 100644 index adbb4188..00000000 --- a/cheri/sail_latexcc/sailccmipszzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -val mips_zero_extend : forall 'n 'm , 'm >= 'n . #\hyperref[zbits]{bits}#('n) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latexcc/sailccmod.tex b/cheri/sail_latexcc/sailccmod.tex deleted file mode 100644 index ab70dd7a..00000000 --- a/cheri/sail_latexcc/sailccmod.tex +++ /dev/null @@ -1,7 +0,0 @@ -val mod = { - smt: "mod", - ocaml: "modulus", - lem: "integerMod", - c: "tmod_int", - coq: "mod_with_eq" -} : forall 'n 'm. (atom('n), atom('m)) -> {'o, 'o = #\hyperref[zmod]{mod}#('n, 'm). atom('o)} diff --git a/cheri/sail_latexcc/sailccmodint.tex b/cheri/sail_latexcc/sailccmodint.tex deleted file mode 100644 index bd5677aa..00000000 --- a/cheri/sail_latexcc/sailccmodint.tex +++ /dev/null @@ -1,7 +0,0 @@ -val mod_int = { - smt: "mod", - ocaml: "modulus", - lem: "integerMod", - c: "tmod_int", - coq: "Z.rem" -} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccmodulus.tex b/cheri/sail_latexcc/sailccmodulus.tex deleted file mode 100644 index ca23a339..00000000 --- a/cheri/sail_latexcc/sailccmodulus.tex +++ /dev/null @@ -1 +0,0 @@ -val modulus = {ocaml: "modulus", lem: "hardware_mod", coq: "euclid_modulo", _ : "tmod_int"} : forall 'n, 'n > 0 . (int, atom('n)) -> range(0, 'n - 1) diff --git a/cheri/sail_latexcc/sailccmultatom.tex b/cheri/sail_latexcc/sailccmultatom.tex deleted file mode 100644 index bbac3e2f..00000000 --- a/cheri/sail_latexcc/sailccmultatom.tex +++ /dev/null @@ -1,2 +0,0 @@ -val mult_atom = {ocaml: "mult", lem: "integerMult", c: "mult_int", coq: "Z.mul"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n * 'm) diff --git a/cheri/sail_latexcc/sailccmultint.tex b/cheri/sail_latexcc/sailccmultint.tex deleted file mode 100644 index 08698e6f..00000000 --- a/cheri/sail_latexcc/sailccmultint.tex +++ /dev/null @@ -1 +0,0 @@ -val mult_int = {ocaml: "mult", lem: "integerMult", c: "mult_int", coq: "Z.mul"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccnegate.tex b/cheri/sail_latexcc/sailccnegate.tex deleted file mode 100644 index ce000062..00000000 --- a/cheri/sail_latexcc/sailccnegate.tex +++ /dev/null @@ -1 +0,0 @@ -overload negate = {negate_range, negate_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccnegateatom.tex b/cheri/sail_latexcc/sailccnegateatom.tex deleted file mode 100644 index d1361e63..00000000 --- a/cheri/sail_latexcc/sailccnegateatom.tex +++ /dev/null @@ -1 +0,0 @@ -val negate_atom = {ocaml: "negate", lem: "integerNegate", c: "neg_int", coq: "Z.opp"} : forall 'n. atom('n) -> atom(- 'n) diff --git a/cheri/sail_latexcc/sailccnegateint.tex b/cheri/sail_latexcc/sailccnegateint.tex deleted file mode 100644 index 52375787..00000000 --- a/cheri/sail_latexcc/sailccnegateint.tex +++ /dev/null @@ -1 +0,0 @@ -val negate_int = {ocaml: "negate", lem: "integerNegate", c: "neg_int", coq: "Z.opp"} : int -> int diff --git a/cheri/sail_latexcc/sailccnegaterange.tex b/cheri/sail_latexcc/sailccnegaterange.tex deleted file mode 100644 index 7a4ad386..00000000 --- a/cheri/sail_latexcc/sailccnegaterange.tex +++ /dev/null @@ -1 +0,0 @@ -val negate_range = {ocaml: "minus_big_int", lem: "integerNegate", coq: "negate_range"} : forall 'n 'm. range('n, 'm) -> range(- 'm, - 'n) diff --git a/cheri/sail_latexcc/sailccneqanything.tex b/cheri/sail_latexcc/sailccneqanything.tex deleted file mode 100644 index a898649e..00000000 --- a/cheri/sail_latexcc/sailccneqanything.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_anything = {lem: "neq", coq: "generic_neq"} : forall ('a : Type). ('a, 'a) -> bool diff --git a/cheri/sail_latexcc/sailccneqatom.tex b/cheri/sail_latexcc/sailccneqatom.tex deleted file mode 100644 index be777013..00000000 --- a/cheri/sail_latexcc/sailccneqatom.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_atom = {lem: "neq", coq: "neq_atom"} : forall 'n 'm. (atom('n), atom('m)) -> bool diff --git a/cheri/sail_latexcc/sailccneqbool.tex b/cheri/sail_latexcc/sailccneqbool.tex deleted file mode 100644 index 0d80dc17..00000000 --- a/cheri/sail_latexcc/sailccneqbool.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_bool : (bool, bool) -> bool diff --git a/cheri/sail_latexcc/sailccneqint.tex b/cheri/sail_latexcc/sailccneqint.tex deleted file mode 100644 index b233ca6b..00000000 --- a/cheri/sail_latexcc/sailccneqint.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_int = {lem: "neq"} : (int, int) -> bool diff --git a/cheri/sail_latexcc/sailccneqrange.tex b/cheri/sail_latexcc/sailccneqrange.tex deleted file mode 100644 index d2d8fb0c..00000000 --- a/cheri/sail_latexcc/sailccneqrange.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_range = {lem: "neq"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool diff --git a/cheri/sail_latexcc/sailccneqvec.tex b/cheri/sail_latexcc/sailccneqvec.tex deleted file mode 100644 index f655b3d8..00000000 --- a/cheri/sail_latexcc/sailccneqvec.tex +++ /dev/null @@ -1 +0,0 @@ -val neq_vec = {lem: "neq"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latexcc/sailccnot.tex b/cheri/sail_latexcc/sailccnot.tex deleted file mode 100644 index 515b3ef9..00000000 --- a/cheri/sail_latexcc/sailccnot.tex +++ /dev/null @@ -1 +0,0 @@ -val not = {coq:"negb", _:"not"} : bool -> bool diff --git a/cheri/sail_latexcc/sailccnotbool.tex b/cheri/sail_latexcc/sailccnotbool.tex deleted file mode 100644 index 7630f6c2..00000000 --- a/cheri/sail_latexcc/sailccnotbool.tex +++ /dev/null @@ -1 +0,0 @@ -val not_bool = {coq: "negb", _: "not"} : bool -> bool diff --git a/cheri/sail_latexcc/sailccnotvec.tex b/cheri/sail_latexcc/sailccnotvec.tex deleted file mode 100644 index a560a544..00000000 --- a/cheri/sail_latexcc/sailccnotvec.tex +++ /dev/null @@ -1 +0,0 @@ -val not_vec = {c:"not_bits", _:"not_vec"} : forall 'n. #\hyperref[zbits]{bits}#('n) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccnumofCPtrCmpOp.tex b/cheri/sail_latexcc/sailccnumofCPtrCmpOp.tex deleted file mode 100644 index 40f1bfa9..00000000 --- a/cheri/sail_latexcc/sailccnumofCPtrCmpOp.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_CPtrCmpOp : CPtrCmpOp -> {'e, 0 <= 'e & 'e <= 7. atom('e)} diff --git a/cheri/sail_latexcc/sailccnumofClearRegSet.tex b/cheri/sail_latexcc/sailccnumofClearRegSet.tex deleted file mode 100644 index 14ea7bea..00000000 --- a/cheri/sail_latexcc/sailccnumofClearRegSet.tex +++ /dev/null @@ -1 +0,0 @@ -val num_of_ClearRegSet : ClearRegSet -> {'e, 0 <= 'e & 'e <= 3. atom('e)} diff --git a/cheri/sail_latexcc/sailccones.tex b/cheri/sail_latexcc/sailccones.tex deleted file mode 100644 index 94fd805f..00000000 --- a/cheri/sail_latexcc/sailccones.tex +++ /dev/null @@ -1 +0,0 @@ -val ones : forall 'n, 'n >= 0 . unit -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccorbits.tex b/cheri/sail_latexcc/sailccorbits.tex deleted file mode 100644 index 55db5ffa..00000000 --- a/cheri/sail_latexcc/sailccorbits.tex +++ /dev/null @@ -1 +0,0 @@ -val or_bits = {c: "or_bits", _: "or_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccorbool.tex b/cheri/sail_latexcc/sailccorbool.tex deleted file mode 100644 index 4b6bfa15..00000000 --- a/cheri/sail_latexcc/sailccorbool.tex +++ /dev/null @@ -1 +0,0 @@ -val or_bool = {coq: "orb", _: "or_bool"} : (bool, bool) -> bool diff --git a/cheri/sail_latexcc/sailccplainvectoraccess.tex b/cheri/sail_latexcc/sailccplainvectoraccess.tex deleted file mode 100644 index 94824f77..00000000 --- a/cheri/sail_latexcc/sailccplainvectoraccess.tex +++ /dev/null @@ -1,6 +0,0 @@ -val plain_vector_access = { - ocaml: "access", - lem: "access_list_dec", - coq: "vec_access_dec", - c: "vector_access" -} : forall ('n : Int) ('m : Int) ('a : Type), 0 <= 'm < 'n. (vector('n, dec, 'a), atom('m)) -> 'a diff --git a/cheri/sail_latexcc/sailccplainvectorupdate.tex b/cheri/sail_latexcc/sailccplainvectorupdate.tex deleted file mode 100644 index 6880d9bd..00000000 --- a/cheri/sail_latexcc/sailccplainvectorupdate.tex +++ /dev/null @@ -1,6 +0,0 @@ -val plain_vector_update = { - ocaml: "update", - lem: "update_list_dec", - coq: "vec_update_dec", - c: "vector_update" -} : forall '#\hyperref[zn]{n}# ('a : Type). (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a) diff --git a/cheri/sail_latexcc/sailccpowtwo.tex b/cheri/sail_latexcc/sailccpowtwo.tex deleted file mode 100644 index 41da946e..00000000 --- a/cheri/sail_latexcc/sailccpowtwo.tex +++ /dev/null @@ -1 +0,0 @@ -val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n) diff --git a/cheri/sail_latexcc/sailccprerrbits.tex b/cheri/sail_latexcc/sailccprerrbits.tex deleted file mode 100644 index 7d926384..00000000 --- a/cheri/sail_latexcc/sailccprerrbits.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_bits" : forall 'n. (string, #\hyperref[zbits]{bits}#('n)) -> unit diff --git a/cheri/sail_latexcc/sailccprerrendline.tex b/cheri/sail_latexcc/sailccprerrendline.tex deleted file mode 100644 index ad4a94a0..00000000 --- a/cheri/sail_latexcc/sailccprerrendline.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_endline" : string -> unit diff --git a/cheri/sail_latexcc/sailccprerrint.tex b/cheri/sail_latexcc/sailccprerrint.tex deleted file mode 100644 index ce7a7d61..00000000 --- a/cheri/sail_latexcc/sailccprerrint.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_int" : (string, int) -> unit diff --git a/cheri/sail_latexcc/sailccprerrstring.tex b/cheri/sail_latexcc/sailccprerrstring.tex deleted file mode 100644 index 7b849da2..00000000 --- a/cheri/sail_latexcc/sailccprerrstring.tex +++ /dev/null @@ -1 +0,0 @@ -val "prerr_string" : string -> unit diff --git a/cheri/sail_latexcc/sailccprint.tex b/cheri/sail_latexcc/sailccprint.tex deleted file mode 100644 index 50a64219..00000000 --- a/cheri/sail_latexcc/sailccprint.tex +++ /dev/null @@ -1 +0,0 @@ -val print = "print_endline" : string -> unit diff --git a/cheri/sail_latexcc/sailccprintbits.tex b/cheri/sail_latexcc/sailccprintbits.tex deleted file mode 100644 index 8783a59a..00000000 --- a/cheri/sail_latexcc/sailccprintbits.tex +++ /dev/null @@ -1 +0,0 @@ -val "print_bits" : forall 'n. (string, #\hyperref[zbits]{bits}#('n)) -> unit diff --git a/cheri/sail_latexcc/sailccprintint.tex b/cheri/sail_latexcc/sailccprintint.tex deleted file mode 100644 index ddf33afc..00000000 --- a/cheri/sail_latexcc/sailccprintint.tex +++ /dev/null @@ -1 +0,0 @@ -val "print_int" : (string, int) -> unit diff --git a/cheri/sail_latexcc/sailccputchar.tex b/cheri/sail_latexcc/sailccputchar.tex deleted file mode 100644 index a123c709..00000000 --- a/cheri/sail_latexcc/sailccputchar.tex +++ /dev/null @@ -1 +0,0 @@ -val putchar = {c:"sail_putchar", _:"putchar"} : int -> unit diff --git a/cheri/sail_latexcc/sailccquotient.tex b/cheri/sail_latexcc/sailccquotient.tex deleted file mode 100644 index 7dba5359..00000000 --- a/cheri/sail_latexcc/sailccquotient.tex +++ /dev/null @@ -1 +0,0 @@ -val quotient = {ocaml: "quotient", lem: "integerDiv", coq: "Z.mod"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccquotientnat.tex b/cheri/sail_latexcc/sailccquotientnat.tex deleted file mode 100644 index 14db4ae0..00000000 --- a/cheri/sail_latexcc/sailccquotientnat.tex +++ /dev/null @@ -1 +0,0 @@ -val quotient_nat = {ocaml: "quotient", lem: "integerDiv", coq: "Z.div"} : (nat, nat) -> nat diff --git a/cheri/sail_latexcc/sailccquotroundzzero.tex b/cheri/sail_latexcc/sailccquotroundzzero.tex deleted file mode 100644 index 9523cfcc..00000000 --- a/cheri/sail_latexcc/sailccquotroundzzero.tex +++ /dev/null @@ -1 +0,0 @@ -val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot", coq: "Z.quot", _ : "tdiv_int"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccregderef.tex b/cheri/sail_latexcc/sailccregderef.tex deleted file mode 100644 index 7f1dc7e8..00000000 --- a/cheri/sail_latexcc/sailccregderef.tex +++ /dev/null @@ -1 +0,0 @@ -val _reg_deref = "reg_deref" : forall ('a : Type). #\hyperref[zregister]{register}#('a) -> 'a diff --git a/cheri/sail_latexcc/sailccremroundzzero.tex b/cheri/sail_latexcc/sailccremroundzzero.tex deleted file mode 100644 index 9d8113ba..00000000 --- a/cheri/sail_latexcc/sailccremroundzzero.tex +++ /dev/null @@ -1 +0,0 @@ -val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod", coq: "Z.rem", _ : "tmod_int"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccreplicatebits.tex b/cheri/sail_latexcc/sailccreplicatebits.tex deleted file mode 100644 index cd7a97d7..00000000 --- a/cheri/sail_latexcc/sailccreplicatebits.tex +++ /dev/null @@ -1 +0,0 @@ -val replicate_bits = "replicate_bits" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('n * 'm) diff --git a/cheri/sail_latexcc/sailccroundUp.tex b/cheri/sail_latexcc/sailccroundUp.tex deleted file mode 100644 index b7e31074..00000000 --- a/cheri/sail_latexcc/sailccroundUp.tex +++ /dev/null @@ -1 +0,0 @@ -val roundUp : range(0, 45) -> range(0, 48) diff --git a/cheri/sail_latexcc/sailccsailccnegatev.tex b/cheri/sail_latexcc/sailccsailccnegatev.tex deleted file mode 100644 index 4f7aea58..00000000 --- a/cheri/sail_latexcc/sailccsailccnegatev.tex +++ /dev/null @@ -1 +0,0 @@ -overload negate = {negate_atom, negate_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailccregderefv.tex b/cheri/sail_latexcc/sailccsailccregderefv.tex deleted file mode 100644 index f5de92ca..00000000 --- a/cheri/sail_latexcc/sailccsailccregderefv.tex +++ /dev/null @@ -1 +0,0 @@ -val "reg_deref" : forall ('a : Type). #\hyperref[zregister]{register}#('a) -> 'a effect {rreg} diff --git a/cheri/sail_latexcc/sailccsailccsailccsailcczeightoperatorzzerozJzJzninevvv.tex b/cheri/sail_latexcc/sailccsailccsailccsailcczeightoperatorzzerozJzJzninevvv.tex deleted file mode 100644 index 0f72fdc9..00000000 --- a/cheri/sail_latexcc/sailccsailccsailccsailcczeightoperatorzzerozJzJzninevvv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_bit2}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozBzninevv.tex b/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozBzninevv.tex deleted file mode 100644 index eacd556c..00000000 --- a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozBzninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator +) = {add_atom, add_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozFzninevv.tex b/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozFzninevv.tex deleted file mode 100644 index 73c40722..00000000 --- a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozFzninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator /) = {div}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozJzJzninevv.tex b/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozJzJzninevv.tex deleted file mode 100644 index 47b1d0f6..00000000 --- a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozJzJzninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_atom, eq_range, eq_int, eq_bool}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozfivezninevv.tex b/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozfivezninevv.tex deleted file mode 100644 index 552e0c24..00000000 --- a/cheri/sail_latexcc/sailccsailccsailcczeightoperatorzzerozfivezninevv.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator %) = {mod}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozAzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozAzninev.tex deleted file mode 100644 index afe7a721..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozAzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator *) = {mult_atom, mult_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozBzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozBzninev.tex deleted file mode 100644 index ddc56bfd..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozBzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator +) = {add_bits, add_bits_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozDzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozDzninev.tex deleted file mode 100644 index 5d12fdf1..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozDzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator -) = {sub_atom, sub_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozFzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozFzninev.tex deleted file mode 100644 index 38e9124b..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozFzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator /) = {div_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozJzJzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozJzJzninev.tex deleted file mode 100644 index 1314a962..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozJzJzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_bit, eq_bits}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozQzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozQzninev.tex deleted file mode 100644 index 05769645..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozQzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ^) = {sail_mask}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozUzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozUzninev.tex deleted file mode 100644 index 1ebacbc4..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozUzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator |) = {or_bool}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozfivezninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozfivezninev.tex deleted file mode 100644 index 14fa73b8..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozfivezninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator %) = {mod_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozonezJzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozonezJzninev.tex deleted file mode 100644 index 527cf596..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozonezJzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator !=) = {neq_atom, neq_range, neq_int, neq_bool}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozsixzninev.tex b/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozsixzninev.tex deleted file mode 100644 index be6f29ef..00000000 --- a/cheri/sail_latexcc/sailccsailcczeightoperatorzzerozsixzninev.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator &) = {and_bool}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccsailmask.tex b/cheri/sail_latexcc/sailccsailmask.tex deleted file mode 100644 index 45862747..00000000 --- a/cheri/sail_latexcc/sailccsailmask.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_mask : forall 'len 'v, 'len >= 0 & 'v >= 0. (atom('len), vector('v, dec, bit)) -> vector('len, dec, bit) diff --git a/cheri/sail_latexcc/sailccsailsignextend.tex b/cheri/sail_latexcc/sailccsailsignextend.tex deleted file mode 100644 index dfaa5c86..00000000 --- a/cheri/sail_latexcc/sailccsailsignextend.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_sign_extend = "sign_extend" : forall 'n 'm, 'm >= 'n. (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latexcc/sailccsailzzeroextend.tex b/cheri/sail_latexcc/sailccsailzzeroextend.tex deleted file mode 100644 index 53f6fff9..00000000 --- a/cheri/sail_latexcc/sailccsailzzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_zero_extend = "zero_extend" : forall 'n 'm, 'm >= 'n. (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latexcc/sailccsailzzeros.tex b/cheri/sail_latexcc/sailccsailzzeros.tex deleted file mode 100644 index 9c60aa12..00000000 --- a/cheri/sail_latexcc/sailccsailzzeros.tex +++ /dev/null @@ -1 +0,0 @@ -val sail_zeros = "zeros" : forall 'n. atom('n) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccsealCap.tex b/cheri/sail_latexcc/sailccsealCap.tex deleted file mode 100644 index 891ae279..00000000 --- a/cheri/sail_latexcc/sailccsealCap.tex +++ /dev/null @@ -1 +0,0 @@ -val sealCap : (CapStruct, bits(24)) -> (bool, CapStruct) diff --git a/cheri/sail_latexcc/sailccsetCapBounds.tex b/cheri/sail_latexcc/sailccsetCapBounds.tex deleted file mode 100644 index 94fbecaf..00000000 --- a/cheri/sail_latexcc/sailccsetCapBounds.tex +++ /dev/null @@ -1 +0,0 @@ -val setCapBounds : (CapStruct, bits(64), bits(65)) -> (bool, CapStruct) effect {escape} diff --git a/cheri/sail_latexcc/sailccsetCapOffset.tex b/cheri/sail_latexcc/sailccsetCapOffset.tex deleted file mode 100644 index fef324f7..00000000 --- a/cheri/sail_latexcc/sailccsetCapOffset.tex +++ /dev/null @@ -1 +0,0 @@ -val setCapOffset : (CapStruct, bits(64)) -> (bool, CapStruct) diff --git a/cheri/sail_latexcc/sailccsetCapPerms.tex b/cheri/sail_latexcc/sailccsetCapPerms.tex deleted file mode 100644 index 617f19fb..00000000 --- a/cheri/sail_latexcc/sailccsetCapPerms.tex +++ /dev/null @@ -1 +0,0 @@ -val setCapPerms : (CapStruct, bits(31)) -> CapStruct diff --git a/cheri/sail_latexcc/sailccsetslicebits.tex b/cheri/sail_latexcc/sailccsetslicebits.tex deleted file mode 100644 index 8a81bff5..00000000 --- a/cheri/sail_latexcc/sailccsetslicebits.tex +++ /dev/null @@ -1,2 +0,0 @@ -val set_slice_bits = "set_slice" : forall 'n 'm. - (atom('n), atom('m), #\hyperref[zbits]{bits}#('n), int, #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccsetsliceint.tex b/cheri/sail_latexcc/sailccsetsliceint.tex deleted file mode 100644 index 413bf721..00000000 --- a/cheri/sail_latexcc/sailccsetsliceint.tex +++ /dev/null @@ -1 +0,0 @@ -val set_slice_int = "set_slice_int" : forall 'w. (atom('w), int, int, #\hyperref[zbits]{bits}#('w)) -> int diff --git a/cheri/sail_latexcc/sailccshiftbitsleft.tex b/cheri/sail_latexcc/sailccshiftbitsleft.tex deleted file mode 100644 index cdb2eb6a..00000000 --- a/cheri/sail_latexcc/sailccshiftbitsleft.tex +++ /dev/null @@ -1 +0,0 @@ -val "shift_bits_left" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) effect {undef} diff --git a/cheri/sail_latexcc/sailccshiftbitsright.tex b/cheri/sail_latexcc/sailccshiftbitsright.tex deleted file mode 100644 index dbc72b11..00000000 --- a/cheri/sail_latexcc/sailccshiftbitsright.tex +++ /dev/null @@ -1 +0,0 @@ -val "shift_bits_right" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) effect {undef} diff --git a/cheri/sail_latexcc/sailccshiftl.tex b/cheri/sail_latexcc/sailccshiftl.tex deleted file mode 100644 index b2c54c27..00000000 --- a/cheri/sail_latexcc/sailccshiftl.tex +++ /dev/null @@ -1 +0,0 @@ -val "shiftl" : forall 'm 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('m), atom('n)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latexcc/sailccshiftr.tex b/cheri/sail_latexcc/sailccshiftr.tex deleted file mode 100644 index f282dcbe..00000000 --- a/cheri/sail_latexcc/sailccshiftr.tex +++ /dev/null @@ -1 +0,0 @@ -val "shiftr" : forall 'm 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('m), atom('n)) -> #\hyperref[zbits]{bits}#('m) diff --git a/cheri/sail_latexcc/sailccshlint.tex b/cheri/sail_latexcc/sailccshlint.tex deleted file mode 100644 index 8ffbcf6c..00000000 --- a/cheri/sail_latexcc/sailccshlint.tex +++ /dev/null @@ -1 +0,0 @@ -val shl_int = "shl_int" : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccshrint.tex b/cheri/sail_latexcc/sailccshrint.tex deleted file mode 100644 index 087c17bb..00000000 --- a/cheri/sail_latexcc/sailccshrint.tex +++ /dev/null @@ -1 +0,0 @@ -val shr_int = "shr_int" : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccsigned.tex b/cheri/sail_latexcc/sailccsigned.tex deleted file mode 100644 index dcdc3049..00000000 --- a/cheri/sail_latexcc/sailccsigned.tex +++ /dev/null @@ -1,4 +0,0 @@ -val signed = { - c: "sail_signed", - _: "sint" -} : forall 'n, 'n > 0. #\hyperref[zbits]{bits}#('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1) diff --git a/cheri/sail_latexcc/sailccsignextend.tex b/cheri/sail_latexcc/sailccsignextend.tex deleted file mode 100644 index 03f56369..00000000 --- a/cheri/sail_latexcc/sailccsignextend.tex +++ /dev/null @@ -1 +0,0 @@ -overload sign_extend = {mips_sign_extend}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccslice.tex b/cheri/sail_latexcc/sailccslice.tex deleted file mode 100644 index b9bb5a70..00000000 --- a/cheri/sail_latexcc/sailccslice.tex +++ /dev/null @@ -1,2 +0,0 @@ -val slice = "slice" : forall 'n 'm 'o, 0 <= 'o < 'm & 'o + 'n <= 'm & 0 <= 'n. - (#\hyperref[zbits]{bits}#('m), atom('o), atom('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccstringofint.tex b/cheri/sail_latexcc/sailccstringofint.tex deleted file mode 100644 index 05edaa20..00000000 --- a/cheri/sail_latexcc/sailccstringofint.tex +++ /dev/null @@ -1 +0,0 @@ -val string_of_int = "string_of_int" : int -> string diff --git a/cheri/sail_latexcc/sailccsubatom.tex b/cheri/sail_latexcc/sailccsubatom.tex deleted file mode 100644 index 437e2d4c..00000000 --- a/cheri/sail_latexcc/sailccsubatom.tex +++ /dev/null @@ -1,2 +0,0 @@ -val sub_atom = {ocaml: "sub_int", lem: "integerMinus", c: "sub_int", coq: "Z.sub"} : forall 'n 'm. - (atom('n), atom('m)) -> atom('n - 'm) diff --git a/cheri/sail_latexcc/sailccsubint.tex b/cheri/sail_latexcc/sailccsubint.tex deleted file mode 100644 index 11fdf922..00000000 --- a/cheri/sail_latexcc/sailccsubint.tex +++ /dev/null @@ -1 +0,0 @@ -val sub_int = {ocaml: "sub_int", lem: "integerMinus", c: "sub_int", coq: "Z.sub"} : (int, int) -> int diff --git a/cheri/sail_latexcc/sailccsubrange.tex b/cheri/sail_latexcc/sailccsubrange.tex deleted file mode 100644 index 2aad56b6..00000000 --- a/cheri/sail_latexcc/sailccsubrange.tex +++ /dev/null @@ -1,2 +0,0 @@ -val sub_range = {ocaml: "sub_int", lem: "integerMinus", coq: "sub_range"} : forall 'n 'm 'o 'p. - (range('n, 'm), range('o, 'p)) -> range('n - 'p, 'm - 'o) diff --git a/cheri/sail_latexcc/sailccsubvec.tex b/cheri/sail_latexcc/sailccsubvec.tex deleted file mode 100644 index b92f07a4..00000000 --- a/cheri/sail_latexcc/sailccsubvec.tex +++ /dev/null @@ -1 +0,0 @@ -val sub_vec = {c : "sub_bits", _:"sub_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccsubvecint.tex b/cheri/sail_latexcc/sailccsubvecint.tex deleted file mode 100644 index 70bf667e..00000000 --- a/cheri/sail_latexcc/sailccsubvecint.tex +++ /dev/null @@ -1 +0,0 @@ -val sub_vec_int = {c:"sub_bits_int", _: "sub_vec_int"} : forall 'n. (#\hyperref[zbits]{bits}#('n), int) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailcctobits.tex b/cheri/sail_latexcc/sailcctobits.tex deleted file mode 100644 index 9dd3c655..00000000 --- a/cheri/sail_latexcc/sailcctobits.tex +++ /dev/null @@ -1 +0,0 @@ -val to_bits : forall 'l, 'l >= 0 .(atom('l), int) -> #\hyperref[zbits]{bits}#('l) diff --git a/cheri/sail_latexcc/sailcctruncate.tex b/cheri/sail_latexcc/sailcctruncate.tex deleted file mode 100644 index 5f7760f3..00000000 --- a/cheri/sail_latexcc/sailcctruncate.tex +++ /dev/null @@ -1,6 +0,0 @@ -val truncate = { - ocaml: "vector_truncate", - lem: "vector_truncate", - coq: "vector_truncate", - c: "sail_truncate" -} : forall 'm 'n, 'm >= 0 & 'm <= 'n. (vector('n, dec, bit), atom('m)) -> vector('m, dec, bit) diff --git a/cheri/sail_latexcc/sailccuintsixfour.tex b/cheri/sail_latexcc/sailccuintsixfour.tex deleted file mode 100644 index a0d52c8f..00000000 --- a/cheri/sail_latexcc/sailccuintsixfour.tex +++ /dev/null @@ -1 +0,0 @@ -type uint64 = range(0, (2 ^ 64) - 1) diff --git a/cheri/sail_latexcc/sailccunsigned.tex b/cheri/sail_latexcc/sailccunsigned.tex deleted file mode 100644 index 47867039..00000000 --- a/cheri/sail_latexcc/sailccunsigned.tex +++ /dev/null @@ -1,7 +0,0 @@ -val unsigned = { - ocaml: "uint", - lem: "uint", - interpreter: "uint", - c: "sail_unsigned", - coq: "uint" -} : forall 'n. #\hyperref[zbits]{bits}#('n) -> range(0, 2 ^ 'n - 1) diff --git a/cheri/sail_latexcc/sailccvectoraccess.tex b/cheri/sail_latexcc/sailccvectoraccess.tex deleted file mode 100644 index a8e8074f..00000000 --- a/cheri/sail_latexcc/sailccvectoraccess.tex +++ /dev/null @@ -1 +0,0 @@ -overload vector_access = {bitvector_access, plain_vector_access}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccvectorlength.tex b/cheri/sail_latexcc/sailccvectorlength.tex deleted file mode 100644 index f41d5bfa..00000000 --- a/cheri/sail_latexcc/sailccvectorlength.tex +++ /dev/null @@ -1,6 +0,0 @@ -val vector_length = { - ocaml: "length", - lem: "length_list", - c: "length", - coq: "vec_length" -} : forall '#\hyperref[zn]{n}# ('a : Type). vector('n, dec, 'a) -> atom('n) diff --git a/cheri/sail_latexcc/sailccvectorsubrange.tex b/cheri/sail_latexcc/sailccvectorsubrange.tex deleted file mode 100644 index c069c7b6..00000000 --- a/cheri/sail_latexcc/sailccvectorsubrange.tex +++ /dev/null @@ -1,7 +0,0 @@ -val vector_subrange = { - ocaml: "subrange", - lem: "subrange_vec_dec", - c: "vector_subrange", - coq: "subrange_vec_dec" -} : forall ('n : Int) ('m : Int) ('o : Int), 0 <= 'o <= 'm < 'n. - (#\hyperref[zbits]{bits}#('n), atom('m), atom('o)) -> #\hyperref[zbits]{bits}#('m - 'o + 1) diff --git a/cheri/sail_latexcc/sailccvectorupdate.tex b/cheri/sail_latexcc/sailccvectorupdate.tex deleted file mode 100644 index 1ec4aaef..00000000 --- a/cheri/sail_latexcc/sailccvectorupdate.tex +++ /dev/null @@ -1 +0,0 @@ -overload vector_update = {bitvector_update, plain_vector_update}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailccvectorupdatesubrange.tex b/cheri/sail_latexcc/sailccvectorupdatesubrange.tex deleted file mode 100644 index 6ff4f9f6..00000000 --- a/cheri/sail_latexcc/sailccvectorupdatesubrange.tex +++ /dev/null @@ -1,6 +0,0 @@ -val vector_update_subrange = { - ocaml: "update_subrange", - lem: "update_subrange_vec_dec", - c: "vector_update_subrange", - coq: "update_subrange_vec_dec" -} : forall 'n 'm 'o. (#\hyperref[zbits]{bits}#('n), atom('m), atom('o), #\hyperref[zbits]{bits}#('m - ('o - 1))) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailccxorvec.tex b/cheri/sail_latexcc/sailccxorvec.tex deleted file mode 100644 index b3aa7372..00000000 --- a/cheri/sail_latexcc/sailccxorvec.tex +++ /dev/null @@ -1 +0,0 @@ -val xor_vec = {c: "xor_bits" , _: "xor_vec"} : forall 'n. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#('n) diff --git a/cheri/sail_latexcc/sailcczW.tex b/cheri/sail_latexcc/sailcczW.tex deleted file mode 100644 index a29ec93f..00000000 --- a/cheri/sail_latexcc/sailcczW.tex +++ /dev/null @@ -1 +0,0 @@ -overload ~ = {not_bool, not_vec}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozAsznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozAsznine.tex deleted file mode 100644 index 0b0a46e2..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozAsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator *_s = "mults_vec" : forall 'n . (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#(2 * 'n) diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozAuznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozAuznine.tex deleted file mode 100644 index 5b762ba7..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozAuznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator *_u = "mult_vec" : forall 'n . (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> #\hyperref[zbits]{bits}#(2 * 'n) diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozAznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozAznine.tex deleted file mode 100644 index 2d188f63..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozAznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator *) = {mult_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozBznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozBznine.tex deleted file mode 100644 index 432e85e5..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozBznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator +) = {add_range, add_int, add_vec, add_vec_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozDznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozDznine.tex deleted file mode 100644 index d671e6b0..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozDznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator -) = {sub_range, sub_int, sub_vec, sub_vec_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozFznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozFznine.tex deleted file mode 100644 index 3c2e441c..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozFznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator /) = {quotient_nat, quotient}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozIsznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozIsznine.tex deleted file mode 100644 index 9b4ebe19..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozIsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator <_s : forall 'n, 'n > 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozIuznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozIuznine.tex deleted file mode 100644 index 5b54235e..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozIuznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator <_u : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozIzIznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozIzIznine.tex deleted file mode 100644 index 51ff2b6c..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozIzIznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator <<) = {shift_bits_left, shiftl}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozIzJznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozIzJznine.tex deleted file mode 100644 index d23f28dd..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozIzJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator <=) = {lteq_atom, lteq_range_atom, lteq_atom_range, lteq_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozIznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozIznine.tex deleted file mode 100644 index 8e5e3fe9..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozIznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator <) = {lt_atom, lt_range_atom, lt_atom_range, lt_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozJzJznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozJzJznine.tex deleted file mode 100644 index 57ea823c..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozJzJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ==) = {eq_anything}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJsznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJsznine.tex deleted file mode 100644 index 032e8600..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator >=_s : forall 'n, 'n > 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJuznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJuznine.tex deleted file mode 100644 index eaa72e60..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJuznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator >=_u : forall 'n, 'n >= 0. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('n)) -> bool diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJznine.tex deleted file mode 100644 index 5733b740..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator >=) = {gteq_atom, gteq_range_atom, gteq_atom_range, gteq_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzKsznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozKzKsznine.tex deleted file mode 100644 index 0f0793a6..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzKsznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator >>_s = "shift_bits_right_arith" : forall 'n 'm. (#\hyperref[zbits]{bits}#('n), #\hyperref[zbits]{bits}#('m)) -> #\hyperref[zbits]{bits}#('n) effect {undef} diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzKznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozKzKznine.tex deleted file mode 100644 index b129e9d2..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozKzKznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator >>) = {shift_bits_right, shiftr}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozKznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozKznine.tex deleted file mode 100644 index a8da7e48..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozKznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator >) = {gt_atom, gt_range_atom, gt_atom_range, gt_int}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozQzQznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozQzQznine.tex deleted file mode 100644 index 185f501e..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozQzQznine.tex +++ /dev/null @@ -1 +0,0 @@ -val operator ^^ = {lem: "replicate_bits"} : forall 'n 'm, 'm >= 0 . (#\hyperref[zbits]{bits}#('n), atom('m)) -> #\hyperref[zbits]{bits}#('n * 'm) diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozQznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozQznine.tex deleted file mode 100644 index 106b6064..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozQznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator ^) = {xor_vec, int_power}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozUznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozUznine.tex deleted file mode 100644 index 4de737e0..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozUznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator |) = {or_bool, or_bits}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozfiveznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozfiveznine.tex deleted file mode 100644 index 8d6b54c3..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozfiveznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator %) = {modulus}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozonezJznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozonezJznine.tex deleted file mode 100644 index 22052668..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozonezJznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator !=) = {neq_atom, neq_int, neq_vec, neq_anything}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczeightoperatorzzerozsixznine.tex b/cheri/sail_latexcc/sailcczeightoperatorzzerozsixznine.tex deleted file mode 100644 index 248fb15e..00000000 --- a/cheri/sail_latexcc/sailcczeightoperatorzzerozsixznine.tex +++ /dev/null @@ -1 +0,0 @@ -overload (operator &) = {and_bool, and_bits}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczzeroextend.tex b/cheri/sail_latexcc/sailcczzeroextend.tex deleted file mode 100644 index 0f754d44..00000000 --- a/cheri/sail_latexcc/sailcczzeroextend.tex +++ /dev/null @@ -1 +0,0 @@ -overload zero_extend = {mips_zero_extend}
\ No newline at end of file diff --git a/cheri/sail_latexcc/sailcczzeros.tex b/cheri/sail_latexcc/sailcczzeros.tex deleted file mode 100644 index 1c251eda..00000000 --- a/cheri/sail_latexcc/sailcczzeros.tex +++ /dev/null @@ -1 +0,0 @@ -val zeros : forall 'n, 'n >= 0 . unit -> #\hyperref[zbits]{bits}#('n) diff --git a/mips/.gitignore b/mips/.gitignore deleted file mode 100644 index 2ee9fde0..00000000 --- a/mips/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -mips.lem -mips_types.lem -mipsScript.sml -mips_typesScript.sml -mips_extrasScript.sml
\ No newline at end of file diff --git a/mips/Holmakefile b/mips/Holmakefile deleted file mode 100644 index a31bfd4f..00000000 --- a/mips/Holmakefile +++ /dev/null @@ -1,11 +0,0 @@ -LEMDIR=../../lem/hol-lib - -INCLUDES = $(LEMDIR) ../lib/hol - -all: mipsTheory.uo -.PHONY: all - -ifdef POLY -BASE_HEAP = ../lib/hol/sail-heap - -endif diff --git a/mips/LOOKING_FOR_SOMETHING.txt b/mips/LOOKING_FOR_SOMETHING.txt new file mode 100644 index 00000000..1f462863 --- /dev/null +++ b/mips/LOOKING_FOR_SOMETHING.txt @@ -0,0 +1 @@ +The mips spec. now lives at https://github.com/CTSRD-CHERI/sail-cheri-mips . diff --git a/mips/Makefile b/mips/Makefile deleted file mode 100644 index a156428a..00000000 --- a/mips/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -THIS_MAKEFILE := $(realpath $(lastword $(MAKEFILE_LIST))) -SAIL_DIR:=$(realpath $(dir $(THIS_MAKEFILE))..) -export SAIL_DIR -SAIL_LIB_DIR:=$(SAIL_DIR)/lib -MIPS_SAIL_DIR:=$(SAIL_DIR)/mips - -SAIL:=$(SAIL_DIR)/sail - -MIPS_PRE:=$(MIPS_SAIL_DIR)/prelude.sail $(MIPS_SAIL_DIR)/mips_prelude.sail -MIPS_TLB:=$(MIPS_SAIL_DIR)/mips_tlb.sail -MIPS_TLB_STUB:=$(MIPS_SAIL_DIR)/mips_tlb_stub.sail -MIPS_SAILS:=$(MIPS_SAIL_DIR)/mips_wrappers.sail $(MIPS_SAIL_DIR)/mips_ast_decl.sail $(MIPS_SAIL_DIR)/mips_insts.sail $(MIPS_SAIL_DIR)/mips_ri.sail $(MIPS_SAIL_DIR)/mips_epilogue.sail -MIPS_MAIN:=$(MIPS_SAIL_DIR)/main.sail - -mips: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS) $(MIPS_MAIN) ../sail - $(SAIL) -ocaml -o mips -memo_z3 $(filter %.sail, $^) - -mips.c: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS) $(MIPS_MAIN) Makefile ../sail - $(SAIL) -O -memo_z3 -c $(filter %.sail, $^) 1> $@ - -C_WARNINGS=-Wall -Wno-unused-but-set-variable -Wno-unused-label -Wno-unused-function -Wno-maybe-uninitialized -C_OPT=-O2 -GCOV_FLAGS= -mips_c: mips.c ../lib/sail.h ../lib/*.c Makefile - gcc $(C_OPT) $(C_WARNINGS) $(GCOV_FLAGS) -g -I ../lib $< ../lib/*.c -lgmp -lz -o $@ - -# Note that for coverage purposes O1 appears optimal. O0 means lots of obviously dead code but O2 risks reducing granularity too much. -mips_c_gcov: C_OPT=-O1 -mips_c_gcov: GCOV_FLAGS=-fprofile-arcs -ftest-coverage -mips_c_gcov: mips_c - -gcovr: - gcovr -r . --html --html-detail -o index.html - -sim.dtb: sim.dts - dtc -O dtb -o $@ -b 0 $< - -mips_no_tlb.lem: $(MIPS_PRE) $(MIPS_TLB_STUB) $(MIPS_SAILS) - $(SAIL) -lem -o mips_no_tlb -lem_mwords -lem_lib Mips_extras -undefined_gen -memo_z3 $^ -mips_no_tlb_types.lem: mips_no_tlb.lem - -mips.lem: $(MIPS_PRE) $(SAIL_LIB_DIR)/mono_rewrites.sail $(MIPS_TLB) $(MIPS_SAILS) - $(SAIL) -lem -o mips -auto_mono -mono_rewrites -lem_mwords -lem_lib Mips_extras -undefined_gen -memo_z3 $^ -mips_types.lem: mips.lem - -mips.v: $(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS) - $(SAIL) -coq -dcoq_undef_axioms -o mips -coq_lib mips_extras -undefined_gen -memo_z3 $^ -mips_types.v: mips.v - -MIPS_COQ = mips_types.v mips_extras.v mips.v -COQ_LIBS = -R ../../bbv/theories bbv -R ../lib/coq Sail - -%.vo: %.v - coqc $(COQ_LIBS) $< -mips.vo: mips_types.vo mips_extras.vo - -M%.thy: m%.lem m%_types.lem mips_extras.lem - lem -isa -outdir . -lib Sail=$(SAIL_DIR)/src/gen_lib -lib Sail=$(SAIL_DIR)/src/lem_interp $^ - sed -i 's/datatype ast/datatype (plugins only: size) ast/' M$*_types.thy - -%Script.sml: %.lem %_types.lem $(MIPS_SAIL_DIR)/mips_extras.lem - lem -hol -outdir . -lib $(SAIL_DIR)/lib/hol -i $(SAIL_DIR)/lib/hol/sail2_prompt_monad.lem -i $(SAIL_DIR)/lib/hol/sail2_prompt.lem -lib $(SAIL_DIR)/src/gen_lib -lib $(SAIL_DIR)/src/lem_interp $^ - -%Theory.uo: %Script.sml - Holmake $@ - -LOC_FILES:=$(MIPS_PRE) $(MIPS_TLB) $(MIPS_SAILS) $(MIPS_MAIN) -include ../etc/loc.mk - -clean: - rm -rf mips Mips.thy mips.lem mips_types.lem _sbuild mips.c mips_c - rm -f mipsScript.sml mips_typesScript.sml mips_extrasScript.sml - rm -f mips.v mips_types.v $(MIPS_COQ:%.v=%.vo) $(MIPS_COQ:%.v=%.glob) $(MIPS_COQ:%.v=.%.aux) - -Holmake cleanAll diff --git a/mips/README b/mips/README deleted file mode 100644 index 8a641e69..00000000 --- a/mips/README +++ /dev/null @@ -1,24 +0,0 @@ -This directory contains a MIPS64-style architecture specification -written in Sail. To support integration with the CHERI ISA it is -split across several files, which must be given to sail in the -following order: - - 1. mips_prelude.sail contains definitions used in the rest of the - ISA, including register declarations and helper functions, for - example for performing address translation. - - 2. mips_wrappers.sail contains wrappers and hooks around certain - functions. In straight MIPS these are mostly identity functions, but - on CHERI they are substituted for functions which implement - CHERI-specific behaviour. - - 3. mips_insts.sail contains descriptions of instructions in the form - of AST members, decode and execute function clauses (using Sail's - scattered union/function definitions). - - 4. mips_epilogue.sail just closes the function and AST union definitions. - -The CHERI sail model extends this model by adding more declarations in a -file cheri_prelude.sail, included after mips_prelude.sail, replacing -the functions in mips_wrappers.sail and adding new instruction -definitions in cheri_insts.sail. diff --git a/mips/_CoqProject b/mips/_CoqProject deleted file mode 100644 index ad38d28d..00000000 --- a/mips/_CoqProject +++ /dev/null @@ -1,2 +0,0 @@ --R ../../bbv/theories bbv --R ../lib/coq Sail
\ No newline at end of file diff --git a/mips/doc/Makefile b/mips/doc/Makefile deleted file mode 100644 index 0220a4cc..00000000 --- a/mips/doc/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -all: - cat preamble.tex ../mips_prelude.sail ../mips_wrappers.sail ../mips_insts.sail ../mips_epilogue.sail postamble.tex > mips_all.tex - pdflatex mips_all.tex - -clean: - rm -rf *~ - rm -rf mips_all.* diff --git a/mips/doc/postamble.tex b/mips/doc/postamble.tex deleted file mode 100644 index 892ef896..00000000 --- a/mips/doc/postamble.tex +++ /dev/null @@ -1,2 +0,0 @@ -\end{lstlisting} -\end{document} diff --git a/mips/doc/preamble.tex b/mips/doc/preamble.tex deleted file mode 100644 index 524ec736..00000000 --- a/mips/doc/preamble.tex +++ /dev/null @@ -1,177 +0,0 @@ - -\documentclass[10pt]{article} - -\usepackage[margin=1.0in]{geometry} -\usepackage[T1]{fontenc} -\usepackage[scaled=0.82]{beramono} - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -% for Lem listing -\usepackage[scaled=0.82]{beramono} -\usepackage{listings} - -\newsavebox{\codebox} - -\lstdefinelanguage{SailExtraKeywords} - {morekeywords= { -% from the sail lexer -and, -alias, -as, -bitzero, -bitone, -bits, -by, -case, -clause, -const, -dec, -default, -deinfix, -effect, -Effect, -end, -enumerate, -else, -exit, -extern, -false, -forall, -foreach, -function, -if, -in, -inc, -IN, -let, -member, -Nat, -Order, -pure, -rec, -register, -scattered, -struct, -switch, -then, -true, -Type, -typedef, -undefined, -union, -with, -val, -div, -mod, -quot, -rem, -barr, -rreg, -wreg, -rmem, -wmem, -undef, -unspec, -nondet, -bool,unit,vector,range,list,bit,nat, int, uint8,uint16,uint32,uint64,implicit -} -} - -\lstdefinelanguage{LemExtraKeywords} - {morekeywords= { -% from the lem lexer - as, - fun, - function, - with, - match, - let, - and, - in, - of, - rec, - type, - module, - rename, - struct, - end, - open, - import, - include, - true, - false, - begin, - if, - then, - else, - val, - class, - instance, - default_instance, - indreln, - forall, - exists, - inline, - lem_transform, - IN, - MEM, - declare, - infix, - field, - automatic, - manual, - exhaustive, - inexhaustive, - ascii_rep, - compile_message, - set_flag, - termination_argument, - pattern_match, - right_assoc, - left_assoc, - non_assoc, - special, - target_rep, - target_type, - target_const, - lemma, - assert, - theorem, - do, - witness, - check, - % coq notation - Inductive, - Prop, -% names of targets, - ocaml, - html, - coq, - hol, - isabelle, -% these seem to be used as keywors in indreln? - input, - output, -% and more keywords for specific target code that we quote - case, - definition, -} -} - -%\lstset{basicstyle=\footnotesize\ttfamily} % -%\lstset{keywordstyle=\pmb} -%\lstset{basicstyle=\footnotesize\ttfamily} % -\lstset{basicstyle=\ttfamily} % -\lstset{keywordstyle=\bfseries} -\lstset{language=Caml} -\lstset{defaultdialect=[Objective]Caml} -\lstset{alsolanguage=SailExtraKeywords} -\lstset{mathescape} - -\lstset{escapeinside={<@}{@>}} - -%%%%%%%%%%%%%%%%%%%%%%%%%%% - -\begin{document} - -\begin{lstlisting} diff --git a/mips/gen/ast.hgen b/mips/gen/ast.hgen deleted file mode 100644 index a251adff..00000000 --- a/mips/gen/ast.hgen +++ /dev/null @@ -1,18 +0,0 @@ -| `MIPSThreadStart -| `MIPSRType of mipsRTypeOp * reg * reg * reg -| `MIPSIType of mipsITypeOp * reg * reg * bit16 -| `MIPSShiftI of mipsShiftIOp * reg * reg * bit5 -| `MIPSShiftV of mipsShiftVOp * reg * reg * reg -| `MIPSMulDiv of mipsMulDivOp * reg * reg -| `MIPSMFHiLo of mipsMFHiLoOp * reg -| `MIPSLUI of reg * bit16 -| `MIPSLoad of mipsWordWidth * bool * bool * reg * reg * bit16 (* width, signed, linked, base, rt, offset *) -| `MIPSStore of mipsWordWidth * bool * reg * reg * bit16 (* width, conditional, base, rt, offset *) -| `MIPSLSLR of bool * bool * bool * reg * reg * bit16 (* store, double, left, base, rt, offset *) -| `MIPSSYNC -| `MIPSBEQ of reg * reg * bit16 * bool * bool (* rs, rt, offset, not equal, likely *) -| `MIPSBCMPZ of reg * bit16 * mipsCmp * bool * bool (* rs, offset, cmp, link, likely *) -| `MIPSJ of bit26 -| `MIPSJAL of bit26 -| `MIPSJR of reg -| `MIPSJALR of reg * reg (* rs, rd *) diff --git a/mips/gen/fold.hgen b/mips/gen/fold.hgen deleted file mode 100644 index 05b9c808..00000000 --- a/mips/gen/fold.hgen +++ /dev/null @@ -1,19 +0,0 @@ -| `MIPSThreadStart -> (y_reg, y_sreg) -| `MIPSRType (op, rd, rs, rt) -> fold_reg rt (fold_reg rs (fold_reg rd (y_reg, y_sreg))) -| `MIPSIType (op, rs, rt, imm) -> fold_reg rs (fold_reg rt (y_reg, y_sreg)) -| `MIPSShiftI (op, rd, rt, imm) -> fold_reg rt (fold_reg rd (y_reg, y_sreg)) -| `MIPSShiftV (op, rd, rt, rs) -> fold_reg rs (fold_reg rt (fold_reg rd (y_reg, y_sreg))) -| `MIPSMulDiv (op, rs, rt) -> fold_reg rs (fold_reg rt (y_reg, y_sreg)) -| `MIPSMFHiLo (op, rs) -> fold_reg rs (y_reg, y_sreg) -| `MIPSLUI (rt, imm) -> fold_reg rt (y_reg, y_sreg) -| `MIPSLoad (width, signed, linked, base, rt, offset) -> fold_reg rt (fold_reg base (y_reg, y_sreg)) -| `MIPSStore (width, conditional, base, rt, offset) -> fold_reg rt (fold_reg base (y_reg, y_sreg)) -| `MIPSLSLR (store, double, left, base, rt, offset) -> fold_reg rt (fold_reg base (y_reg, y_sreg)) -| `MIPSSYNC -> (y_reg, y_sreg) -| `MIPSBEQ (rs, rt, offset, ne, likely) -> fold_reg rs (fold_reg rt (y_reg, y_sreg)) -| `MIPSBCMPZ (rs, offset, cmp, link, likely) -> fold_reg rs (y_reg, y_sreg) -| `MIPSJ (offset) -> (y_reg, y_sreg) -| `MIPSJAL (offset) -> fold_reg (IReg(R31)) (y_reg, y_sreg) -| `MIPSJR (rd) -> fold_reg rd (y_reg, y_sreg) -| `MIPSJALR (rd, rs) -> fold_reg rd (fold_reg rs (y_reg, y_sreg)) - diff --git a/mips/gen/herdtools_ast_to_shallow_ast.hgen b/mips/gen/herdtools_ast_to_shallow_ast.hgen deleted file mode 100644 index 7b1a58d9..00000000 --- a/mips/gen/herdtools_ast_to_shallow_ast.hgen +++ /dev/null @@ -1,121 +0,0 @@ -| `MIPSThreadStart -> - SYSCALL_THREAD_START - -| `MIPSStopFetching -> - ImplementationDefinedStopFetching0 - -(* Note different argument order, which reflects difference - between instruction encoding and asm format *) -| `MIPSRType (op, rd, rs, rt) -> - (translate_rtype_op op) - ( - translate_reg "rs" rs, - translate_reg "rt" rt, - translate_reg "rd" rd - ) - - -(* Note different argument order similar to above *) -| `MIPSIType (op, rt, rs, imm) -> - (translate_itype_op op) - ( - translate_reg "rs" rs, - translate_reg "rt" rt, - translate_imm16 "imm" imm - ) - - -| `MIPSShiftI (op, rd, rt, sa) -> - (translate_shifti_op op) - ( - translate_reg "rt" rt, - translate_reg "rd" rd, - translate_imm5 "sa" sa - ) - - -| `MIPSShiftV (op, rd, rt, rs) -> - (translate_shiftv_op op) - ( - translate_reg "rs" rs, - translate_reg "rt" rt, - translate_reg "rd" rd - ) - - -| `MIPSMulDiv (op, rs, rt) -> - (translate_muldiv_op op) - ( - translate_reg "rs" rs, - translate_reg "rt" rt - ) - - -| `MIPSMFHiLo (op, rs) -> - (translate_mfhilo_op op) - ( - translate_reg "rs" rs - ) - -| `MIPSLUI (rt, imm) -> - LUI - ( - translate_reg "rt" rt, - translate_imm16 "imm" imm - ) - -| `MIPSLoad (width, signed, linked, base, rt, offset) -> - Load - ( - translate_wordsize "width" width, - translate_bool "signed" signed, - translate_bool "linked" linked, - translate_reg "base" base, - translate_reg "rt" rt, - translate_imm16 "offset" offset - ) - -| `MIPSStore (width, conditional, base, rt, offset) -> - Store - ( - translate_wordsize "width" width, - translate_bool "conditional" conditional, - translate_reg "base" base, - translate_reg "rt" rt, - translate_imm16 "offset" offset - ) - -| `MIPSLSLR (store, double, left, base, rt, offset) -> - (translate_lslr_op store double left) - ( - translate_reg "base" base, - translate_reg "rt" rt, - translate_imm16 "offset" offset - ) - -| `MIPSSYNC -> SYNC -| `MIPSBEQ (rs, rt, offset, ne, likely) -> - BEQ - (translate_reg "rs" rs, - translate_reg "rt" rt, - translate_imm16 "offset" offset, - translate_bool "ne" ne, - translate_bool "likely" likely - ) - -| `MIPSBCMPZ (rs, offset, cmp, link, likely) -> - BCMPZ - (translate_reg "rs" rs, - translate_imm16 "offset" offset, - translate_cmp "cmp" cmp, - translate_bool "link" link, - translate_bool "likely" likely - ) -| `MIPSJ (offset) -> - J (translate_imm26 "offset" offset) -| `MIPSJAL (offset) -> - JAL (translate_imm26 "offset" offset) -| `MIPSJR(rd) -> - JR (translate_reg "rd" rd) -| `MIPSJALR(rd, rs) -> - JALR (translate_reg "rd" rd, translate_reg "rs" rs) diff --git a/mips/gen/herdtools_types_to_shallow_types.hgen b/mips/gen/herdtools_types_to_shallow_types.hgen deleted file mode 100644 index 5a0e3bfc..00000000 --- a/mips/gen/herdtools_types_to_shallow_types.hgen +++ /dev/null @@ -1,120 +0,0 @@ -let is_inc = false - -let translate_rtype_op op = uppercase (pp_rtype_op op) - -let translate_rtype_op op x = match op with - | MIPSROpADD -> ADD x - | MIPSROpADDU -> ADDU x - | MIPSROpAND -> AND x - | MIPSROpDADD -> DADD x - | MIPSROpDADDU -> DADDU x - | MIPSROpDSUB -> DSUB x - | MIPSROpDSUBU -> DSUBU x - | MIPSROpMOVN -> MOVN x - | MIPSROpMOVZ -> MOVZ x - | MIPSROpMUL -> MUL x - | MIPSROpNOR -> NOR x - | MIPSROpOR -> OR x - | MIPSROpSLT -> SLT x - | MIPSROpSLTU -> SLTU x - | MIPSROpSUB -> SUB x - | MIPSROpSUBU -> SUBU x - | MIPSROpXOR -> XOR x - -let translate_itype_op op x = match op with - | MIPSIOpADDI -> ADDI x - | MIPSIOpADDIU -> ADDIU x - | MIPSIOpANDI -> ANDI x - | MIPSIOpDADDI -> DADDI x - | MIPSIOpDADDIU -> DADDIU x - | MIPSIOpORI -> ORI x - | MIPSIOpSLTI -> SLTI x - | MIPSIOpSLTIU -> SLTIU x - | MIPSIOpXORI -> XORI x - -let translate_shifti_op op x = match op with - | MIPSDSLL -> DSLL x - | MIPSDSLL32 -> DSLL32 x - | MIPSDSRA -> DSRA x - | MIPSDSRA32 -> DSRA32 x - | MIPSDSRL -> DSRL x - | MIPSDSRL32 -> DSRL32 x - | MIPSSLL -> SLL x - | MIPSSRA -> SRA x - | MIPSSRL -> SRL x - -let translate_shiftv_op op x = match op with - | MIPSDSLLV -> DSLLV x - | MIPSDSRAV -> DSRAV x - | MIPSDSRLV -> DSRLV x - | MIPSSLLV -> SLLV x - | MIPSSRAV -> SRAV x - | MIPSSRLV -> SRLV x - -let translate_muldiv_op op x = match op with - | MIPSDDIV -> DDIV x - | MIPSDDIVU -> DDIVU x - | MIPSDIV -> DIV x - | MIPSDIVU -> DIVU x - | MIPSDMULT -> DMULT x - | MIPSDMULTU -> DMULTU x - | MIPSMADD -> MADD x - | MIPSMADDU -> MADDU x - | MIPSMSUB -> MSUB x - | MIPSMSUBU -> MSUBU x - | MIPSMULT -> MULT x - | MIPSMULTU -> MULTU x - -let translate_mfhilo_op op x = match op with - | MIPSMFHI -> MFHI x - | MIPSMFLO -> MFLO x - | MIPSMTHI -> MTHI x - | MIPSMTLO -> MTLO x - -let translate_load_op width signed linked = uppercase (pp_load_op width signed linked) - -let translate_store_op width conditional = uppercase (pp_store_op width conditional) - -let translate_lslr_op store double left x = match (store,double,left) with - | (false, false, true ) -> LWL x - | (false, false, false) -> LWR x - | (false, true , true ) -> LDL x - | (false, true , false) -> LDR x - | (true , false, true ) -> SWL x - | (true , false, false) -> SWR x - | (true , true , true ) -> SDL x - | (true , true , false) -> SDR x - -let translate_beq_op ne likely = uppercase (pp_beq_op ne likely) - -let translate_bcmpz_op cmp link likely = uppercase (pp_bcmpz_op cmp link likely) - - -let translate_reg name value = - Sail_values.to_vec0 is_inc (Nat_big_num.of_int 5,Nat_big_num.of_int (reg_to_int value)) - -let translate_imm26 name value = - Sail_values.to_vec0 is_inc (Nat_big_num.of_int 26,Nat_big_num.of_int value) -let translate_imm16 name value = - Sail_values.to_vec0 is_inc (Nat_big_num.of_int 16,Nat_big_num.of_int value) -let translate_imm5 name value = - Sail_values.to_vec0 is_inc (Nat_big_num.of_int 5,Nat_big_num.of_int value) -let translate_bool name = function - | true -> Sail_values.B1 - | false -> Sail_values.B0 - -let translate_wordsize _ = function - | MIPSByte -> Mips_embed_types.B2 - | MIPSHalf -> Mips_embed_types.H - | MIPSWord -> Mips_embed_types.W - | MIPSDouble -> Mips_embed_types.D - -let translate_cmp _ = function - | MIPS_EQ -> EQ' - | MIPS_NE -> NE - | MIPS_GE -> GE - | MIPS_GEU -> GEU - | MIPS_GT -> GT' - | MIPS_LE -> LE - | MIPS_LT -> LT' - | MIPS_LTU -> LTU diff --git a/mips/gen/lexer.hgen b/mips/gen/lexer.hgen deleted file mode 100644 index c01b14cc..00000000 --- a/mips/gen/lexer.hgen +++ /dev/null @@ -1,116 +0,0 @@ -"add" , RTYPE {txt="ADD" ; op=MIPSROpADD }; -"addu" , RTYPE {txt="ADDU" ; op=MIPSROpADDU }; -"and" , RTYPE {txt="AND" ; op=MIPSROpAND }; -"dadd" , RTYPE {txt="DADD" ; op=MIPSROpDADD }; -"daddu" , RTYPE {txt="DADDU" ; op=MIPSROpDADDU }; -"dsub" , RTYPE {txt="DSUB" ; op=MIPSROpDSUB }; -"dsubu" , RTYPE {txt="DSUBU" ; op=MIPSROpDSUBU }; -"movn" , RTYPE {txt="MOVN" ; op=MIPSROpMOVN }; -"movz" , RTYPE {txt="MOVZ" ; op=MIPSROpMOVZ }; -"mul" , RTYPE {txt="MUL" ; op=MIPSROpMUL }; -"nor" , RTYPE {txt="NOR" ; op=MIPSROpNOR }; -"or" , RTYPE {txt="OR" ; op=MIPSROpOR }; -"slt" , RTYPE {txt="SLT" ; op=MIPSROpSLT }; -"sltu" , RTYPE {txt="SLTU" ; op=MIPSROpSLTU }; -"sub" , RTYPE {txt="SUB" ; op=MIPSROpSUB }; -"subu" , RTYPE {txt="SUBU" ; op=MIPSROpSUBU }; -"xor" , RTYPE {txt="XOR" ; op=MIPSROpXOR }; - -"addi" , ITYPE {txt="ADDI" ; op=MIPSIOpADDI }; -"addiu" , ITYPE {txt="ADDIU" ; op=MIPSIOpADDIU }; -"andi" , ITYPE {txt="ANDI" ; op=MIPSIOpANDI }; -"daddi" , ITYPE {txt="DADDI" ; op=MIPSIOpDADDI }; -"daddiu", ITYPE {txt="DADDIU"; op=MIPSIOpDADDIU }; -"ori" , ITYPE {txt="ORI" ; op=MIPSIOpORI }; -"slti" , ITYPE {txt="SLTI" ; op=MIPSIOpSLTI }; -"sltiu" , ITYPE {txt="SLTIU" ; op=MIPSIOpSLTIU }; -"xori" , ITYPE {txt="XORI" ; op=MIPSIOpXORI }; - -"dsll" , SHIFTI {txt="DSLL" ; op=MIPSDSLL }; -"dsll32" , SHIFTI {txt="DSLL32" ; op=MIPSDSLL32 }; -"dsra" , SHIFTI {txt="DSRA" ; op=MIPSDSRA }; -"dsra32" , SHIFTI {txt="DSRA32" ; op=MIPSDSRA32 }; -"dsrl" , SHIFTI {txt="DSRL" ; op=MIPSDSRL }; -"dsrl32" , SHIFTI {txt="DSRL32" ; op=MIPSDSRL32 }; -"sll" , SHIFTI {txt="SLL" ; op=MIPSSLL }; -"sra" , SHIFTI {txt="SRA" ; op=MIPSSRA }; -"srl" , SHIFTI {txt="SRL" ; op=MIPSSRL }; - -"dsllv", SHIFTV {txt="DSLLV" ; op=MIPSDSLLV }; -"dsrav", SHIFTV {txt="DSRAV" ; op=MIPSDSRAV }; -"dsrlv", SHIFTV {txt="DSRLV" ; op=MIPSDSRLV }; -"sllv" , SHIFTV {txt="SLLV" ; op=MIPSSLLV }; -"srav" , SHIFTV {txt="SRAV" ; op=MIPSSRAV }; -"srlv" , SHIFTV {txt="SRLV" ; op=MIPSSRLV }; - -"ddiv" , MULDIV {txt="DDIV" ; op=MIPSDDIV }; -"ddivu" , MULDIV {txt="DDIVU" ; op=MIPSDDIVU }; -"div" , MULDIV {txt="DIV" ; op=MIPSDIV }; -"divu" , MULDIV {txt="DIVU" ; op=MIPSDIVU }; -"dmult" , MULDIV {txt="DMULT" ; op=MIPSDMULT }; -"dmultu", MULDIV {txt="DMULTU"; op=MIPSDMULTU }; -"madd" , MULDIV {txt="MADD" ; op=MIPSMADD }; -"maddu" , MULDIV {txt="MADDU" ; op=MIPSMADDU }; -"msub" , MULDIV {txt="MSUB" ; op=MIPSMSUB }; -"msubu" , MULDIV {txt="MSUBU" ; op=MIPSMSUBU }; -"mult" , MULDIV {txt="MULT" ; op=MIPSMULT }; -"multu" , MULDIV {txt="MULTU" ; op=MIPSMULTU }; - -"mfhi" , MFHILO {txt="MFHI" ; op=MIPSMFHI }; -"mflo" , MFHILO {txt="MFLO" ; op=MIPSMFLO }; -"mthi" , MFHILO {txt="MTHI" ; op=MIPSMTHI }; -"mtlo" , MFHILO {txt="MTLO" ; op=MIPSMTLO }; - -"lui" , LUI {txt="LUI" }; - -"lb" , LOAD {txt="LB" ; width=MIPSByte ; signed=true; linked=false }; -"lbu" , LOAD {txt="LBU" ; width=MIPSByte ; signed=false; linked=false }; -"lh" , LOAD {txt="LH" ; width=MIPSHalf ; signed=true; linked=false }; -"lhu" , LOAD {txt="LHU" ; width=MIPSHalf ; signed=false; linked=false }; -"lw" , LOAD {txt="LW" ; width=MIPSWord ; signed=true; linked=false }; -"lwu" , LOAD {txt="LWU" ; width=MIPSWord ; signed=false; linked=false }; -"ld" , LOAD {txt="LD" ; width=MIPSDouble ; signed=false; linked=false }; -"ll" , LOAD {txt="LL" ; width=MIPSWord ; signed=true; linked=true }; -"lld" , LOAD {txt="LLD" ; width=MIPSDouble ; signed=false; linked=true }; - -"sb" , STORE {txt="SB" ; width=MIPSByte ; conditional=false }; -"sh" , STORE {txt="SH" ; width=MIPSHalf ; conditional=false }; -"sw" , STORE {txt="SW" ; width=MIPSWord ; conditional=false }; -"sd" , STORE {txt="SD" ; width=MIPSDouble ; conditional=false }; -"sc" , STORE {txt="SC" ; width=MIPSWord ; conditional=true }; -"scd" , STORE {txt="SCD" ; width=MIPSDouble ; conditional=true }; - -"lwl" , LSLR {txt="LWL" ; store=false; double=false; left=true }; -"lwr" , LSLR {txt="LWR" ; store=false; double=false; left=false}; -"ldl" , LSLR {txt="LDL" ; store=false; double=true ; left=true }; -"ldr" , LSLR {txt="LDR" ; store=false; double=true ; left=false}; -"swl" , LSLR {txt="SWL" ; store=true ; double=false; left=true }; -"swr" , LSLR {txt="SWR" ; store=true ; double=false; left=false}; -"sdl" , LSLR {txt="SDL" ; store=true ; double=true ; left=true }; -"sdr" , LSLR {txt="SDR" ; store=true ; double=true ; left=false}; -"sync", SYNC {txt="SYNC"}; - -"beq", BEQ {txt="BEQ"; ne=false; likely=false }; -"beql", BEQ {txt="BEQ"; ne=false; likely=true }; -"bne", BEQ {txt="BEQ"; ne=true ; likely=false }; -"bnel", BEQ {txt="BEQ"; ne=true ; likely=true }; - -"bltz", BCMPZ {txt="BCMPZ"; cmp=MIPS_LT; likely=false; link=false }; -"bltzal", BCMPZ {txt="BCMPZ"; cmp=MIPS_LT; likely=false; link=true }; -"bltzl", BCMPZ {txt="BCMPZ"; cmp=MIPS_LT; likely=true; link=false }; -"bltzall",BCMPZ {txt="BCMPZ"; cmp=MIPS_LT; likely=true; link=true }; - -"bgez", BCMPZ {txt="BCMPZ"; cmp=MIPS_GE; likely=false; link=false }; -"bgezal", BCMPZ {txt="BCMPZ"; cmp=MIPS_GE; likely=false; link=true }; -"bgezl", BCMPZ {txt="BCMPZ"; cmp=MIPS_GE; likely=true; link=false }; -"bgezall",BCMPZ {txt="BCMPZ"; cmp=MIPS_GE; likely=true; link=true }; - -"bgtz", BCMPZ {txt="BCMPZ"; cmp=MIPS_GT; likely=false; link=false }; -"bgtzl", BCMPZ {txt="BCMPZ"; cmp=MIPS_GT; likely=true; link=false }; - -"blez", BCMPZ {txt="BCMPZ"; cmp=MIPS_LE; likely=false; link=false }; -"blezl", BCMPZ {txt="BCMPZ"; cmp=MIPS_LE; likely=true; link=false }; -"j", J {txt="J"}; -"jal", JAL {txt="JAL"}; -"jr", JR {txt="JR"}; -"jalr", JALR {txt="JALR"}; diff --git a/mips/gen/map.hgen b/mips/gen/map.hgen deleted file mode 100644 index f5116bae..00000000 --- a/mips/gen/map.hgen +++ /dev/null @@ -1,19 +0,0 @@ -| `MIPSThreadStart -> `MIPSThreadStart -| `MIPSRType (op, rd, rs, rt) -> `MIPSRType (op, map_reg rd, map_reg rs, map_reg rt) -| `MIPSIType (op, rs, rt, imm) -> `MIPSIType (op, map_reg rs, map_reg rt, imm) -| `MIPSShiftI (op, rd, rt, imm) -> `MIPSShiftI (op, map_reg rd, map_reg rt, imm) -| `MIPSShiftV (op, rd, rt, rs) -> `MIPSShiftV (op, map_reg rd, map_reg rt, map_reg rs) -| `MIPSMulDiv (op, rs, rt) -> `MIPSMulDiv (op, map_reg rs, map_reg rt) -| `MIPSMFHiLo (op, rs) -> `MIPSMFHiLo (op, map_reg rs) -| `MIPSLUI (rt, imm) -> `MIPSLUI (map_reg rt, imm) -| `MIPSLoad (width, signed, linked, base, rt, offset) -> `MIPSLoad (width, signed, linked, map_reg base, map_reg rt, offset) -| `MIPSStore (width, conditional, base, rt, offset) -> `MIPSStore (width, conditional, map_reg base, map_reg rt, offset) -| `MIPSLSLR (store, double, left, base, rt, offset) -> `MIPSLSLR (store, double, left, map_reg base, map_reg rt, offset) -| `MIPSSYNC -> `MIPSSYNC -| `MIPSBEQ (rs, rt, offset, ne, likely) -> `MIPSBEQ (map_reg rs, map_reg rt, offset, ne, likely) -| `MIPSBCMPZ (rs, offset, cmp, link, likely) -> `MIPSBCMPZ (map_reg rs, offset, cmp, link, likely) -| `MIPSJ (offset) -> `MIPSJ (offset) -| `MIPSJAL (offset) -> `MIPSJAL (offset) (* implicit R31? *) -| `MIPSJR (rd) -> `MIPSJR (map_reg rd) -| `MIPSJALR (rd, rs) -> `MIPSJALR(map_reg rd, map_reg rs) - diff --git a/mips/gen/parser.hgen b/mips/gen/parser.hgen deleted file mode 100644 index 8f573aa5..00000000 --- a/mips/gen/parser.hgen +++ /dev/null @@ -1,34 +0,0 @@ -| RTYPE reg COMMA reg COMMA reg - { `MIPSRType ($1.op, $2, $4, $6) } -| ITYPE reg COMMA reg COMMA NUM - { `MIPSIType ($1.op, $2, $4, $6) } -| SHIFTI reg COMMA reg COMMA NUM - { `MIPSShiftI ($1.op, $2, $4, $6) } -| SHIFTV reg COMMA reg COMMA reg - { `MIPSShiftV ($1.op, $2, $4, $6) } -| MULDIV reg COMMA reg - { `MIPSMulDiv ($1.op, $2, $4) } -| MFHILO reg - { `MIPSMFHiLo ($1.op, $2) } -| LUI reg COMMA NUM - { `MIPSLUI ($2, $4) } -| LOAD reg COMMA NUM LPAR reg RPAR - { `MIPSLoad ($1.width, $1.signed, $1.linked, $6, $2, $4) } -| STORE reg COMMA NUM LPAR reg RPAR - { `MIPSStore ($1.width, $1.conditional, $6, $2, $4) } -| LSLR reg COMMA NUM LPAR reg RPAR - { `MIPSLSLR ($1.store, $1.double, $1.left, $6, $2, $4) } -| SYNC - { `MIPSSYNC } -| BEQ reg COMMA reg COMMA NUM - { `MIPSBEQ ( $2, $4, $6, $1.ne, $1.likely) } -| BCMPZ reg COMMA NUM - { `MIPSBCMPZ ( $2, $4, $1.cmp, $1.link, $1.likely) } -| J NUM - { `MIPSJ ($2) } -| JAL NUM - { `MIPSJAL ($2) } -| JR reg - { `MIPSJR ($2) } -| JALR reg COMMA reg - { `MIPSJALR ($2, $4) } diff --git a/mips/gen/pretty.hgen b/mips/gen/pretty.hgen deleted file mode 100644 index 98f56f2e..00000000 --- a/mips/gen/pretty.hgen +++ /dev/null @@ -1,36 +0,0 @@ -| `MIPSThreadStart -> "syscall 0xfffff" (* thread start *) -| `MIPSStopFetching -> "STOP" (* TODO *) -| `MIPSRType (op, rd,rs,rt) -> - sprintf "%s %s,%s,%s" (pp_rtype_op op) (pp_reg rd) (pp_reg rs) (pp_reg rt) -| `MIPSIType (op,rd,rs,imm) -> - sprintf "%s %s,%s,%d" (pp_itype_op op) (pp_reg rd) (pp_reg rs) imm -| `MIPSShiftI (op, rs, rt, imm) -> - sprintf "%s %s,%s,%d" (pp_shifti_op op) (pp_reg rs) (pp_reg rt) imm -| `MIPSShiftV (op, rd,rs,rt) -> - sprintf "%s %s,%s,%s" (pp_shiftv_op op) (pp_reg rd) (pp_reg rs) (pp_reg rt) -| `MIPSMulDiv (op, rs, rt) -> - sprintf "%s %s,%s" (pp_muldiv_op op) (pp_reg rs) (pp_reg rt) -| `MIPSMFHiLo (op, rs) -> - sprintf "%s %s" (pp_mfhilo_op op) (pp_reg rs) -| `MIPSLUI (rt, imm) -> - sprintf "lui %s,%d" (pp_reg rt) imm -| `MIPSLoad (width, signed, linked, base, rt, offset) -> - sprintf "%s %s,%d(%s)" (pp_load_op width signed linked) (pp_reg rt) offset (pp_reg base) -| `MIPSStore (width, conditional, base, rt, offset) -> - sprintf "%s %s,%d(%s)" (pp_store_op width conditional) (pp_reg rt) offset (pp_reg base) -| `MIPSLSLR (store, double, left, base, rt, offset) -> - sprintf "%s %s,%d(%s)" (pp_lslr_op store double left) (pp_reg rt) offset (pp_reg base) -| `MIPSSYNC -> "sync" -| `MIPSBEQ (rs, rt, offset, ne, likely) -> - sprintf "%s %s,%s,.%+d" (pp_beq_op ne likely) (pp_reg rs) (pp_reg rt) offset -| `MIPSBCMPZ (rs, offset, cmp, link, likely) -> - sprintf "%s,%s,.%+d" (pp_bcmpz_op cmp link likely) (pp_reg rs) offset -| `MIPSJ (offset) -> - sprintf "j %d" offset -| `MIPSJAL (offset) -> - sprintf "jal %d" offset -| `MIPSJR(rd) -> - sprintf "jr %s" (pp_reg rd) -| `MIPSJALR(rd, rs) -> - sprintf "jalr %s,%s" (pp_reg rd) (pp_reg rs) - diff --git a/mips/gen/sail_trans_out.hgen b/mips/gen/sail_trans_out.hgen deleted file mode 100644 index f2d006e8..00000000 --- a/mips/gen/sail_trans_out.hgen +++ /dev/null @@ -1,98 +0,0 @@ -| ("SYSCALL_THREAD_START", []) -> `MIPSThreadStart -| ("ADD" , [rs; rt; rd]) -> `MIPSRType (MIPSROpADD , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("ADDU" , [rs; rt; rd]) -> `MIPSRType (MIPSROpADDU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("AND" , [rs; rt; rd]) -> `MIPSRType (MIPSROpAND , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("DADD" , [rs; rt; rd]) -> `MIPSRType (MIPSROpDADD , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("DADDU" , [rs; rt; rd]) -> `MIPSRType (MIPSROpDADDU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("DSUB" , [rs; rt; rd]) -> `MIPSRType (MIPSROpDSUB , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("DSUBU" , [rs; rt; rd]) -> `MIPSRType (MIPSROpDSUBU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("MOVN" , [rs; rt; rd]) -> `MIPSRType (MIPSROpMOVN , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("MOVZ" , [rs; rt; rd]) -> `MIPSRType (MIPSROpMOVZ , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("MUL" , [rs; rt; rd]) -> `MIPSRType (MIPSROpMUL , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("NOR" , [rs; rt; rd]) -> `MIPSRType (MIPSROpNOR , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("OR" , [rs; rt; rd]) -> `MIPSRType (MIPSROpOR , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("SLT" , [rs; rt; rd]) -> `MIPSRType (MIPSROpSLT , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("SLTU" , [rs; rt; rd]) -> `MIPSRType (MIPSROpSLTU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("SUB" , [rs; rt; rd]) -> `MIPSRType (MIPSROpSUB , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("SUBU" , [rs; rt; rd]) -> `MIPSRType (MIPSROpSUBU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| ("XOR" , [rs; rt; rd]) -> `MIPSRType (MIPSROpXOR , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) - -| ("ADDI" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpADDI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| ("ADDIU" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpADDIU ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| ("ANDI" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpANDI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_imm16 imm)) -| ("DADDI" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpDADDI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| ("DADDIU", [rs; rt; imm]) -> `MIPSIType (MIPSIOpDADDIU,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| ("ORI" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpORI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_imm16 imm)) -| ("SLTI" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpSLTI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| ("SLTIU" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpSLTIU ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| ("XORI" , [rs; rt; imm]) -> `MIPSIType (MIPSIOpXORI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_imm16 imm)) - -| ("DSLL" , [rt; rd; sa]) -> `MIPSShiftI (MIPSDSLL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("DSLL32" , [rt; rd; sa]) -> `MIPSShiftI (MIPSDSLL32 , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("DSRA" , [rt; rd; sa]) -> `MIPSShiftI (MIPSDSRA , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("DSRA32" , [rt; rd; sa]) -> `MIPSShiftI (MIPSDSRA32 , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("DSRL" , [rt; rd; sa]) -> `MIPSShiftI (MIPSDSRL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("DSRL32" , [rt; rd; sa]) -> `MIPSShiftI (MIPSDSRL32 , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("SLL" , [rt; rd; sa]) -> `MIPSShiftI (MIPSSLL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("SRA" , [rt; rd; sa]) -> `MIPSShiftI (MIPSSRA , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| ("SRL" , [rt; rd; sa]) -> `MIPSShiftI (MIPSSRL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) - -| "DSLLV" , [rs; rt; rd] -> `MIPSShiftV (MIPSDSLLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| "DSRAV" , [rs; rt; rd] -> `MIPSShiftV (MIPSDSRAV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| "DSRLV" , [rs; rt; rd] -> `MIPSShiftV (MIPSDSRLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| "SLLV" , [rs; rt; rd] -> `MIPSShiftV (MIPSSLLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| "SRAV" , [rs; rt; rd] -> `MIPSShiftV (MIPSSRAV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| "SRLV" , [rs; rt; rd] -> `MIPSShiftV (MIPSSRLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) - -| "DDIV" , [rs; rt] -> `MIPSMulDiv (MIPSDDIV , (translate_out_ireg rs), (translate_out_ireg rt)) -| "DDIVU" , [rs; rt] -> `MIPSMulDiv (MIPSDDIVU , (translate_out_ireg rs), (translate_out_ireg rt)) -| "DIV" , [rs; rt] -> `MIPSMulDiv (MIPSDIV , (translate_out_ireg rs), (translate_out_ireg rt)) -| "DIVU" , [rs; rt] -> `MIPSMulDiv (MIPSDIVU , (translate_out_ireg rs), (translate_out_ireg rt)) -| "DMULT" , [rs; rt] -> `MIPSMulDiv (MIPSDMULT , (translate_out_ireg rs), (translate_out_ireg rt)) -| "DMULTU", [rs; rt] -> `MIPSMulDiv (MIPSDMULTU , (translate_out_ireg rs), (translate_out_ireg rt)) -| "MADD" , [rs; rt] -> `MIPSMulDiv (MIPSMADD , (translate_out_ireg rs), (translate_out_ireg rt)) -| "MADDU" , [rs; rt] -> `MIPSMulDiv (MIPSMADDU , (translate_out_ireg rs), (translate_out_ireg rt)) -| "MSUB" , [rs; rt] -> `MIPSMulDiv (MIPSMSUB , (translate_out_ireg rs), (translate_out_ireg rt)) -| "MSUBU" , [rs; rt] -> `MIPSMulDiv (MIPSMSUBU , (translate_out_ireg rs), (translate_out_ireg rt)) -| "MULT" , [rs; rt] -> `MIPSMulDiv (MIPSMULT , (translate_out_ireg rs), (translate_out_ireg rt)) -| "MULTU" , [rs; rt] -> `MIPSMulDiv (MIPSMULTU , (translate_out_ireg rs), (translate_out_ireg rt)) - -| "MFHI" , [rs] -> `MIPSMFHiLo (MIPSMFHI, (translate_out_ireg rs)) -| "MFLO" , [rs] -> `MIPSMFHiLo (MIPSMFLO, (translate_out_ireg rs)) -| "MTHI" , [rs] -> `MIPSMFHiLo (MIPSMTHI, (translate_out_ireg rs)) -| "MTLO" , [rs] -> `MIPSMFHiLo (MIPSMTLO, (translate_out_ireg rs)) - -| "LUI" , [rt; imm] -> `MIPSLUI ((translate_out_ireg rt), (translate_out_imm16 imm)) -| "Load", [width; signed; linked; base; rt; offset] -> - `MIPSLoad ( - (translate_out_wordWidth width), - (translate_out_bool signed), - (translate_out_bool linked), - (translate_out_ireg base), - (translate_out_ireg rt), - (translate_out_simm16 offset) - ) -| "Store", [width; conditional; base; rt; offset] -> - `MIPSStore ( - (translate_out_wordWidth width), - (translate_out_bool conditional), - (translate_out_ireg base), - (translate_out_ireg rt), - (translate_out_simm16 offset) - ) -| "LWL", [base; rt; offset] -> `MIPSLSLR (false, false, true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "LWR", [base; rt; offset] -> `MIPSLSLR (false, false, false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "LDL", [base; rt; offset] -> `MIPSLSLR (false, true , true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "LDR", [base; rt; offset] -> `MIPSLSLR (false, true , false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "SWL", [base; rt; offset] -> `MIPSLSLR (true , false, true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "SWR", [base; rt; offset] -> `MIPSLSLR (true , false, false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "SDL", [base; rt; offset] -> `MIPSLSLR (true , true , true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "SDR", [base; rt; offset] -> `MIPSLSLR (true , true , false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| "SYNC", [] -> `MIPSSYNC -| "BEQ", [rs; rt; offset; ne; likely] -> `MIPSBEQ ((translate_out_ireg rs), (translate_out_ireg rt), (translate_out_simm16 offset), (translate_out_bool ne), (translate_out_bool likely)) -| "BCMPZ", [rs; offset; cmp; link; likely] -> `MIPSBCMPZ ((translate_out_ireg rs), (translate_out_simm16 offset), (translate_out_cmp cmp), (translate_out_bool link), (translate_out_bool likely)) -| "J", [offset] -> `MIPSJ (translate_out_imm26 offset) -| "JAL", [offset] -> `MIPSJAL (translate_out_imm26 offset) -| "JR", [rd] -> `MIPSJR (translate_out_ireg rd) -| "JALR", [rd; rs] -> `MIPSJALR (translate_out_ireg rd, translate_out_ireg rs) - diff --git a/mips/gen/shallow_ast_to_herdtools_ast.hgen b/mips/gen/shallow_ast_to_herdtools_ast.hgen deleted file mode 100644 index efe2c77e..00000000 --- a/mips/gen/shallow_ast_to_herdtools_ast.hgen +++ /dev/null @@ -1,98 +0,0 @@ -| SYSCALL_THREAD_START -> `MIPSThreadStart -| (ADD (rs, rt, rd)) -> `MIPSRType (MIPSROpADD , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (ADDU (rs, rt, rd)) -> `MIPSRType (MIPSROpADDU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (AND (rs, rt, rd)) -> `MIPSRType (MIPSROpAND , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (DADD (rs, rt, rd)) -> `MIPSRType (MIPSROpDADD , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (DADDU (rs, rt, rd)) -> `MIPSRType (MIPSROpDADDU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (DSUB (rs, rt, rd)) -> `MIPSRType (MIPSROpDSUB , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (DSUBU (rs, rt, rd)) -> `MIPSRType (MIPSROpDSUBU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (MOVN (rs, rt, rd)) -> `MIPSRType (MIPSROpMOVN , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (MOVZ (rs, rt, rd)) -> `MIPSRType (MIPSROpMOVZ , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (MUL (rs, rt, rd)) -> `MIPSRType (MIPSROpMUL , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (NOR (rs, rt, rd)) -> `MIPSRType (MIPSROpNOR , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (OR (rs, rt, rd)) -> `MIPSRType (MIPSROpOR , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (SLT (rs, rt, rd)) -> `MIPSRType (MIPSROpSLT , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (SLTU (rs, rt, rd)) -> `MIPSRType (MIPSROpSLTU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (SUB (rs, rt, rd)) -> `MIPSRType (MIPSROpSUB , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (SUBU (rs, rt, rd)) -> `MIPSRType (MIPSROpSUBU , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) -| (XOR (rs, rt, rd)) -> `MIPSRType (MIPSROpXOR , (translate_out_ireg rd), (translate_out_ireg rs), (translate_out_ireg rt)) - -| (ADDI (rs, rt, imm)) -> `MIPSIType (MIPSIOpADDI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| (ADDIU (rs, rt, imm)) -> `MIPSIType (MIPSIOpADDIU ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| (ANDI (rs, rt, imm)) -> `MIPSIType (MIPSIOpANDI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_imm16 imm)) -| (DADDI (rs, rt, imm)) -> `MIPSIType (MIPSIOpDADDI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| (DADDIU (rs, rt, imm)) -> `MIPSIType (MIPSIOpDADDIU,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| (ORI (rs, rt, imm)) -> `MIPSIType (MIPSIOpORI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_imm16 imm)) -| (SLTI (rs, rt, imm)) -> `MIPSIType (MIPSIOpSLTI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| (SLTIU (rs, rt, imm)) -> `MIPSIType (MIPSIOpSLTIU ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_simm16 imm)) -| (XORI (rs, rt, imm)) -> `MIPSIType (MIPSIOpXORI ,(translate_out_ireg rt), (translate_out_ireg rs), (translate_out_imm16 imm)) - -| (DSLL (rt, rd, sa)) -> `MIPSShiftI (MIPSDSLL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (DSLL32 (rt, rd, sa)) -> `MIPSShiftI (MIPSDSLL32 , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (DSRA (rt, rd, sa)) -> `MIPSShiftI (MIPSDSRA , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (DSRA32 (rt, rd, sa)) -> `MIPSShiftI (MIPSDSRA32 , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (DSRL (rt, rd, sa)) -> `MIPSShiftI (MIPSDSRL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (DSRL32 (rt, rd, sa)) -> `MIPSShiftI (MIPSDSRL32 , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (SLL (rt, rd, sa)) -> `MIPSShiftI (MIPSSLL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (SRA (rt, rd, sa)) -> `MIPSShiftI (MIPSSRA , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) -| (SRL (rt, rd, sa)) -> `MIPSShiftI (MIPSSRL , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_imm5 sa)) - -| DSLLV (rs, rt, rd) -> `MIPSShiftV (MIPSDSLLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| DSRAV (rs, rt, rd) -> `MIPSShiftV (MIPSDSRAV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| DSRLV (rs, rt, rd) -> `MIPSShiftV (MIPSDSRLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| SLLV (rs, rt, rd) -> `MIPSShiftV (MIPSSLLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| SRAV (rs, rt, rd) -> `MIPSShiftV (MIPSSRAV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) -| SRLV (rs, rt, rd) -> `MIPSShiftV (MIPSSRLV , (translate_out_ireg rd), (translate_out_ireg rt), (translate_out_ireg rs)) - -| DDIV (rs, rt) -> `MIPSMulDiv (MIPSDDIV , (translate_out_ireg rs), (translate_out_ireg rt)) -| DDIVU (rs, rt) -> `MIPSMulDiv (MIPSDDIVU , (translate_out_ireg rs), (translate_out_ireg rt)) -| DIV (rs, rt) -> `MIPSMulDiv (MIPSDIV , (translate_out_ireg rs), (translate_out_ireg rt)) -| DIVU (rs, rt) -> `MIPSMulDiv (MIPSDIVU , (translate_out_ireg rs), (translate_out_ireg rt)) -| DMULT (rs, rt) -> `MIPSMulDiv (MIPSDMULT , (translate_out_ireg rs), (translate_out_ireg rt)) -| DMULTU (rs, rt) -> `MIPSMulDiv (MIPSDMULTU , (translate_out_ireg rs), (translate_out_ireg rt)) -| MADD (rs, rt) -> `MIPSMulDiv (MIPSMADD , (translate_out_ireg rs), (translate_out_ireg rt)) -| MADDU (rs, rt) -> `MIPSMulDiv (MIPSMADDU , (translate_out_ireg rs), (translate_out_ireg rt)) -| MSUB (rs, rt) -> `MIPSMulDiv (MIPSMSUB , (translate_out_ireg rs), (translate_out_ireg rt)) -| MSUBU (rs, rt) -> `MIPSMulDiv (MIPSMSUBU , (translate_out_ireg rs), (translate_out_ireg rt)) -| MULT (rs, rt) -> `MIPSMulDiv (MIPSMULT , (translate_out_ireg rs), (translate_out_ireg rt)) -| MULTU (rs, rt) -> `MIPSMulDiv (MIPSMULTU , (translate_out_ireg rs), (translate_out_ireg rt)) - -| MFHI (rs) -> `MIPSMFHiLo (MIPSMFHI, (translate_out_ireg rs)) -| MFLO (rs) -> `MIPSMFHiLo (MIPSMFLO, (translate_out_ireg rs)) -| MTHI (rs) -> `MIPSMFHiLo (MIPSMTHI, (translate_out_ireg rs)) -| MTLO (rs) -> `MIPSMFHiLo (MIPSMTLO, (translate_out_ireg rs)) - -| LUI (rt, imm) -> `MIPSLUI ((translate_out_ireg rt), (translate_out_imm16 imm)) -| Load (width, signed, linked, base, rt, offset) -> - `MIPSLoad ( - (translate_out_wordWidth width), - (translate_out_bool signed), - (translate_out_bool linked), - (translate_out_ireg base), - (translate_out_ireg rt), - (translate_out_simm16 offset) - ) -| Store (width, conditional, base, rt, offset) -> - `MIPSStore ( - (translate_out_wordWidth width), - (translate_out_bool conditional), - (translate_out_ireg base), - (translate_out_ireg rt), - (translate_out_simm16 offset) - ) -| LWL (base, rt, offset) -> `MIPSLSLR (false, false, true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| LWR (base, rt, offset) -> `MIPSLSLR (false, false, false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| LDL (base, rt, offset) -> `MIPSLSLR (false, true , true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| LDR (base, rt, offset) -> `MIPSLSLR (false, true , false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| SWL (base, rt, offset) -> `MIPSLSLR (true , false, true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| SWR (base, rt, offset) -> `MIPSLSLR (true , false, false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| SDL (base, rt, offset) -> `MIPSLSLR (true , true , true , (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| SDR (base, rt, offset) -> `MIPSLSLR (true , true , false, (translate_out_ireg base), (translate_out_ireg rt), (translate_out_simm16 offset)) -| SYNC -> `MIPSSYNC -| BEQ (rs, rt, offset, ne, likely) -> `MIPSBEQ ((translate_out_ireg rs), (translate_out_ireg rt), (translate_out_simm16 offset), (translate_out_bool ne), (translate_out_bool likely)) -| BCMPZ (rs, offset, cmp, link, likely) -> `MIPSBCMPZ ((translate_out_ireg rs), (translate_out_simm16 offset), (translate_out_cmp cmp), (translate_out_bool link), (translate_out_bool likely)) -| J (offset) -> `MIPSJ (translate_out_imm26 offset) -| JAL (offset) -> `MIPSJAL (translate_out_imm26 offset) -| JR (rd) -> `MIPSJR (translate_out_ireg rd) -| JALR (rd, rs) -> `MIPSJALR (translate_out_ireg rd, translate_out_ireg rs) - diff --git a/mips/gen/shallow_types_to_herdtools_types.hgen b/mips/gen/shallow_types_to_herdtools_types.hgen deleted file mode 100644 index a02d83b7..00000000 --- a/mips/gen/shallow_types_to_herdtools_types.hgen +++ /dev/null @@ -1,39 +0,0 @@ -let translate_out_big_bit = Sail_values.unsigned - -let translate_out_int inst = (Nat_big_num.to_int (translate_out_big_bit inst)) -let translate_out_signed_int inst bits = - let i = (Nat_big_num.to_int (translate_out_big_bit inst)) in - if (i >= (1 lsl (bits - 1))) then - (i - (1 lsl bits)) else - i - -let translate_out_ireg ireg = IReg (int_to_ireg (translate_out_int ireg)) - -let translate_out_imm26 imm = translate_out_int imm - -let translate_out_imm16 imm = translate_out_int imm -let translate_out_simm16 imm = translate_out_signed_int imm 16 - -let translate_out_imm5 imm = translate_out_int imm - -let translate_out_bool = function - | Sail_values.B1 -> true - | Sail_values.B0 -> false - | _ -> failwith "translate_out_bool Undef" - - -let translate_out_wordWidth = function - | Mips_embed_types.B2 -> MIPSByte - | Mips_embed_types.H -> MIPSHalf - | Mips_embed_types.W -> MIPSWord - | Mips_embed_types.D -> MIPSDouble - -let translate_out_cmp = function - | Mips_embed_types.EQ' -> MIPS_EQ (* equal *) - | Mips_embed_types.NE -> MIPS_NE (* not equal *) - | Mips_embed_types.GE -> MIPS_GE (* signed greater than or equal *) - | Mips_embed_types.GEU -> MIPS_GEU (* unsigned greater than or equal *) - | Mips_embed_types.GT' -> MIPS_GT (* signed strictly greater than *) - | Mips_embed_types.LE -> MIPS_LE (* signed less than or equal *) - | Mips_embed_types.LT' -> MIPS_LT (* signed strictly less than *) - | Mips_embed_types.LTU -> MIPS_LTU (* unsigned less than or qual *) diff --git a/mips/gen/token_types.hgen b/mips/gen/token_types.hgen deleted file mode 100644 index 170b42d3..00000000 --- a/mips/gen/token_types.hgen +++ /dev/null @@ -1,39 +0,0 @@ -type token_RTYPE = {txt : string; op : mipsRTypeOp } -type token_ITYPE = {txt : string; op : mipsITypeOp } -type token_ShiftI = {txt : string; op : mipsShiftIOp } -type token_ShiftV = {txt : string; op : mipsShiftVOp } -type token_MulDiv = {txt : string; op : mipsMulDivOp } -type token_MFHiLo = {txt : string; op : mipsMFHiLoOp } -type token_LUI = {txt : string } -type token_Load = {txt : string; width: mipsWordWidth; signed : bool; linked : bool} -type token_Store = {txt : string; width: mipsWordWidth; conditional : bool} -type token_LSLR = {txt : string; store : bool; double : bool; left: bool } (* Load/Store Left/Right *) -type token_SYNC = {txt : string} -type token_BEQ = {txt : string; ne : bool; likely : bool } -type token_BCMPZ = {txt : string; cmp : mipsCmp; likely : bool; link : bool } -type token_J = {txt : string} -type token_JAL = {txt : string} -type token_JR = {txt : string} -type token_JALR = {txt : string} -(* -(regno, imm16, Comparison) TRAPIMM - -(regno, regno) RDHWR -(regno, regno, Comparison) TRAPREG -(regno, regno, bit[3], bool) MFC0 -(regno, regno, bit[3], bool) MTC0 -(regno, regno, imm16, bool, bool) BEQ -TLBP -TLBR -TLBWI -TLBWR - -regregimm16 CACHE -regregimm16 PREF - -unit BREAK -unit ERET -unit HCF -unit SYSCALL -unit WAIT -*)
\ No newline at end of file diff --git a/mips/gen/tokens.hgen b/mips/gen/tokens.hgen deleted file mode 100644 index 937c6354..00000000 --- a/mips/gen/tokens.hgen +++ /dev/null @@ -1,17 +0,0 @@ -%token <MIPSHGenBase.token_RTYPE> RTYPE -%token <MIPSHGenBase.token_ITYPE> ITYPE -%token <MIPSHGenBase.token_ShiftI> SHIFTI -%token <MIPSHGenBase.token_ShiftV> SHIFTV -%token <MIPSHGenBase.token_MulDiv> MULDIV -%token <MIPSHGenBase.token_MFHiLo> MFHILO -%token <MIPSHGenBase.token_LUI> LUI -%token <MIPSHGenBase.token_Load> LOAD -%token <MIPSHGenBase.token_Store> STORE -%token <MIPSHGenBase.token_LSLR> LSLR -%token <MIPSHGenBase.token_SYNC> SYNC -%token <MIPSHGenBase.token_BEQ> BEQ -%token <MIPSHGenBase.token_BCMPZ> BCMPZ -%token <MIPSHGenBase.token_J> J -%token <MIPSHGenBase.token_JAL> JAL -%token <MIPSHGenBase.token_JR> JR -%token <MIPSHGenBase.token_JALR> JALR diff --git a/mips/gen/trans_sail.hgen b/mips/gen/trans_sail.hgen deleted file mode 100644 index e42d1b19..00000000 --- a/mips/gen/trans_sail.hgen +++ /dev/null @@ -1,122 +0,0 @@ -| `MIPSThreadStart -> - ("SYSCALL_THREAD_START", [], []) -| `MIPSStopFetching -> - ("ImplementationDefinedStopFetching", - [], - []) - -(* Note different argument order, which reflects difference - between instruction encoding and asm format *) -| `MIPSRType (op, rd, rs, rt) -> - (translate_rtype_op op, - [ - translate_reg "rs" rs; - translate_reg "rt" rt; - translate_reg "rd" rd; - ], - []) - -(* Note different argument order similar to above *) -| `MIPSIType (op, rt, rs, imm) -> - (translate_itype_op op, - [ - translate_reg "rs" rs; - translate_reg "rt" rt; - translate_imm16 "imm" imm; - ], - []) - -| `MIPSShiftI (op, rd, rt, sa) -> - (translate_shifti_op op, - [ - translate_reg "rt" rt; - translate_reg "rd" rd; - translate_imm5 "sa" sa; - ], - []) - -| `MIPSShiftV (op, rd, rt, rs) -> - (translate_shiftv_op op, - [ - translate_reg "rs" rs; - translate_reg "rt" rt; - translate_reg "rd" rd; - ], - []) - -| `MIPSMulDiv (op, rs, rt) -> - (translate_muldiv_op op, - [ - translate_reg "rs" rs; - translate_reg "rt" rt; - ], - []) - -| `MIPSMFHiLo (op, rs) -> - (translate_mfhilo_op op, - [ - translate_reg "rs" rs; - ], - []) -| `MIPSLUI (rt, imm) -> - ("LUI", - [ - translate_reg "rt" rt; - translate_imm16 "imm" imm; - ], - []) -| `MIPSLoad (width, signed, linked, base, rt, offset) -> - ("Load", - [ - translate_wordsize "width" width; - translate_bool "signed" signed; - translate_bool "linked" linked; - translate_reg "base" base; - translate_reg "rt" rt; - translate_imm16 "offset" offset; - ], - []) -| `MIPSStore (width, conditional, base, rt, offset) -> - ("Store", - [ - translate_wordsize "width" width; - translate_bool "conditional" conditional; - translate_reg "base" base; - translate_reg "rt" rt; - translate_imm16 "offset" offset; - ], - []) -| `MIPSLSLR (store, double, left, base, rt, offset) -> - (translate_lslr_op store double left, - [ - translate_reg "base" base; - translate_reg "rt" rt; - translate_imm16 "offset" offset; - ], - []) -| `MIPSSYNC -> ("SYNC", [], []) -| `MIPSBEQ (rs, rt, offset, ne, likely) -> - ("BEQ", - [translate_reg "rs" rs; - translate_reg "rt" rt; - translate_imm16 "offset" offset; - translate_bool "ne" ne; - translate_bool "likely" likely; - ], []) - -| `MIPSBCMPZ (rs, offset, cmp, link, likely) -> - ("BCMPZ", - [translate_reg "rs" rs; - translate_imm16 "offset" offset; - translate_cmp "cmp" cmp; - translate_bool "link" link; - translate_bool "likely" likely; - ], []) -| `MIPSJ (offset) -> - ("J", [translate_imm26 "offset" offset;], []) -| `MIPSJAL (offset) -> - ("JAL", [translate_imm26 "offset" offset;], []) -| `MIPSJR(rd) -> - ("JR", [translate_reg "rd" rd;], []) -| `MIPSJALR(rd, rs) -> - ("JALR", [translate_reg "rd" rd; translate_reg "rs" rs;], []) diff --git a/mips/gen/types.hgen b/mips/gen/types.hgen deleted file mode 100644 index a1c61f4b..00000000 --- a/mips/gen/types.hgen +++ /dev/null @@ -1,209 +0,0 @@ -type mipsRTypeOp = -| MIPSROpADD -| MIPSROpADDU -| MIPSROpAND -| MIPSROpDADD -| MIPSROpDADDU -| MIPSROpDSUB -| MIPSROpDSUBU -| MIPSROpMOVN -| MIPSROpMOVZ -| MIPSROpMUL -| MIPSROpNOR -| MIPSROpOR -| MIPSROpSLT -| MIPSROpSLTU -| MIPSROpSUB -| MIPSROpSUBU -| MIPSROpXOR - -let pp_rtype_op = function -| MIPSROpADD -> "add" -| MIPSROpADDU -> "addu" -| MIPSROpAND -> "and" -| MIPSROpDADD -> "dadd" -| MIPSROpDADDU -> "daddu" -| MIPSROpDSUB -> "dsub" -| MIPSROpDSUBU -> "dsubu" -| MIPSROpMOVN -> "movn" -| MIPSROpMOVZ -> "movz" -| MIPSROpMUL -> "mul" -| MIPSROpNOR -> "nor" -| MIPSROpOR -> "or" -| MIPSROpSLT -> "slt" -| MIPSROpSLTU -> "sltu" -| MIPSROpSUB -> "sub" -| MIPSROpSUBU -> "subu" -| MIPSROpXOR -> "xor" - -type bit26 = int -type bit16 = int -type bit5 = int - -type mipsITypeOp = -| MIPSIOpADDI -| MIPSIOpADDIU -| MIPSIOpANDI -| MIPSIOpDADDI -| MIPSIOpDADDIU -| MIPSIOpORI -| MIPSIOpSLTI -| MIPSIOpSLTIU -| MIPSIOpXORI - -let pp_itype_op = function -| MIPSIOpADDI -> "addi" -| MIPSIOpADDIU -> "addiu" -| MIPSIOpANDI -> "andi" -| MIPSIOpDADDI -> "daddi" -| MIPSIOpDADDIU -> "daddiu" -| MIPSIOpORI -> "ori" -| MIPSIOpSLTI -> "slti" -| MIPSIOpSLTIU -> "sltiu" -| MIPSIOpXORI -> "xori" - -type mipsShiftIOp = -| MIPSDSLL -| MIPSDSLL32 -| MIPSDSRA -| MIPSDSRA32 -| MIPSDSRL -| MIPSDSRL32 -| MIPSSLL -| MIPSSRA -| MIPSSRL - -let pp_shifti_op = function -| MIPSDSLL -> "dsll" -| MIPSDSLL32 -> "dsll32" -| MIPSDSRA -> "dsra" -| MIPSDSRA32 -> "dsra32" -| MIPSDSRL -> "dsrl" -| MIPSDSRL32 -> "dsrl32" -| MIPSSLL -> "sll" -| MIPSSRA -> "sra" -| MIPSSRL -> "srl" - -type mipsShiftVOp = -| MIPSDSLLV -| MIPSDSRAV -| MIPSDSRLV -| MIPSSLLV -| MIPSSRAV -| MIPSSRLV - -let pp_shiftv_op = function -| MIPSDSLLV -> "dsllv" -| MIPSDSRAV -> "dsrav" -| MIPSDSRLV -> "dsrlv" -| MIPSSLLV -> "sllv" -| MIPSSRAV -> "srav" -| MIPSSRLV -> "srlv" - -type mipsMulDivOp = -| MIPSDDIV -| MIPSDDIVU -| MIPSDIV -| MIPSDIVU -| MIPSDMULT -| MIPSDMULTU -| MIPSMADD -| MIPSMADDU -| MIPSMSUB -| MIPSMSUBU -| MIPSMULT -| MIPSMULTU - -let pp_muldiv_op = function -| MIPSDDIV -> "ddiv" -| MIPSDDIVU -> "ddivu" -| MIPSDIV -> "div" -| MIPSDIVU -> "divu" -| MIPSDMULT -> "dmult" -| MIPSDMULTU -> "dmultu" -| MIPSMADD -> "madd" -| MIPSMADDU -> "maddu" -| MIPSMSUB -> "msub" -| MIPSMSUBU -> "msubu" -| MIPSMULT -> "mult" -| MIPSMULTU -> "multu" - -type mipsMFHiLoOp = -| MIPSMFHI -| MIPSMFLO -| MIPSMTHI -| MIPSMTLO - -let pp_mfhilo_op = function -| MIPSMFHI -> "mfhi" -| MIPSMFLO -> "mflo" -| MIPSMTHI -> "mthi" -| MIPSMTLO -> "mtlo" - -type mipsWordWidth = -| MIPSByte -| MIPSHalf -| MIPSWord -| MIPSDouble - -type mipsCmp = -| MIPS_EQ (* equal *) -| MIPS_NE (* not equal *) -| MIPS_GE (* signed greater than or equal *) -| MIPS_GEU (* unsigned greater than or equal *) -| MIPS_GT (* signed strictly greater than *) -| MIPS_LE (* signed less than or equal *) -| MIPS_LT (* signed strictly less than *) -| MIPS_LTU (* unsigned less than or qual *) - -let pp_load_op width signed linked = match (width, signed, linked) with - | (MIPSByte, true, false) -> "lb" - | (MIPSByte, false, false) -> "lbu" - | (MIPSHalf, true, false) -> "lh" - | (MIPSHalf, false, false) -> "lhu" - | (MIPSWord, true, false) -> "lw" - | (MIPSWord, false, false) -> "lwu" - | (MIPSDouble, false, false) -> "ld" - | (MIPSWord, true, true) -> "ll" - | (MIPSDouble, false, true) -> "lld" - | _ -> failwith "unexpected load op" - -let pp_store_op width conditional = match (width, conditional) with - | (MIPSByte, false) -> "sb" - | (MIPSHalf, false) -> "sh" - | (MIPSWord, false) -> "sw" - | (MIPSDouble, false) -> "sd" - | (MIPSWord, true) -> "sc" - | (MIPSDouble, true) -> "scd" - | _ -> failwith "unexpected store op" - -let pp_lslr_op store double left = match (store, double, left) with - | (false, false, true ) -> "lwl" - | (false, false, false) -> "lwr" - | (false, true , true ) -> "ldl" - | (false, true , false) -> "ldr" - | (true , false, true ) -> "swl" - | (true , false, false) -> "swr" - | (true , true , true ) -> "sdl" - | (true , true , false) -> "sdr" - -let pp_beq_op ne likely = match (ne, likely) with - | (false, false) -> "beq" - | (false, true) -> "beql" - | (true , false) -> "bne" - | (true , true) -> "bnel" - -let pp_bcmpz_op cmp link likely = match (cmp, likely, link) with -| (MIPS_LT, false , false ) -> "bltz" -| (MIPS_LT, false , true ) -> "bltzal" -| (MIPS_LT, true , false ) -> "bltzl" -| (MIPS_LT, true , true ) -> "bltzall" -| (MIPS_GE, false , false ) -> "bgez" -| (MIPS_GE, false , true ) -> "bgezal" -| (MIPS_GE, true , false ) -> "bgezl" -| (MIPS_GE, true , true ) -> "bgezall" -| (MIPS_GT, false , false ) -> "bgtz" -| (MIPS_GT, true , false ) -> "bgtzl" -| (MIPS_LE, false , false ) -> "blez" -| (MIPS_LE, true , false ) -> "blezl" -| _ -> failwith "unknown bcmpz instruction" diff --git a/mips/gen/types_sail_trans_out.hgen b/mips/gen/types_sail_trans_out.hgen deleted file mode 100644 index ebd31fcb..00000000 --- a/mips/gen/types_sail_trans_out.hgen +++ /dev/null @@ -1,47 +0,0 @@ -let translate_out_big_bit = function - | (name, Bvector _, bits) -> IInt.integer_of_bit_list bits - | _ -> assert false - -let translate_out_int inst = (Nat_big_num.to_int (translate_out_big_bit inst)) -let translate_out_signed_int inst bits = - let i = (Nat_big_num.to_int (translate_out_big_bit inst)) in - if (i >= (1 lsl (bits - 1))) then - (i - (1 lsl bits)) else - i - -let translate_out_ireg ireg = IReg (int_to_ireg (translate_out_int ireg)) - -let translate_out_imm26 imm = translate_out_int imm - -let translate_out_imm16 imm = translate_out_int imm -let translate_out_simm16 imm = translate_out_signed_int imm 16 - -let translate_out_imm5 imm = translate_out_int imm - -let translate_out_bool = function - | (name, Bit, [Bitc_one]) -> true - | (name, Bit, [Bitc_zero]) -> false - | _ -> assert false - -let translate_out_enum (name,_,bits) = - Nat_big_num.to_int (IInt.integer_of_bit_list bits) - -let translate_out_wordWidth inst = - match translate_out_enum inst with - | 0 -> MIPSByte - | 1 -> MIPSHalf - | 2 -> MIPSWord - | 3 -> MIPSDouble - | _ -> failwith "Unknown wordWidth in sail translate out" - -let translate_out_cmp inst = - match translate_out_enum inst with - | 0 -> MIPS_EQ (* equal *) - | 1 -> MIPS_NE (* not equal *) - | 2 -> MIPS_GE (* signed greater than or equal *) - | 3 -> MIPS_GEU (* unsigned greater than or equal *) - | 4 -> MIPS_GT (* signed strictly greater than *) - | 5 -> MIPS_LE (* signed less than or equal *) - | 6 -> MIPS_LT (* signed strictly less than *) - | 7 -> MIPS_LTU (* unsigned less than or qual *) - | _ -> failwith "Unknown mipsCmp in sail translate out" diff --git a/mips/gen/types_trans_sail.hgen b/mips/gen/types_trans_sail.hgen deleted file mode 100644 index 63880ae9..00000000 --- a/mips/gen/types_trans_sail.hgen +++ /dev/null @@ -1,44 +0,0 @@ -let translate_rtype_op op = uppercase (pp_rtype_op op) -let translate_itype_op op = uppercase (pp_itype_op op) -let translate_shifti_op op = uppercase (pp_shifti_op op) -let translate_shiftv_op op = uppercase (pp_shiftv_op op) -let translate_muldiv_op op = uppercase (pp_muldiv_op op) -let translate_mfhilo_op op = uppercase (pp_mfhilo_op op) -let translate_load_op width signed linked = uppercase (pp_load_op width signed linked) -let translate_store_op width conditional = uppercase (pp_store_op width conditional) -let translate_lslr_op store double left = uppercase (pp_lslr_op store double left) -let translate_beq_op ne likely = uppercase (pp_beq_op ne likely) -let translate_bcmpz_op cmp link likely = uppercase (pp_bcmpz_op cmp link likely) - -let translate_reg name value = - (name, Bvector (Some 5), bit_list_of_integer 5 (Nat_big_num.of_int (reg_to_int value))) -let translate_imm26 name value = - (name, Bvector (Some 26), bit_list_of_integer 26 (Nat_big_num.of_int value)) -let translate_imm16 name value = - (name, Bvector (Some 16), bit_list_of_integer 16 (Nat_big_num.of_int value)) -let translate_imm5 name value = - (name, Bvector (Some 5), bit_list_of_integer 5 (Nat_big_num.of_int value)) -let translate_bool name value = - (name, Bit, [if value then Bitc_one else Bitc_zero]) -let translate_enum enum_values name value = - let rec bit_count n = - if n = 0 then 0 - else 1 + (bit_count (n lsr 1)) in - let rec find_index element = function - | h::tail -> if h = element then 0 else 1 + (find_index element tail) - | _ -> failwith "translate_enum could not find value" - in - let size = bit_count (List.length enum_values) in - let index = find_index value enum_values in - (name, Range0 (Some size), IInt.bit_list_of_integer size (Nat_big_num.of_int index)) -let translate_wordsize = translate_enum [MIPSByte; MIPSHalf; MIPSWord; MIPSDouble] -let translate_cmp = translate_enum [ -MIPS_EQ ;(* equal *) -MIPS_NE ;(* not equal *) -MIPS_GE ;(* signed greater than or equal *) -MIPS_GEU ;(* unsigned greater than or equal *) -MIPS_GT ;(* signed strictly greater than *) -MIPS_LE ;(* signed less than or equal *) -MIPS_LT ;(* signed strictly less than *) -MIPS_LTU ;(* unsigned less than or qual *) -]
\ No newline at end of file diff --git a/mips/main.sail b/mips/main.sail deleted file mode 100644 index 8fc48f9a..00000000 --- a/mips/main.sail +++ /dev/null @@ -1,97 +0,0 @@ - -val cycle_limit_reached = { c: "cycle_limit_reached" } : unit -> bool - -function cycle_limit_reached() = false - -register instCount : int - -val fetch_and_execute : unit -> bool effect {barr, eamem, escape, rmem, rreg, wmv, wreg, undef, wmvt, rmemt} -function fetch_and_execute () = { - PC = nextPC; - inBranchDelay = branchPending; - branchPending = 0b0; - nextPC = if inBranchDelay then delayedPC else PC + 4; - cp2_next_pc(); - instCount = instCount + 1; - if UART_WRITTEN then { - putchar(unsigned(UART_WDATA)); - UART_WRITTEN = 0b0; - }; - /* the following skips are required on mips to fake the tag effects otherwise type checker complains */ - skip_rmemt(); - skip_wmvt(); - /* prerr_bits("PC: ", PC); */ - loop_again = true; - try { - let pc_pa = TranslatePC(PC); - /*print_bits("pa: ", pc_pa);*/ - let instr = MEMr_wrapper(pc_pa, 4); - /*print_bits("hex: ", instr);*/ - let instr_ast = decode(instr); - match instr_ast { - Some(HCF()) => { - print("simulation stopped due to halt instruction."); - loop_again = false - }, - Some(ast) => execute(ast), - None() => { print("Decode failed"); loop_again=false } /* Never expect this -- unknown instruction should actually result in reserved instruction ISA-level exception (see mips_ri.sail). */ - } - } catch { - ISAException() => () /*prerr_endline("EXCEPTION")*/ - /* ISA-level exception occurrred either during TranslatePC or execute -- - just continue from nextPC, which should have been set to the appropriate - exception vector (along with clearing branchPending etc.) . */ - }; - loop_again & not (cycle_limit_reached()); -} - -val elf_entry = { - ocaml: "Elf_loader.elf_entry", - lem: "elf_entry", - c: "elf_entry" -} : unit -> int - -val init_registers : bits(64) -> unit effect {wreg} - -function init_registers (initialPC) = { - init_cp0_state(); - init_cp2_state(); - nextPC = initialPC; -} - -function dump_mips_state () : unit -> unit = { - print_bits("DEBUG MIPS PC ", PC); - foreach (idx from 0 to 31) { - print(concat_str("DEBUG MIPS REG ", concat_str(string_of_int(idx), concat_str(" ", BitStr(rGPR(to_bits(5,idx))))))); - } -} - -val main : unit -> unit effect {barr, eamem, escape, rmem, rreg, undef, wmv, wreg, rmemt, wmvt} - -function main () = { - init_registers(to_bits(64, elf_entry())); - startTime = get_time_ns(); - while (fetch_and_execute()) do { - /* uncomment to print IPS every 10M instructions (~10s) - if (instCount == 10000000) then { - endTime = get_time_ns(); - elapsed = endTime - startTime; - inst_1e9 = instCount * 1000000000; - ips = inst_1e9 / elapsed; - print_int("*IPS*: ", ips); - startTime = get_time_ns(); - instCount = 0; - };*/ - (); - }; - - endTime = get_time_ns(); - elapsed = endTime - startTime; - inst_1e9 = instCount * 1000000000; - ips = inst_1e9 / elapsed; - dump_mips_state (); - dump_cp2_state (); - print_int("Executed instructions: ", instCount); - print_int("Nanoseconds elapsed: ", elapsed); - print_int("Instructions per second: ", ips); -} diff --git a/mips/mips_ast_decl.sail b/mips/mips_ast_decl.sail deleted file mode 100644 index e39bc270..00000000 --- a/mips/mips_ast_decl.sail +++ /dev/null @@ -1,44 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* misp_insts.sail: mips instruction decode and execute clauses and AST node - declarations */ - -scattered union ast - -val execute : ast -> unit effect {barr, eamem, escape, rmem, rreg, undef, wmv, wreg} -scattered function execute - -val decode : bits(32) -> option(ast) effect pure -scattered function decode diff --git a/mips/mips_epilogue.sail b/mips/mips_epilogue.sail deleted file mode 100644 index c7477a50..00000000 --- a/mips/mips_epilogue.sail +++ /dev/null @@ -1,42 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* mips_epilogue.sail: end of decode, execute and AST definitions. */ - -end decode -end execute -end ast - -val supported_instructions : ast -> option(ast) -function supported_instructions instr = Some(instr) diff --git a/mips/mips_extras.lem b/mips/mips_extras.lem deleted file mode 100644 index 4edb0066..00000000 --- a/mips/mips_extras.lem +++ /dev/null @@ -1,128 +0,0 @@ -open import Pervasives -open import Pervasives_extra -open import Sail2_instr_kinds -open import Sail2_values -open import Sail2_operators -open import Sail2_prompt_monad -open import Sail2_prompt - -val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e -val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e -val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e -val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e - -let MEMr addr size = read_mem Read_plain addr size -let MEMr_reserve addr size = read_mem Read_reserve addr size - -val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e -let read_tag_bool addr = - read_tag addr >>= fun t -> - maybe_fail "read_tag_bool" (bool_of_bitU t) - -val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e -let write_tag_bool addr t = write_tag addr (bitU_of_bool t) >>= fun _ -> return () - -let MEMr_tag addr size = - read_mem Read_plain addr size >>= fun v -> - read_tag_bool addr >>= fun t -> - return (t, v) - -let MEMr_tag_reserve addr size = - read_mem Read_plain addr size >>= fun v -> - read_tag_bool addr >>= fun t -> - return (t, v) - - -val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e - -let MEMea addr size = write_mem_ea Write_plain addr size -let MEMea_conditional addr size = write_mem_ea Write_conditional addr size - -let MEMea_tag addr size = write_mem_ea Write_plain addr size -let MEMea_tag_conditional addr size = write_mem_ea Write_conditional addr size - - -val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e -val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e -val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e -val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e - -let MEMval _ size v = write_mem_val v >>= fun _ -> return () -let MEMval_conditional _ size v = write_mem_val v >>= fun b -> return (if b then true else false) -let MEMval_tag addr size t v = write_mem_val v >>= fun _ -> write_tag_bool addr t >>= fun _ -> return () -let MEMval_tag_conditional addr size t v = write_mem_val v >>= fun b -> write_tag_bool addr t >>= fun _ -> return (if b then true else false) - -val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e - -let MEM_sync () = barrier Barrier_MIPS_SYNC - -(* Some wrappers copied from aarch64_extras *) -(* TODO: Harmonise into a common library *) - -let get_slice_int_bl len n lo = - (* TODO: Is this the intended behaviour? *) - let hi = lo + len - 1 in - let bs = bools_of_int (hi + 1) n in - subrange_list false bs hi lo - -val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -let get_slice_int len n lo = of_bools (get_slice_int_bl len n lo) - -let write_ram _ size _ addr data = - MEMea addr size >> - MEMval addr size data - -let read_ram _ size _ addr = MEMr addr size - -let string_of_int = show - -let shift_bits_left v n = - let r = Maybe.bind (unsigned n) (fun n -> of_bits (shiftl_bv v n)) in - maybe_fail "shift_bits_left" r -let shift_bits_right v n = - let r = Maybe.bind (unsigned n) (fun n -> of_bits (shiftr_bv v n)) in - maybe_fail "shift_bits_right" r -let shift_bits_right_arith v n = - let r = Maybe.bind (unsigned n) (fun n -> of_bits (arith_shiftr_bv v n)) in - maybe_fail "shift_bits_right_arith" r - -(* Use constants for undefined values for now *) -let undefined_string () = return "" -let undefined_unit () = return () -let undefined_int () = return (0:ii) -val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e -let undefined_vector len u = return (repeat [u] len) -val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e -let undefined_bitvector len = return (of_bools (repeat [false] len)) -val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e -let undefined_bits = undefined_bitvector -let undefined_bit () = return B0 -let undefined_real () = return (realFromFrac 0 1) -let undefined_range i j = return i -let undefined_atom i = return i -let undefined_nat () = return (0:ii) - -let skip () = return () - -val elf_entry : unit -> integer -let elf_entry () = 0 -declare ocaml target_rep function elf_entry = `Elf_loader.elf_entry` - -let print_bits msg bs = print_endline (msg ^ (string_of_bv bs)) -let prerr_bits msg bs = prerr_endline (msg ^ (string_of_bv bs)) - -val prerr_string : string -> unit -let prerr_string _ = () -declare ocaml target_rep function prerr_string = `Pervasives.prerr_string` - -val get_time_ns : unit -> integer -let get_time_ns () = 0 -declare ocaml target_rep function get_time_ns = `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))` - -val cycle_count : unit -> unit -let cycle_count _ = () - -let inline eq_bit = eq diff --git a/mips/mips_extras.v b/mips/mips_extras.v deleted file mode 100644 index 83f39079..00000000 --- a/mips/mips_extras.v +++ /dev/null @@ -1,179 +0,0 @@ -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import String. -Require Import List. -Import List.ListNotations. -(* -val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e -val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e -val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e -val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e -*) -Definition MEMr {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (mword b) e := read_mem Read_plain addr size. -Definition MEMr_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (mword b) e := read_mem Read_reserve addr size. - -(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) -Definition read_tag_bool {regval a e} (addr : mword a) : monad regval bool e := - read_tag addr >>= fun t => - maybe_fail "read_tag_bool" (bool_of_bitU t). - -(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) -Definition write_tag_bool {regval a e} (addr : mword a) t : monad regval unit e := - write_tag addr (bitU_of_bool t) >>= fun _ => returnm tt. - -Definition MEMr_tag {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e := - read_mem Read_plain addr size >>= fun v => - read_tag_bool addr >>= fun t => - returnm (t, v). - -Definition MEMr_tag_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e := - read_mem Read_plain addr size >>= fun v => - read_tag_bool addr >>= fun t => - returnm (t, v). - -(* -val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e -*) -Definition MEMea {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_plain addr size. -Definition MEMea_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size. - -Definition MEMea_tag {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_plain addr size. -Definition MEMea_tag_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size. - -(* -val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e -val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e -val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e -val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e -*) -Definition MEMval {regval a b e} (_ : mword a) (size : Z) (v : mword b) : monad regval unit e := write_mem_val v >>= fun _ => returnm tt. -Definition MEMval_conditional {regval a b e} (_ : mword a) (size : Z) (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => returnm (if b then true else false). -Definition MEMval_tag {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval unit e := write_mem_val v >>= fun _ => write_tag_bool addr t >>= fun _ => returnm tt. -Definition MEMval_tag_conditional {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => write_tag_bool addr t >>= fun _ => returnm (if b then true else false). - -(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) - -Definition MEM_sync {regval e} (_:unit) : monad regval unit e := barrier Barrier_MIPS_SYNC. - -(* Some wrappers copied from aarch64_extras *) -(* TODO: Harmonise into a common library *) -(* -Definition get_slice_int_bl len n lo := - (* TODO: Is this the intended behaviour? *) - let hi := lo + len - 1 in - let bs := bools_of_int (hi + 1) n in - subrange_list false bs hi lo - -val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) -*) -Definition write_ram {rv e} m size (_ : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv unit e := - MEMea addr size >> - MEMval addr size data. - -Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := MEMr addr size. -(* -Definition string_of_bits bs := string_of_bv (bits_of bs). -Definition string_of_int := show - -Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) -Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) -*) -Definition shift_bits_left {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := - maybe_fail "shift_bits_left" (unsigned n) >>= fun n => - returnm (shiftl v n). - -Definition shift_bits_right {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := - maybe_fail "shift_bits_right" (unsigned n) >>= fun n => - returnm (shiftr v n). - -Definition shift_bits_right_arith {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e := - maybe_fail "shift_bits_right" (unsigned n) >>= fun n => - returnm (arith_shiftr v n). - -(* Use constants for undefined values for now *) -Definition internal_pick {rv a e} (vs : list a) : monad rv a e := -match vs with -| (h::_) => returnm h -| _ => Fail "empty list in internal_pick" -end. -Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. -Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. -Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). -(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) -Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). -(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). -(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) -Definition undefined_bits {rv e} := @undefined_bitvector rv e. -Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. -(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) -Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). -Definition undefined_atom {rv e} i : monad rv Z e := returnm i. -Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). - -Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. - -(*val elf_entry : unit -> integer*) -Definition elf_entry (_:unit) : Z := 0. -(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) - -(*Definition print_bits msg bs := prerr_endline (msg ^ (string_of_bits bs)) - -val get_time_ns : unit -> integer*) -Definition get_time_ns (_:unit) : Z := 0. -(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) - -Definition eq_bit (x : bitU) (y : bitU) : bool := - match x, y with - | B0, B0 => true - | B1, B1 => true - | BU, BU => true - | _,_ => false - end. - -Require Import Zeuclid. -Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. -refine (existT _ (ZEuclid.modulo m n) _). -constructor. -destruct H. -assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } -rewrite <- H at 3. -lapply (ZEuclid.mod_always_pos m n); omega. -Qed. - -(* Override the more general version *) - -Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. -Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. - - -Definition print_endline (_:string) : unit := tt. -Definition prerr_endline (_:string) : unit := tt. -Definition prerr_string (_:string) : unit := tt. -Definition putchar {T} (_:T) : unit := tt. -Require DecimalString. -Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). - -Lemma __MIPS_read_lemma : forall width, 8 * width = 8 * (8 * width ÷ 8). -intros. -rewrite Z.mul_comm. -rewrite Z.quot_mul; auto with zarith. -Qed. -Hint Resolve __MIPS_read_lemma : sail. - -Lemma MEMr_wrapper_lemma : forall size : Z, 8 * size = 8 * (8 * (8 * size ÷ 8) ÷ 8). -intros. -rewrite Z.mul_comm. -rewrite Z.quot_mul; auto with zarith. -rewrite Z.mul_comm with (m := size). -rewrite Z.quot_mul; auto with zarith. -Qed. -Hint Resolve MEMr_wrapper_lemma : sail. - diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail deleted file mode 100644 index 63c380de..00000000 --- a/mips/mips_insts.sail +++ /dev/null @@ -1,1682 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* misp_insts.sail: mips instruction decode and execute clauses and AST node - declarations */ - -/**************************************************************************************/ -/* [D]ADD[I][U] various forms of ADD */ -/**************************************************************************************/ - -/* DADDIU Doubleword Add Immediate Unsigned -- - the simplest possible instruction, no undefined behaviour or exceptions - reg, reg, immediate */ - -union clause ast = DADDIU : (regno, regno, imm16) - -function clause decode (0b011001 @ rs : regno @ rt : regno @ imm : imm16) = - Some(DADDIU(rs, rt, imm)) - -function clause execute (DADDIU (rs, rt, imm)) = - { - wGPR(rt) = rGPR(rs) + sign_extend(imm) - } - -/* DADDU Doubleword Add Unsigned -- another very simple instruction, - reg, reg, reg */ - -union clause ast = DADDU : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101101) = - Some(DADDU(rs, rt, rd)) - -function clause execute (DADDU (rs, rt, rd)) = - { - wGPR(rd) = rGPR(rs) + rGPR(rt) - } - -/* DADDI Doubleword Add Immediate - reg, reg, imm with possible exception */ - -union clause ast = DADDI : (regno, regno, bits(16)) - -function clause decode (0b011000 @ rs : regno @ rt : regno @ imm : imm16) = - Some(DADDI(rs, rt, imm)) - -function clause execute (DADDI (rs, rt, imm)) = - { - let sum65 : bits(65) = sign_extend(rGPR(rs)) + sign_extend(imm) in - { - if (sum65[64] != sum65[63]) then - (SignalException(Ov)) - else - wGPR(rt) = sum65[63..0] - } - } - -/* DADD Doubleword Add - reg, reg, reg with possible exception */ - -union clause ast = DADD : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101100) = - Some(DADD(rs, rt, rd)) - -function clause execute (DADD (rs, rt, rd)) = - { - let sum65 : bits(65) = sign_extend(rGPR(rs)) + sign_extend(rGPR(rt)) in - { - if sum65[64] != sum65[63] then - (SignalException(Ov)) - else - wGPR(rd) = sum65[63..0] - } - } - -/* ADD 32-bit add -- reg, reg, reg with possible undefined behaviour or exception */ - -union clause ast = ADD : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100000) = - Some(ADD(rs, rt, rd)) - -function clause execute (ADD(rs, rt, rd)) = - { - opA : bits(64) = rGPR(rs); - opB : bits(64) = rGPR(rt); - if NotWordVal(opA) | NotWordVal(opB) then - wGPR(rd) = undefined /* XXX could exit instead */ - else - let sum33 : bits(33) = sign_extend(opA[31 .. 0]) + sign_extend(opB[31 .. 0])in - if sum33[32] != sum33[31] then - (SignalException(Ov)) - else - wGPR(rd) = sign_extend(sum33[31..0]) - } - -/* ADDI 32-bit add immediate -- reg, reg, imm with possible undefined behaviour or exception */ - -union clause ast = ADDI : (regno, regno, bits(16)) - -function clause decode (0b001000 @ rs : regno @ rt : regno @ imm : imm16) = - Some(ADDI(rs, rt, imm)) - -function clause execute (ADDI(rs, rt, imm)) = - { - opA = rGPR(rs); - if NotWordVal(opA) then - wGPR(rt) = undefined /* XXX could exit instead */ - else - let sum33 : bits(33) = sign_extend(opA[31 .. 0]) + sign_extend(imm) in - if sum33[32] != sum33[31] then - (SignalException(Ov)) - else - wGPR(rt) = sign_extend(sum33[31..0]) - } - -/* ADDU 32-bit add immediate -- reg, reg, reg with possible undefined behaviour */ - -union clause ast = ADDU : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100001) = - Some(ADDU(rs, rt, rd)) - -function clause execute (ADDU(rs, rt, rd)) = - { - opA = rGPR(rs); - opB = rGPR(rt); - if NotWordVal(opA) | NotWordVal(opB) then - wGPR(rd) = undefined - else - wGPR(rd) = sign_extend(opA[31..0] + opB[31..0]) - } - - -/* ADDIU 32-bit add immediate -- reg, reg, imm with possible undefined behaviour */ - -union clause ast = ADDIU : (regno, regno, bits(16)) - -function clause decode (0b001001 @ rs : regno @ rt : regno @ imm : imm16) = - Some(ADDIU(rs, rt, imm)) - -function clause execute (ADDIU(rs, rt, imm)) = - { - opA = rGPR(rs); - if NotWordVal(opA) then - wGPR(rt) = undefined /* XXX could exit instead */ - else - wGPR(rt) = sign_extend((opA[31 .. 0]) + sign_extend(imm)) - } - -/**************************************************************************************/ -/* [D]SUB[U] various forms of SUB */ -/**************************************************************************************/ - -/* DSUBU doubleword subtract 'unsigned' reg, reg, reg */ - -union clause ast = DSUBU : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101111) = - Some(DSUBU(rs, rt, rd)) - -function clause execute (DSUBU (rs, rt, rd)) = - { - wGPR(rd) = rGPR(rs) - rGPR(rt) - } - -/* DSUB reg, reg, reg with possible exception */ - -union clause ast = DSUB : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101110) = - Some(DSUB(rs, rt, rd)) - -function clause execute (DSUB (rs, rt, rd)) = - { - let temp65 : bits(65) = sign_extend(rGPR(rs)) - sign_extend(rGPR(rt)) in - { - if temp65[64] != temp65[63] then - (SignalException(Ov)) - else - wGPR(rd) = temp65[63..0] - } - } - -/* SUB 32-bit sub -- reg, reg, reg with possible undefined behaviour or exception */ - -union clause ast = SUB : (regno, regno, regno) - -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100010) = - Some(SUB(rs, rt, rd)) - -function clause execute (SUB(rs, rt, rd)) = - { - opA = rGPR(rs); - opB = rGPR(rt); - if NotWordVal(opA) | NotWordVal(opB) then - wGPR(rd) = undefined /* XXX could instead */ - else - let temp33 : bits(33) = sign_extend(opA[31..0]) - sign_extend(opB[31..0]) in - if temp33[32] != temp33[31] then - (SignalException(Ov)) - else - wGPR(rd) = sign_extend(temp33[31..0]) - } - -/* SUBU 32-bit 'unsigned' sub -- reg, reg, reg with possible undefined behaviour */ - -union clause ast = SUBU : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100011) = - Some(SUBU(rs, rt, rd)) - -function clause execute (SUBU(rs, rt, rd)) = - { - opA = rGPR(rs); - opB = rGPR(rt); - if NotWordVal(opA) | NotWordVal(opB) then - wGPR(rd) = undefined - else - wGPR(rd) = sign_extend(opA[31..0] - opB[31..0]) - } - -/**************************************************************************************/ -/* Logical bitwise operations */ -/**************************************************************************************/ - -/* AND reg, reg, reg */ - -union clause ast = AND : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100100) = - Some(AND(rs, rt, rd)) - -function clause execute (AND (rs, rt, rd)) = - { - wGPR(rd) = (rGPR(rs) & rGPR(rt)) - } - -/* ANDI reg, reg, imm */ - -union clause ast = ANDI : (regno, regno, bits(16)) -function clause decode (0b001100 @ rs : regno @ rt : regno @ imm : imm16) = - Some(ANDI(rs, rt, imm)) -function clause execute (ANDI (rs, rt, imm)) = - { - wGPR(rt) = (rGPR(rs) & zero_extend(imm)) - } - -/* OR reg, reg, reg */ - -union clause ast = OR : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100101) = - Some(OR(rs, rt, rd)) -function clause execute (OR (rs, rt, rd)) = - { - wGPR(rd) = (rGPR(rs) | rGPR(rt)) - } - -/* ORI reg, reg, imm */ - -union clause ast = ORI : (regno, regno, bits(16)) -function clause decode (0b001101 @ rs : regno @ rt : regno @ imm : imm16) = - Some(ORI(rs, rt, imm)) -function clause execute (ORI (rs, rt, imm)) = - { - wGPR(rt) = (rGPR(rs) | zero_extend(imm)) - } - -/* NOR reg, reg, reg */ - -union clause ast = NOR : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100111) = - Some(NOR(rs, rt, rd)) -function clause execute (NOR (rs, rt, rd)) = - { - wGPR(rd) = ~(rGPR(rs) | rGPR(rt)) - } - -/* XOR reg, reg, reg */ - -union clause ast = XOR : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b100110) = - Some(XOR(rs, rt, rd)) -function clause execute (XOR (rs, rt, rd)) = - { - wGPR(rd) = (rGPR(rs) ^ rGPR(rt)) - } - -/* XORI reg, reg, imm */ -union clause ast = XORI : (regno, regno, bits(16)) -function clause decode (0b001110 @ rs : regno @ rt : regno @ imm : imm16) = - Some(XORI(rs, rt, imm)) -function clause execute (XORI (rs, rt, imm)) = - { - wGPR(rt) = (rGPR(rs) ^ zero_extend(imm)) - } - -/* LUI reg, imm 32-bit load immediate into upper 16 bits */ -union clause ast = LUI : (regno, imm16) -function clause decode (0b001111 @ 0b00000 @ rt : regno @ imm : imm16) = - Some(LUI(rt, imm)) -function clause execute (LUI (rt, imm)) = - { - wGPR(rt) = sign_extend(imm @ 0x0000) - } - -/**************************************************************************************/ -/* 64-bit shift operations */ -/**************************************************************************************/ - -/* DSLL reg, reg, imm5 */ - -union clause ast = DSLL : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : bits(5) @ 0b111000) = - Some(DSLL(rt, rd, sa)) -function clause execute (DSLL (rt, rd, sa)) = - { - - wGPR(rd) = (rGPR(rt) << sa) - } - -/* DSLL32 reg, reg, imm5 */ - -union clause ast = DSLL32 : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : bits(5) @ 0b111100) = - Some(DSLL32(rt, rd, sa)) -function clause execute (DSLL32 (rt, rd, sa)) = - { - wGPR(rd) = (rGPR(rt) << (0b1 @ sa)) - } - -/* DSLLV reg, reg, reg */ - -union clause ast = DSLLV : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b010100) = - Some(DSLLV(rs, rt, rd)) -function clause execute (DSLLV (rs, rt, rd)) = - { - wGPR(rd) = (rGPR(rt) << ((rGPR(rs))[5 .. 0])) - } - -/* DSRA arithmetic shift duplicating sign bit - reg, reg, imm5 */ - -union clause ast = DSRA : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : bits(5) @ 0b111011) = - Some(DSRA(rt, rd, sa)) -function clause execute (DSRA (rt, rd, sa)) = - { - temp = rGPR(rt); - wGPR(rd) = temp >>_s sa - } - -/* DSRA32 reg, reg, imm5 */ - -union clause ast = DSRA32 : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : bits(5) @ 0b111111) = - Some(DSRA32(rt, rd, sa)) -function clause execute (DSRA32 (rt, rd, sa)) = - { - temp = rGPR(rt); - sa32 = 0b1 @ sa; /* sa+32 */ - wGPR(rd) = temp >>_s sa32 - } - -/* DSRAV reg, reg, reg */ -union clause ast = DSRAV : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b010111) = - Some(DSRAV(rs, rt, rd)) -function clause execute (DSRAV (rs, rt, rd)) = - { - temp = rGPR(rt); - sa = rGPR(rs)[5..0]; - wGPR(rd) = temp >>_s sa - } - -/* DSRL shift right logical - reg, reg, imm5 */ - -union clause ast = DSRL : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : bits(5) @ 0b111010) = - Some(DSRL(rt, rd, sa)) -function clause execute (DSRL (rt, rd, sa)) = - { - temp = rGPR(rt); - wGPR(rd) = temp >> sa; - } - -/* DSRL32 reg, reg, imm5 */ - -union clause ast = DSRL32 : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : bits(5) @ 0b111110) = - Some(DSRL32(rt, rd, sa)) -function clause execute (DSRL32 (rt, rd, sa)) = - { - temp = rGPR(rt); - sa32 = 0b1 @ sa; /* sa+32 */ - wGPR(rd) = temp >> sa32; - } - -/* DSRLV reg, reg, reg */ - -union clause ast = DSRLV : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b010110) = - Some(DSRLV(rs, rt, rd)) -function clause execute (DSRLV (rs, rt, rd)) = - { - temp = rGPR(rt); - sa = rGPR(rs)[5..0]; - wGPR(rd) = temp >> sa; - } - -/**************************************************************************************/ -/* 32-bit shift operations */ -/**************************************************************************************/ - -/* SLL 32-bit shift left */ - -union clause ast = SLL : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : regno @ 0b000000) = - Some(SLL(rt, rd, sa)) -function clause execute (SLL(rt, rd, sa)) = - { - rt32 = rGPR(rt)[31..0]; - wGPR(rd) = sign_extend(rt32 << sa); - } - -/* SLLV 32-bit shift left variable */ - -union clause ast = SLLV : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000100) = - Some(SLLV(rs, rt, rd)) -function clause execute (SLLV(rs, rt, rd)) = - { - sa = rGPR(rs)[4..0]; - rt32 = rGPR(rt)[31..0]; - wGPR(rd) = sign_extend(rt32 << sa) - } - -/* SRA 32-bit arithmetic shift right */ - -union clause ast = SRA : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : regno @ 0b000011) = - Some(SRA(rt, rd, sa)) -function clause execute (SRA(rt, rd, sa)) = - { - temp = rGPR(rt); - if (NotWordVal(temp)) then - wGPR(rd) = undefined - else { - rt32 = temp[31..0]; - wGPR(rd) = sign_extend(rt32 >>_s sa); - } - } - -/* SRAV 32-bit arithmetic shift right variable */ - -union clause ast = SRAV : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000111) = - Some(SRAV(rs, rt, rd)) -function clause execute (SRAV(rs, rt, rd)) = - { - temp = rGPR(rt); - sa = rGPR(rs)[4..0]; - if (NotWordVal(temp)) then - wGPR(rd) = undefined - else { - rt32 = temp[31..0]; - wGPR(rd) = sign_extend(rt32 >>_s sa) - } - } - -/* SRL 32-bit shift right */ - -union clause ast = SRL : (regno, regno, regno) -function clause decode (0b000000 @ 0b00000 @ rt : regno @ rd : regno @ sa : regno @ 0b000010) = - Some(SRL(rt, rd, sa)) -function clause execute (SRL(rt, rd, sa)) = - { - temp = rGPR(rt); - if (NotWordVal(temp)) then - wGPR(rd) = undefined - else { - rt32 = temp[31..0]; - wGPR(rd) = sign_extend(rt32 >> sa); - } - } - -/* SRLV 32-bit shift right variable */ - -union clause ast = SRLV : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000110) = - Some(SRLV(rs, rt, rd)) -function clause execute (SRLV(rs, rt, rd)) = - { - temp = rGPR(rt); - sa = (rGPR(rs))[4..0]; - if (NotWordVal(temp)) then - wGPR(rd) = undefined - else { - rt32 = temp[31..0]; - wGPR(rd) = sign_extend(rt32 >> sa); - } - } - -/**************************************************************************************/ -/* set less than / conditional move */ -/**************************************************************************************/ - -/* SLT set if less than (signed) */ - -union clause ast = SLT : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101010) = - Some(SLT(rs, rt, rd)) -function clause execute (SLT(rs, rt, rd)) = - { - wGPR(rd) = zero_extend(if (rGPR(rs) <_s rGPR(rt)) then 0b1 else 0b0) - } - -/* SLT set if less than immediate (signed) */ - -union clause ast = SLTI : (regno, regno, bits(16)) -function clause decode (0b001010 @ rs : regno @ rt : regno @ imm : imm16) = - Some(SLTI(rs, rt, imm)) -function clause execute (SLTI(rs, rt, imm)) = - { - let imm_val = signed(imm) in - let rs_val = signed(rGPR(rs)) in - wGPR(rt) = zero_extend(if (rs_val < imm_val) then 0b1 else 0b0) - } - -/* SLTU set if less than unsigned */ - -union clause ast = SLTU : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b101011) = - Some(SLTU(rs, rt, rd)) -function clause execute (SLTU(rs, rt, rd)) = - { - let rs_val = rGPR(rs) in - let rt_val = rGPR(rt) in - wGPR(rd) = zero_extend(if (rs_val <_u rt_val) then 0b1 else 0b0) - } - -/* SLTIU set if less than immediate unsigned */ - -union clause ast = SLTIU : (regno, regno, bits(16)) -function clause decode (0b001011 @ rs : regno @ rt : regno @ imm : imm16) = - Some(SLTIU(rs, rt, imm)) -function clause execute (SLTIU(rs, rt, imm)) = - { - let rs_val = rGPR(rs) in - let immext : bits(64) = sign_extend(imm) in /* NB defined to sign extend here even though comparison is unsigned! */ - wGPR(rt) = zero_extend(if (rs_val <_u immext) then 0b1 else 0b0) - } - -/* MOVN move if non-zero */ - -union clause ast = MOVN : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b001011) = - Some(MOVN(rs, rt, rd)) -function clause execute (MOVN(rs, rt, rd)) = - { - if (rGPR(rt) != 0x0000000000000000) then - wGPR(rd) = rGPR(rs) - } - -/* MOVZ move if zero */ - -union clause ast = MOVZ : (regno, regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b001010) = - Some(MOVZ(rs, rt, rd)) -function clause execute (MOVZ(rs, rt, rd)) = - { - if (rGPR(rt) == 0x0000000000000000) then - wGPR(rd) = rGPR(rs) - } - -/******************************************************************************/ -/* MUL/DIV instructions */ -/******************************************************************************/ - -/* MFHI move from HI register */ -union clause ast = MFHI : regno -function clause decode (0b000000 @ 0b0000000000 @ rd : regno @ 0b00000 @ 0b010000) = - Some(MFHI(rd)) -function clause execute (MFHI(rd)) = - { - wGPR(rd) = HI - } - -/* MFLO move from LO register */ -union clause ast = MFLO : regno -function clause decode (0b000000 @ 0b0000000000 @ rd : regno @ 0b00000 @ 0b010010) = - Some(MFLO(rd)) -function clause execute (MFLO(rd)) = - { - wGPR(rd) = LO - } - -/* MTHI move to HI register */ -union clause ast = MTHI : regno -function clause decode (0b000000 @ rs : regno @ 0b000000000000000 @ 0b010001) = - Some(MTHI(rs)) -function clause execute (MTHI(rs)) = - { - HI = rGPR(rs) - } - -/* MTLO move to LO register */ -union clause ast = MTLO : regno -function clause decode (0b000000 @ rs : regno @ 0b000000000000000 @ 0b010011) = - Some(MTLO(rs)) -function clause execute (MTLO(rs)) = - { - LO = rGPR(rs) - } - -/* MUL 32-bit multiply into GPR */ -union clause ast = MUL : (regno, regno, regno) -function clause decode (0b011100 @ rs : regno @ rt : regno @ rd : regno @ 0b00000 @ 0b000010) = - Some(MUL(rs, rt, rd)) -function clause execute (MUL(rs, rt, rd)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - result : bits(64) = sign_extend((rsVal[31..0]) *_s (rtVal[31..0])); - wGPR(rd) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - sign_extend(result[31..0]); - /* HI and LO are technically undefined after MUL, but this causes problems with tests and - (potentially) context switch so just leave them alone - HI = undefined; - LO = undefined; - */ - } - -/* MULT 32-bit multiply into HI/LO */ -union clause ast = MULT : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011000) = - Some(MULT(rs, rt)) -function clause execute (MULT(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - result : bits(64) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - (rsVal[31..0]) *_s (rtVal[31..0]); - HI = sign_extend(result[63..32]); - LO = sign_extend(result[31..0]); - } - -/* MULTU 32-bit unsignedm rultiply into HI/LO */ -union clause ast = MULTU : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011001) = - Some(MULTU(rs, rt)) -function clause execute (MULTU(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - result : bits(64) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - (rsVal[31..0]) *_u (rtVal[31..0]); - HI = sign_extend(result[63..32]); - LO = sign_extend(result[31..0]); - } - -/* DMULT 64-bit multiply into HI/LO */ -union clause ast = DMULT : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011100) = - Some(DMULT(rs, rt)) -function clause execute (DMULT(rs, rt)) = - { - result = rGPR(rs) *_s rGPR(rt); - HI = (result[127..64]); - LO = (result[63..0]); - } - -/* DMULTU 64-bit unsigned multiply into HI/LO */ -union clause ast = DMULTU : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011101) = - Some(DMULTU(rs, rt)) -function clause execute (DMULTU(rs, rt)) = - { - result = rGPR(rs) *_u rGPR(rt); - HI = (result[127..64]); - LO = (result[63..0]); - } - -/* MADD 32-bit signed multiply and add into HI/LO */ -union clause ast = MADD : (regno, regno) -function clause decode (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000000) = - Some(MADD(rs, rt)) -function clause execute (MADD(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - mul_result : bits(64) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - rsVal[31..0] *_s rtVal[31..0]; - result = mul_result + (HI[31..0] @ LO[31..0]); - HI = sign_extend(result[63..32]); - LO = sign_extend(result[31..0]); - } - -/* MADDU 32-bit unsigned multiply and add into HI/LO */ -union clause ast = MADDU : (regno, regno) -function clause decode (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000001) = - Some(MADDU(rs, rt)) -function clause execute (MADDU(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - mul_result : bits(64) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - rsVal[31..0] *_u rtVal[31..0]; - result = mul_result + (HI[31..0] @ LO[31..0]); - HI = sign_extend(result[63..32]); - LO = sign_extend(result[31..0]); - } - -/* MSUB 32-bit signed multiply and sub from HI/LO */ -union clause ast = MSUB : (regno, regno) -function clause decode (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000100) = - Some(MSUB(rs, rt)) -function clause execute (MSUB(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - mul_result : bits(64) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - rsVal[31..0] *_s rtVal[31..0]; - result = (HI[31..0] @ LO[31..0]) - mul_result; - HI = sign_extend(result[63..32]); - LO = sign_extend(result[31..0]); - } - -/* MSUBU 32-bit unsigned multiply and sub from HI/LO */ -union clause ast = MSUBU : (regno, regno) -function clause decode (0b011100 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b000101) = - Some(MSUBU(rs, rt)) -function clause execute (MSUBU(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - mul_result : bits(64) = if (NotWordVal(rsVal) | NotWordVal(rtVal)) then - undefined - else - rsVal[31..0] *_u rtVal[31..0]; - result = (HI[31..0] @ LO[31..0]) - mul_result; - HI = sign_extend(result[63..32]); - LO = sign_extend(result[31..0]); - } - -/* DIV 32-bit divide into HI/LO */ -union clause ast = DIV : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011010) = - Some(DIV(rs, rt)) -function clause execute (DIV(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - let (q, r) = - if (NotWordVal(rsVal) | NotWordVal(rtVal) | (rtVal == 0x0000000000000000)) then - (undefined : bits(32), undefined : bits(32)) - else - let si = signed((rsVal[31..0])) in - let ti = signed((rtVal[31..0])) in - let qi = quot_round_zero(si, ti) in - let ri = si - (ti*qi) in - (to_bits(32, qi), to_bits(32, ri)) - in - { - HI = sign_extend(r); - LO = sign_extend(q); - } - } - -/* DIVU 32-bit unsigned divide into HI/LO */ -union clause ast = DIVU : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011011) = - Some(DIVU(rs, rt)) -function clause execute (DIVU(rs, rt)) = - { - rsVal = rGPR(rs); - rtVal = rGPR(rt); - let (q, r) = - if (NotWordVal(rsVal) | NotWordVal(rtVal) | rtVal == 0x0000000000000000) then - (undefined : bits(32), undefined : bits(32)) - else - let si = unsigned(rsVal[31..0]) in - let ti = unsigned(rtVal[31..0]) in - let qi = quot_round_zero(si, ti) in - let ri = rem_round_zero(si, ti) in - (to_bits(32, qi), to_bits(32, ri)) - in - { - HI = sign_extend(r); - LO = sign_extend(q); - } - } - -/* DDIV 64-bit divide into HI/LO */ -union clause ast = DDIV : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011110) = - Some(DDIV(rs, rt)) -function clause execute (DDIV(rs, rt)) = - { - rsVal = signed(rGPR(rs)); - rtVal = signed(rGPR(rt)); - let (q , r) = - if (rtVal == 0) - then (undefined : bits(64), undefined : bits(64)) - else - let qi = quot_round_zero(rsVal, rtVal) in - let ri = (rsVal - (qi * rtVal)) in - (to_bits(64, qi), to_bits(64, ri)) in - { - LO = q; - HI = r; - } - } - -/* DDIV 64-bit divide into HI/LO */ -union clause ast = DDIVU : (regno, regno) -function clause decode (0b000000 @ rs : regno @ rt : regno @ 0b00000 @ 0b00000 @ 0b011111) = - Some(DDIVU(rs, rt)) -function clause execute (DDIVU(rs, rt)) = - { - rsVal = unsigned(rGPR(rs)); - rtVal = unsigned(rGPR(rt)); - let (q, r) = - if (rtVal == 0) - then (undefined : bits(64), undefined : bits(64)) - else - let qi = quot_round_zero(rsVal, rtVal) in - let ri = rem_round_zero(rsVal, rtVal) in - (to_bits(64, qi), to_bits(64, ri)) in - { - LO = q; - HI = r; - } - } - -/**************************************************************************************/ -/* Jump instructions -- unconditional branches */ -/**************************************************************************************/ - -/* J - jump, the simplest control flow instruction, with branch delay slot */ -union clause ast = J : bits(26) -function clause decode (0b000010 @ offset : bits(26)) = - Some(J(offset)) -function clause execute (J(offset)) = - { - execute_branch((PC + 4)[63..28] @ offset @ 0b00); - } - -/* JAL - jump and link */ -union clause ast = JAL : bits(26) -function clause decode (0b000011 @ offset : bits(26)) = - Some(JAL(offset)) -function clause execute (JAL(offset)) = - { - execute_branch((PC + 4)[63..28] @ offset @ 0b00); - wGPR(0b11111) = PC + 8; - } - -/* JR -- jump via register */ -union clause ast = JR : regno -function clause decode (0b000000 @ rs : regno @ 0b00000 @ 0b00000 @ hint : regno @ 0b001000) = - Some(JR(rs)) /* hint is ignored */ -function clause execute (JR(rs)) = - { - execute_branch(rGPR(rs)); - } - -/* JALR -- jump via register with link */ -union clause ast = JALR : (regno, regno) -function clause decode (0b000000 @ rs : regno @ 0b00000 @ rd : regno @ hint : regno @ 0b001001) = - Some(JALR(rs, rd)) /* hint is ignored */ -function clause execute (JALR(rs, rd)) = - { - execute_branch(rGPR(rs)); - wGPR(rd) = PC + 8; - } - -/**************************************************************************************/ -/* B[N]EQ[L] - branch on (not) equal (likely) */ -/* Conditional branch instructions with two register operands */ -/**************************************************************************************/ - -union clause ast = BEQ : (regno, regno, imm16, bool, bool) -function clause decode (0b000100 @ rs : regno @ rt : regno @ imm : imm16) = - Some(BEQ(rs, rt, imm, false, false)) /* BEQ */ -function clause decode (0b010100 @ rs : regno @ rt : regno @ imm : imm16) = - Some(BEQ(rs, rt, imm, false, true)) /* BEQL */ -function clause decode (0b000101 @ rs : regno @ rt : regno @ imm : imm16) = - Some(BEQ(rs, rt, imm, true , false)) /* BNE */ -function clause decode (0b010101 @ rs : regno @ rt : regno @ imm : imm16) = - Some(BEQ(rs, rt, imm, true , true)) /* BNEL */ -function clause execute (BEQ(rs, rd, imm, ne, likely)) = - { - if ((rGPR(rs) == rGPR(rd)) ^ ne) then - { - let offset : bits(64) = (sign_extend(imm @ 0b00) + 4) in - execute_branch(PC + offset); - } - else - { - if (likely) then - nextPC = PC + 8; /* skip branch delay */ - } - } - -/* - - Branches comparing with zero (single register operand, possible link in r31) -*/ - -/**************************************************************************************/ -/* BGEZ[AL][L] - branch on comparison with zero (possibly link, likely) */ -/* Conditional branch instructions with single register operand */ -/**************************************************************************************/ - -union clause ast = BCMPZ : (regno, imm16, Comparison, bool, bool) -function clause decode (0b000001 @ rs : regno @ 0b00000 @ imm : imm16) = - Some(BCMPZ(rs, imm, LT, false, false)) /* BLTZ */ -function clause decode (0b000001 @ rs : regno @ 0b10000 @ imm : imm16) = - Some(BCMPZ(rs, imm, LT, true, false)) /* BLTZAL */ -function clause decode (0b000001 @ rs : regno @ 0b00010 @ imm : imm16) = - Some(BCMPZ(rs, imm, LT, false, true)) /* BLTZL */ -function clause decode (0b000001 @ rs : regno @ 0b10010 @ imm : imm16) = - Some(BCMPZ(rs, imm, LT, true, true)) /* BLTZALL */ - -function clause decode (0b000001 @ rs : regno @ 0b00001 @ imm : imm16) = - Some(BCMPZ(rs, imm, GE, false, false)) /* BGEZ */ -function clause decode (0b000001 @ rs : regno @ 0b10001 @ imm : imm16) = - Some(BCMPZ(rs, imm, GE, true, false)) /* BGEZAL */ -function clause decode (0b000001 @ rs : regno @ 0b00011 @ imm : imm16) = - Some(BCMPZ(rs, imm, GE, false, true)) /* BGEZL */ -function clause decode (0b000001 @ rs : regno @ 0b10011 @ imm : imm16) = - Some(BCMPZ(rs, imm, GE, true, true)) /* BGEZALL */ - -function clause decode (0b000111 @ rs : regno @ 0b00000 @ imm : imm16) = - Some(BCMPZ(rs, imm, GT, false, false)) /* BGTZ */ -function clause decode (0b010111 @ rs : regno @ 0b00000 @ imm : imm16) = - Some(BCMPZ(rs, imm, GT, false, true)) /* BGTZL */ - -function clause decode (0b000110 @ rs : regno @ 0b00000 @ imm : imm16) = - Some(BCMPZ(rs, imm, LE, false, false)) /* BLEZ */ -function clause decode (0b010110 @ rs : regno @ 0b00000 @ imm : imm16) = - Some(BCMPZ(rs, imm, LE, false, true)) /* BLEZL */ - -function clause execute (BCMPZ(rs, imm, cmp, link, likely)) = - { - linkVal = PC + 8; - regVal = rGPR(rs); - condition = compare(cmp, regVal, zero_extend(0b0)); - if (condition) then - { - let offset : bits(64) = (sign_extend(imm @ 0b00) + 4) in - execute_branch(PC + offset); - } - else if (likely) then - { - nextPC = PC + 8 /* skip branch delay */ - }; - if (link) then - wGPR(0b11111) = linkVal - } - -/**************************************************************************************/ -/* SYSCALL/BREAK/WAIT/Trap */ -/**************************************************************************************/ - -/* $include mips_rmem.sail */ - -union clause ast = SYSCALL : unit -function clause decode (0b000000 @ code : bits(20) @ 0b001100) = - Some(SYSCALL()) /* code is ignored */ -function clause execute (SYSCALL()) = - { - (SignalException(Sys)) - } - -/* BREAK is identical to SYSCALL exception for the exception raised */ -union clause ast = BREAK : unit -function clause decode (0b000000 @ code : bits(20) @ 0b001101) = - Some(BREAK()) /* code is ignored */ -function clause execute (BREAK()) = - { - (SignalException(Bp)) - } - -/* Accept WAIT as a NOP */ -union clause ast = WAIT : unit -function clause decode (0b010000 @ 0x80000 @ 0b100000) = - Some(WAIT()) /* we only accept code == 0 */ -function clause execute (WAIT()) = { - nextPC = PC; -} - -/* Trap instructions with two register operands */ -union clause ast = TRAPREG : (regno, regno, Comparison) -function clause decode (0b000000 @ rs : regno @ rt : regno @ code : bits(10) @ 0b110000) = - Some(TRAPREG(rs, rt, GE)) /* TGE */ -function clause decode (0b000000 @ rs : regno @ rt : regno @ code : bits(10) @ 0b110001) = - Some(TRAPREG(rs, rt, GEU)) /* TGEU */ -function clause decode (0b000000 @ rs : regno @ rt : regno @ code : bits(10) @ 0b110010) = - Some(TRAPREG(rs, rt, LT)) /* TLT */ -function clause decode (0b000000 @ rs : regno @ rt : regno @ code : bits(10) @ 0b110011) = - Some(TRAPREG(rs, rt, LTU)) /* TLTU */ -function clause decode (0b000000 @ rs : regno @ rt : regno @ code : bits(10) @ 0b110100) = - Some(TRAPREG(rs, rt, EQ)) /* TEQ */ -function clause decode (0b000000 @ rs : regno @ rt : regno @ code : bits(10) @ 0b110110) = - Some(TRAPREG(rs, rt, NE)) /* TNE */ -function clause execute (TRAPREG(rs, rt, cmp)) = - { - rs_val = rGPR(rs); - rt_val = rGPR(rt); - condition = compare(cmp, rs_val, rt_val); - if (condition) then - (SignalException(Tr)) - } - - -/* Trap instructions with one register and one immediate operand */ -union clause ast = TRAPIMM : (regno, imm16, Comparison) -function clause decode (0b000001 @ rs : regno @ 0b01100 @ imm : imm16) = - Some(TRAPIMM(rs, imm, EQ)) /* TEQI */ -function clause decode (0b000001 @ rs : regno @ 0b01110 @ imm : imm16) = - Some(TRAPIMM(rs, imm, NE)) /* TNEI */ -function clause decode (0b000001 @ rs : regno @ 0b01000 @ imm : imm16) = - Some(TRAPIMM(rs, imm, GE)) /* TGEI */ -function clause decode (0b000001 @ rs : regno @ 0b01001 @ imm : imm16) = - Some(TRAPIMM(rs, imm, GEU)) /* TGEIU */ -function clause decode (0b000001 @ rs : regno @ 0b01010 @ imm : imm16) = - Some(TRAPIMM(rs, imm, LT)) /* TLTI */ -function clause decode (0b000001 @ rs : regno @ 0b01011 @ imm : imm16) = - Some(TRAPIMM(rs, imm, LTU)) /* TLTIU */ -function clause execute (TRAPIMM(rs, imm, cmp)) = - { - rs_val = rGPR(rs); - imm_val : bits(64) = sign_extend(imm); - condition = compare(cmp, rs_val, imm_val); - if (condition) then - (SignalException(Tr)) - } - -/**************************************************************************************/ -/* Load instructions -- various width/signs */ -/**************************************************************************************/ - -union clause ast = Load : (WordType, bool, bool, regno, regno, imm16) -function clause decode (0b100000 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(B, true, false, base, rt, offset)) /* LB */ -function clause decode (0b100100 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(B, false, false, base, rt, offset)) /* LBU */ -function clause decode (0b100001 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(H, true, false, base, rt, offset)) /* LH */ -function clause decode (0b100101 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(H, false, false, base, rt, offset)) /* LHU */ -function clause decode (0b100011 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(W, true, false, base, rt, offset)) /* LW */ -function clause decode (0b100111 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(W, false, false, base, rt, offset)) /* LWU */ -function clause decode (0b110111 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(D, false, false, base, rt, offset)) /* LD */ -function clause decode (0b110000 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(W, true, true, base, rt, offset)) /* LL */ -function clause decode (0b110100 @ base : regno @ rt : regno @ offset : imm16) = - Some(Load(D, false, true, base, rt, offset)) /* LLD */ - -val extendLoad : forall 'sz, 'sz <= 64 . (bits('sz), bool) -> bits(64) effect pure -function extendLoad(memResult, sign) = { - if (sign) then - sign_extend(memResult) - else - zero_extend(memResult) -} - -function clause execute (Load(width, sign, linked, base, rt, offset)) = - { - vAddr : bits(64) = addrWrapper(sign_extend(offset) + rGPR(base), LoadData, width); - if ~ (isAddressAligned(vAddr, width)) then - (SignalExceptionBadAddr(AdEL, vAddr)) /* unaligned access */ - else - let pAddr = (TLBTranslate(vAddr, LoadData)) in - { - memResult : bits(64) = if (linked) then - { - CP0LLBit = 0b1; - CP0LLAddr = pAddr; - match width { - W => extendLoad(MEMr_reserve_wrapper(pAddr, 4), sign), - D => extendLoad(MEMr_reserve_wrapper(pAddr, 8), sign), - _ => throw(Error_internal_error()) /* there is no llbc or llhc */ - } - } - else - { - match width { - B => extendLoad(MEMr_wrapper(pAddr, 1), sign), - H => extendLoad(MEMr_wrapper(pAddr, 2), sign), - W => extendLoad(MEMr_wrapper(pAddr, 4), sign), - D => extendLoad(MEMr_wrapper(pAddr, 8), sign) - } - }; - wGPR(rt) = memResult - } - } - -/**************************************************************************************/ -/* Store instructions -- various widths */ -/**************************************************************************************/ - -union clause ast = Store : (WordType, bool, regno, regno, imm16) -function clause decode (0b101000 @ base : regno @ rt : regno @ offset : imm16) = - Some(Store(B, false, base, rt, offset)) /* SB */ -function clause decode (0b101001 @ base : regno @ rt : regno @ offset : imm16) = - Some(Store(H, false, base, rt, offset)) /* SH */ -function clause decode (0b101011 @ base : regno @ rt : regno @ offset : imm16) = - Some(Store(W, false, base, rt, offset)) /* SW */ -function clause decode (0b111111 @ base : regno @ rt : regno @ offset : imm16) = - Some(Store(D, false, base, rt, offset)) /* SD */ -function clause decode (0b111000 @ base : regno @ rt : regno @ offset : imm16) = - Some(Store(W, true, base, rt, offset)) /* SC */ -function clause decode (0b111100 @ base : regno @ rt : regno @ offset : imm16) = - Some(Store(D, true, base, rt, offset)) /* SCD */ -function clause execute (Store(width, conditional, base, rt, offset)) = - { - vAddr : bits(64) = addrWrapper(sign_extend(offset) + rGPR(base), StoreData, width); - rt_val = rGPR(rt); - if ~ (isAddressAligned(vAddr, width)) then - (SignalExceptionBadAddr(AdES, vAddr)) /* unaligned access */ - else - let pAddr = (TLBTranslate(vAddr, StoreData)) in - { - if (conditional) then - { - success : bool = if (CP0LLBit[0]) then match width - { - W => MEMw_conditional_wrapper(pAddr, 4, rt_val[31..0]), - D => MEMw_conditional_wrapper(pAddr, 8, rt_val), - _ => throw(Error_internal_error()) /* there is no sbc or shc */ - } else false; - wGPR(rt) = zero_extend(success) - } - else - match width - { - B => MEMw_wrapper(pAddr, 1) = rt_val[7..0], - H => MEMw_wrapper(pAddr, 2) = rt_val[15..0], - W => MEMw_wrapper(pAddr, 4) = rt_val[31..0], - D => MEMw_wrapper(pAddr, 8) = rt_val - } - } - } - -/* LWL - Load word left (big-endian only) */ - -union clause ast = LWL : (regno, regno, bits(16)) -function clause decode(0b100010 @ base : regno @ rt : regno @ offset : imm16) = - Some(LWL(base, rt, offset)) -function clause execute(LWL(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, WL); - let pAddr = (TLBTranslate(vAddr, LoadData)) in - { - mem_val = MEMr_wrapper (pAddr[63..2] @ 0b00, 4); /* read word of interest */ - reg_val = rGPR(rt); - result : bits(32) = match vAddr[1..0] - { - 0b00 => mem_val, - 0b01 => mem_val[23..0] @ reg_val[07..0], - 0b10 => mem_val[15..0] @ reg_val[15..0], - 0b11 => mem_val[07..0] @ reg_val[23..0] - }; - wGPR(rt) = sign_extend(result); - } - } -union clause ast = LWR : (regno, regno, bits(16)) -function clause decode(0b100110 @ base : regno @ rt : regno @ offset : imm16) = - Some(LWR(base, rt, offset)) -function clause execute(LWR(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, WR); - let pAddr = (TLBTranslate(vAddr, LoadData)) in - { - mem_val = MEMr_wrapper(pAddr[63..2] @ 0b00, 4); /* read word of interest */ - reg_val = rGPR(rt); - result : bits(32) = match vAddr[1..0] - { - 0b00 => reg_val[31..8] @ mem_val[31..24], - 0b01 => reg_val[31..16] @ mem_val[31..16], - 0b10 => reg_val[31..24] @ mem_val[31..8], - 0b11 => mem_val - }; - wGPR(rt) = sign_extend(result) - } - } - -/* SWL - Store word left */ -union clause ast = SWL : (regno, regno, bits(16)) -function clause decode(0b101010 @ base : regno @ rt : regno @ offset : imm16) = - Some(SWL(base, rt, offset)) -function clause execute(SWL(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, WL); - let pAddr = TLBTranslate(vAddr, StoreData) in - { - reg_val = rGPR(rt); - match vAddr[1..0] - { - 0b00 => (MEMw_wrapper(pAddr, 4) = reg_val[31..0]), - 0b01 => (MEMw_wrapper(pAddr, 3) = reg_val[31..8]), - 0b10 => (MEMw_wrapper(pAddr, 2) = reg_val[31..16]), - 0b11 => (MEMw_wrapper(pAddr, 1) = reg_val[31..24]) - } - } - } - -union clause ast = SWR : (regno, regno, bits(16)) -function clause decode(0b101110 @ base : regno @ rt : regno @ offset : imm16) = - Some(SWR(base, rt, offset)) -function clause execute(SWR(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, WR); - let pAddr = TLBTranslate(vAddr, StoreData) in - { - wordAddr = pAddr[63..2] @ 0b00; - reg_val = rGPR(rt); - match vAddr[1..0] - { - 0b00 => (MEMw_wrapper(wordAddr, 1) = reg_val[7..0]), - 0b01 => (MEMw_wrapper(wordAddr, 2) = reg_val[15..0]), - 0b10 => (MEMw_wrapper(wordAddr, 3) = reg_val[23..0]), - 0b11 => (MEMw_wrapper(wordAddr, 4) = reg_val[31..0]) - } - } - } - -/* Load double-word left */ -union clause ast = LDL : (regno, regno, bits(16)) -function clause decode(0b011010 @ base : regno @ rt : regno @ offset : imm16) = - Some(LDL(base, rt, offset)) -function clause execute(LDL(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, DL); - let pAddr = TLBTranslate(vAddr, LoadData) in - { - mem_val = MEMr_wrapper(pAddr[63..3] @ 0b000, 8); /* read double of interest */ - reg_val = rGPR(rt); - wGPR(rt) = match vAddr[2..0] - { - 0b000 => mem_val, - 0b001 => mem_val[55..0] @ reg_val[7..0], - 0b010 => mem_val[47..0] @ reg_val[15..0], - 0b011 => mem_val[39..0] @ reg_val[23..0], - 0b100 => mem_val[31..0] @ reg_val[31..0], - 0b101 => mem_val[23..0] @ reg_val[39..0], - 0b110 => mem_val[15..0] @ reg_val[47..0], - 0b111 => mem_val[07..0] @ reg_val[55..0] - }; - } - } - -/* Load double-word right */ -union clause ast = LDR : (regno, regno, bits(16)) -function clause decode(0b011011 @ base : regno @ rt : regno @ offset : imm16) = - Some(LDR(base, rt, offset)) -function clause execute(LDR(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), LoadData, DR); - let pAddr = TLBTranslate(vAddr, LoadData) in - { - mem_val = MEMr_wrapper(pAddr[63..3] @ 0b000, 8); /* read double of interest */ - reg_val = rGPR(rt); - wGPR(rt) = match vAddr[2..0] - { - 0b000 => reg_val[63..08] @ mem_val[63..56], - 0b001 => reg_val[63..16] @ mem_val[63..48], - 0b010 => reg_val[63..24] @ mem_val[63..40], - 0b011 => reg_val[63..32] @ mem_val[63..32], - 0b100 => reg_val[63..40] @ mem_val[63..24], - 0b101 => reg_val[63..48] @ mem_val[63..16], - 0b110 => reg_val[63..56] @ mem_val[63..08], - 0b111 => mem_val - }; - } - } - -/* SDL - Store double-word left */ -union clause ast = SDL : (regno, regno, bits(16)) -function clause decode(0b101100 @ base : regno @ rt : regno @ offset : imm16) = - Some(SDL(base, rt, offset)) -function clause execute(SDL(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, DL); - let pAddr = TLBTranslate(vAddr, StoreData) in - { - reg_val = rGPR(rt); - match vAddr[2..0] - { - 0b000 => (MEMw_wrapper(pAddr, 8) = reg_val[63..00]), - 0b001 => (MEMw_wrapper(pAddr, 7) = reg_val[63..08]), - 0b010 => (MEMw_wrapper(pAddr, 6) = reg_val[63..16]), - 0b011 => (MEMw_wrapper(pAddr, 5) = reg_val[63..24]), - 0b100 => (MEMw_wrapper(pAddr, 4) = reg_val[63..32]), - 0b101 => (MEMw_wrapper(pAddr, 3) = reg_val[63..40]), - 0b110 => (MEMw_wrapper(pAddr, 2) = reg_val[63..48]), - 0b111 => (MEMw_wrapper(pAddr, 1) = reg_val[63..56]) - } - } - } - - -/* SDR - Store double-word right */ -union clause ast = SDR : (regno, regno, bits(16)) -function clause decode(0b101101 @ base : regno @ rt : regno @ offset : imm16) = - Some(SDR(base, rt, offset)) -function clause execute(SDR(base, rt, offset)) = - { - vAddr = addrWrapperUnaligned(sign_extend(offset) + rGPR(base), StoreData, DR); - let pAddr = TLBTranslate(vAddr, StoreData) in - { - reg_val = rGPR(rt); - wordAddr = pAddr[63..3] @ 0b000; - match vAddr[2..0] - { - 0b000 => (MEMw_wrapper(wordAddr, 1) = reg_val[07..0]), - 0b001 => (MEMw_wrapper(wordAddr, 2) = reg_val[15..0]), - 0b010 => (MEMw_wrapper(wordAddr, 3) = reg_val[23..0]), - 0b011 => (MEMw_wrapper(wordAddr, 4) = reg_val[31..0]), - 0b100 => (MEMw_wrapper(wordAddr, 5) = reg_val[39..0]), - 0b101 => (MEMw_wrapper(wordAddr, 6) = reg_val[47..0]), - 0b110 => (MEMw_wrapper(wordAddr, 7) = reg_val[55..0]), - 0b111 => (MEMw_wrapper(wordAddr, 8) = reg_val[63..0]) - } - } - } - -/* CACHE - manipulate (non-existent) caches */ - -union clause ast = CACHE : (regno, regno, bits(16)) -function clause decode (0b101111 @ base : regno @ op : regno @ imm : imm16) = - Some(CACHE(base, op, imm)) -function clause execute (CACHE(base, op, imm)) = - checkCP0Access () /* pretty much a NOP because no caches */ - -/* PREF - prefetching into (non-existent) caches - -union clause ast = PREF : (regno, regno, bits(16)) -function clause decode (0b110011 @ base : regno @ op : regno @ imm : imm16) = - Some(PREF(base, op, imm)) -function clause execute (PREF(base, op, imm)) = - () /* XXX NOP */ - -*/ - -/* SYNC - Memory barrier */ -union clause ast = SYNC : unit -function clause decode (0b000000 @ 0b00000 @ 0b00000 @ 0b00000 @ stype : regno @ 0b001111) = - Some(SYNC()) /* stype is currently ignored */ -function clause execute(SYNC()) = - MEM_sync() - -union clause ast = MFC0 : (regno, regno, bits(3), bool) -function clause decode (0b010000 @ 0b00000 @ rt : regno @ rd : regno @ 0b00000000 @ sel : bits(3)) = - Some(MFC0(rt, rd, sel, false)) /* MFC0 */ -function clause decode (0b010000 @ 0b00001 @ rt : regno @ rd : regno @ 0b00000000 @ sel : bits(3)) = - Some(MFC0(rt, rd, sel, true)) /* DMFC0 */ -function clause execute (MFC0(rt, rd, sel, double)) = { - checkCP0Access(); - let result : bits(64) = match (rd, sel) - { - (0b00000,0b000) => let idx : bits(31) = zero_extend(TLBIndex) in - (0x00000000 @ TLBProbe @ idx), /* 0, TLB Index */ - (0b00001,0b000) => zero_extend(TLBRandom), /* 1, TLB Random */ - (0b00010,0b000) => TLBEntryLo0.bits(), /* 2, TLB EntryLo0 */ - (0b00011,0b000) => TLBEntryLo1.bits(), /* 3, TLB EntryLo1 */ - (0b00100,0b000) => TLBContext.bits(), /* 4, TLB Context */ - (0b00100,0b010) => CP0UserLocal, - (0b00101,0b000) => zero_extend(TLBPageMask @ 0x000), /* 5, TLB PageMask */ - (0b00110,0b000) => zero_extend(TLBWired), /* 6, TLB Wired */ - (0b00111,0b000) => zero_extend(CP0HWREna), /* 7, HWREna */ - (0b01000,0b000) => CP0BadVAddr, /* 8, BadVAddr reg */ - (0b01000,0b001) => zero_extend(0b0), /* 8, BadInstr reg XXX TODO */ - (0b01001,0b000) => zero_extend(CP0Count), /* 9, Count reg */ - (0b01010,0b000) => TLBEntryHi.bits(),/* 10, TLB EntryHi */ - (0b01011,0b000) => zero_extend(CP0Compare), /* 11, Compare reg */ - (0b01100,0b000) => zero_extend(CP0Status.bits()), /* 12, Status reg */ - (0b01101,0b000) => zero_extend(CP0Cause.bits()), /* 13, Cause reg */ - (0b01110,0b000) => CP0EPC, /* 14, EPC */ - (0b01111,0b000) => zero_extend(0x00000400), /* 15, sel 0: PrID processor ID */ - (0b01111,0b110) => zero_extend(0b0), /* 15, sel 6: CHERI core ID */ - (0b01111,0b111) => zero_extend(0b0), /* 15, sel 7: CHERI thread ID */ - (0b10000,0b000) => zero_extend(0b1 /* M */ /* 16, sel 0: Config0 */ - @ 0b000000000000000 /* Impl */ - @ 0b1 /* BE */ - @ 0b10 /* AT */ - @ 0b000 /* AR */ - @ 0b001 /* MT standard TLB */ - @ 0b0000 /* zero */ - @ CP0ConfigK0), - (0b10000,0b001) => zero_extend( /* 16, sel 1: Config1 */ - 0b1 /* M */ - @ TLBIndexMax /* MMU size-1 */ - @ 0b000 /* IS icache sets */ - @ 0b000 /* IL icache lines */ - @ 0b000 /* IA icache assoc. */ - @ 0b000 /* DS dcache sets */ - @ 0b000 /* DL dcache lines */ - @ 0b000 /* DA dcache assoc. */ - @ bool_to_bits(have_cp2) /* C2 CP2 presence */ - @ 0b0 /* MD MDMX implemented */ - @ 0b0 /* PC performance counters */ - @ 0b0 /* WR watch registers */ - @ 0b0 /* CA 16e code compression */ - @ 0b0 /* EP EJTAG */ - @ 0b0), /* FP FPU present */ - (0b10000,0b010) => zero_extend( /* 16, sel 2: Config2 */ - 0b1 /* M */ - @ 0b000 /* TU L3 control */ - @ 0b0000 /* TS L3 sets */ - @ 0b0000 /* TL L3 lines */ - @ 0b0000 /* TA L3 assoc. */ - @ 0b0000 /* SU L2 control */ - @ 0b0000 /* SS L2 sets */ - @ 0b0000 /* SL L2 lines */ - @ 0b0000), /* SA L2 assoc. */ - (0b10000,0b011) => 0x0000000000002000, /* 16, sel 3: Config3 zero except for bit 13 == ulri */ - (0b10000,0b101) => 0x0000000000000000, /* 16, sel 5: Config5 beri specific -- no extended TLB */ - (0b10001,0b000) => CP0LLAddr, /* 17, sel 0: LLAddr */ - (0b10010,0b000) => zero_extend(0b0), /* 18, WatchLo */ - (0b10011,0b000) => zero_extend(0b0), /* 19, WatchHi */ - (0b10100,0b000) => TLBXContext.bits(), /* 20, XContext */ - (0b11110,0b000) => CP0ErrorEPC, /* 30, ErrorEPC */ - _ => (SignalException(ResI)) - } in - wGPR(rt) = if (double) then result else sign_extend(result[31..0]) -} - -/* simulator halt instruction "MTC0 rt, r23" (cheri specific behaviour) */ -union clause ast = HCF : unit -function clause decode (0b010000 @ 0b00100 @ rt : regno @ 0b10111 @ 0b00000000000) = - Some(HCF()) - -function clause decode (0b010000 @ 0b00100 @ rt : regno @ 0b11010 @ 0b00000000000) = - Some(HCF()) - -function clause execute (HCF()) = - () /* halt instruction actually executed by interpreter framework */ - -union clause ast = MTC0 : (regno, regno, bits(3), bool) -function clause decode (0b010000 @ 0b00100 @ rt : regno @ rd : regno @ 0b00000000 @ sel : bits(3)) = - Some(MTC0(rt, rd, sel, false)) /* MTC0 */ -function clause decode (0b010000 @ 0b00101 @ rt : regno @ rd : regno @ 0b00000000 @ sel : bits(3)) = - Some(MTC0(rt, rd, sel, true)) /* DMTC0 */ -function clause execute (MTC0(rt, rd, sel, double)) = { - checkCP0Access(); - let reg_val = rGPR(rt) in - match (rd, sel) - { - (0b00000,0b000) => TLBIndex = mask(reg_val), /* NB no write to TLBProbe */ - (0b00001,0b000) => (), /* TLBRandom is read only */ - (0b00010,0b000) => TLBEntryLo0->bits() = reg_val, - (0b00011,0b000) => TLBEntryLo1->bits() = reg_val, - (0b00100,0b000) => TLBContext->PTEBase() = reg_val[63..23], - (0b00100,0b010) => CP0UserLocal = reg_val, - (0b00101,0b000) => TLBPageMask = reg_val[28..13], - (0b00110,0b000) => { - TLBWired = mask(reg_val); - TLBRandom = TLBIndexMax; - }, - (0b00111,0b000) => CP0HWREna = (reg_val[31..29] @ 0b0000000000000000000000000 @ reg_val[3..0]), - (0b01000,0b000) => (), /* BadVAddr read only */ - (0b01001,0b000) => CP0Count = reg_val[31..0], - (0b01010,0b000) => { - TLBEntryHi->R() = reg_val[63..62]; - TLBEntryHi->VPN2() = reg_val[39..13]; - TLBEntryHi->ASID() = reg_val[7..0]; - }, - (0b01011,0b000) => { /* 11, sel 0: Compare reg */ - CP0Compare = reg_val[31..0]; - CP0Cause->IP() = CP0Cause.IP() & 0x7f; /* clear IP7 */ - }, - (0b01100,0b000) => { /* 12 Status */ - CP0Status->CU() = reg_val[31..28]; - CP0Status->BEV() = reg_val[22]; - CP0Status->IM() = reg_val[15..8]; - CP0Status->KX() = reg_val[7]; - CP0Status->SX() = reg_val[6]; - CP0Status->UX() = reg_val[5]; - CP0Status->KSU() = reg_val[4..3]; - CP0Status->ERL() = reg_val[2]; - CP0Status->EXL() = reg_val[1]; - CP0Status->IE() = reg_val[0]; - }, - (0b01101,0b000) => { /* 13 Cause */ - CP0Cause->IV() = reg_val[23]; /* TODO special interrupt vector not implemeneted */ - let ip = CP0Cause.IP() in - CP0Cause->IP() = ((ip[7..2]) @ (reg_val[9..8])); - }, - (0b01110,0b000) => CP0EPC = reg_val, /* 14, EPC */ - (0b10000,0b000) => CP0ConfigK0 = reg_val[2..0], /* K0 cache config 16: Config0 */ - (0b10100,0b000) => TLBXContext->XPTEBase() = reg_val[63..33], - (0b11110,0b000) => CP0ErrorEPC = reg_val, /* 30, ErrorEPC */ - _ => (SignalException(ResI)) - } -} - -val TLBWriteEntry : TLBIndexT -> unit effect {rreg, wreg, escape} -function TLBWriteEntry(idx) = { - pagemask = TLBPageMask; - match pagemask { - 0x0000 => (), - 0x0003 => (), - 0x000f => (), - 0x003f => (), - 0x00ff => (), - 0x03ff => (), - 0x0fff => (), - 0x3fff => (), - 0xffff => (), - _ => (SignalException(MCheck)) - }; - let i as atom(_) = unsigned(idx) in - let entry = TLBEntries[i] in { - entry.pagemask() = pagemask; - entry.r() = TLBEntryHi.R(); - entry.vpn2() = TLBEntryHi.VPN2(); - entry.asid() = TLBEntryHi.ASID(); - entry.g() = ((TLBEntryLo0.G()) & (TLBEntryLo1.G())); - entry.valid() = bitone; - entry.caps0() = TLBEntryLo0.CapS(); - entry.capl0() = TLBEntryLo0.CapL(); - entry.pfn0() = TLBEntryLo0.PFN(); - entry.c0() = TLBEntryLo0.C(); - entry.d0() = TLBEntryLo0.D(); - entry.v0() = TLBEntryLo0.V(); - entry.caps1() = TLBEntryLo1.CapS(); - entry.capl1() = TLBEntryLo1.CapL(); - entry.pfn1() = TLBEntryLo1.PFN(); - entry.c1() = TLBEntryLo1.C(); - entry.d1() = TLBEntryLo1.D(); - entry.v1() = TLBEntryLo1.V(); - } -} - -union clause ast = TLBWI : unit -function clause decode (0b010000 @ 0b10000000000000000000 @ 0b000010) = Some(TLBWI() : ast) -function clause execute (TLBWI()) = { - checkCP0Access(); - TLBWriteEntry(TLBIndex); -} - -union clause ast = TLBWR : unit -function clause decode (0b010000 @ 0b10000000000000000000 @ 0b000110) = Some(TLBWR() : ast) -function clause execute (TLBWR()) = { - checkCP0Access(); - TLBWriteEntry(TLBRandom); -} - -union clause ast = TLBR : unit -function clause decode (0b010000 @ 0b10000000000000000000 @ 0b000001) = Some(TLBR() : ast) -function clause execute (TLBR()) = { - checkCP0Access(); - let i as atom(_) = unsigned(TLBIndex) in - let entry = reg_deref(TLBEntries[i]) in { - TLBPageMask = entry.pagemask(); - TLBEntryHi->R() = entry.r(); - TLBEntryHi->VPN2() = entry.vpn2(); - TLBEntryHi->ASID() = entry.asid(); - TLBEntryLo0->CapS()= entry.caps0(); - TLBEntryLo0->CapL()= entry.capl0(); - TLBEntryLo0->PFN() = entry.pfn0(); - TLBEntryLo0->C() = entry.c0(); - TLBEntryLo0->D() = entry.d0(); - TLBEntryLo0->V() = entry.v0(); - TLBEntryLo0->G() = entry.g(); - TLBEntryLo1->CapS()= entry.caps1(); - TLBEntryLo1->CapL()= entry.capl1(); - TLBEntryLo1->PFN() = entry.pfn1(); - TLBEntryLo1->C() = entry.c1(); - TLBEntryLo1->D() = entry.d1(); - TLBEntryLo1->V() = entry.v1(); - TLBEntryLo1->G() = entry.g(); - } -} - -union clause ast = TLBP : unit -function clause decode (0b010000 @ 0b10000000000000000000 @ 0b001000) = Some(TLBP() : ast) -function clause execute (TLBP()) = { - checkCP0Access(); - let result = tlbSearch(TLBEntryHi.bits()) in - match result { - (Some(idx)) => { - TLBProbe = [bitzero]; - TLBIndex = idx; - }, - None() => { - TLBProbe = [bitone]; - TLBIndex = 0b000000; - } - } -} - -union clause ast = RDHWR : (regno, regno) -function clause decode (0b011111 @ 0b00000 @ rt : regno @ rd : regno @ 0b00000 @ 0b111011) = - Some(RDHWR(rt, rd)) -function clause execute (RDHWR(rt, rd)) = { - let accessLevel = getAccessLevel() in - let haveAccessLevel : bool = accessLevel == Kernel in - let haveCU0 : bool = bitone == (CP0Status.CU()[0]) in - let rdi as atom(_) = unsigned(rd) in - let haveHWREna : bool = bitone == (CP0HWREna[rdi]) in - if ~(haveAccessLevel | haveCU0 | haveHWREna) then - (SignalException(ResI)); - let temp : bits(64) = match rd { - 0b00000 => zero_extend([bitzero]), /* CPUNum */ - 0b00001 => zero_extend([bitzero]), /* SYNCI_step */ - 0b00010 => zero_extend(CP0Count), /* Count */ - 0b00011 => zero_extend([bitone]), /* Count resolution */ - 0b11101 => CP0UserLocal, /* User local register */ - _ => (SignalException(ResI)) - } in - wGPR(rt) = temp; -} - -union clause ast = ERET : unit - -function clause decode (0b010000 @ 0b1 @ 0b0000000000000000000 @ 0b011000) = - Some(ERET()) -function clause execute (ERET()) = - { - checkCP0Access(); - ERETHook(); - CP0LLBit = 0b0; - if (CP0Status.ERL() == bitone) then - { - nextPC = CP0ErrorEPC; - CP0Status->ERL() = 0b0; - } - else - { - nextPC = CP0EPC; - CP0Status->EXL() = 0b0; - } - } diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail deleted file mode 100644 index 6babfd19..00000000 --- a/mips/mips_prelude.sail +++ /dev/null @@ -1,649 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* mips_prelude.sail: declarations of mips registers, and functions common - to mips instructions (e.g. address translation) */ - -register PC : bits(64) -register nextPC : bits(64) - -/* CP0 Registers */ - -bitfield CauseReg : bits(32) = { - BD : 31, /* branch delay */ - /*Z0 : 30,*/ - CE : 29.. 28, /* for coprocessor enable exception */ - /*Z1 : 27.. 24,*/ - IV : 23, /* special interrupt vector not supported */ - WP : 22, /* watchpoint exception occurred */ - /*Z2 : 21.. 16, */ - IP : 15.. 8, /* interrupt pending bits */ - /*Z3 : 7,*/ - ExcCode : 6.. 2, /* code of last exception */ - /*Z4 : 1.. 0,*/ -} - -bitfield TLBEntryLoReg : bits(64) = { - CapS : 63, - CapL : 62, - PFN : 29.. 6, - C : 5.. 3, - D : 2, - V : 1, - G : 0, -} - -bitfield TLBEntryHiReg : bits(64) = { - R : 63.. 62, - VPN2 : 39.. 13, - ASID : 7.. 0, -} - -bitfield ContextReg : bits(64) = { - PTEBase : 63.. 23, - BadVPN2 : 22.. 4, - /*ZR : 3.. 0,*/ -} - -bitfield XContextReg : bits(64) = { - XPTEBase : 63.. 33, - XR : 32.. 31, - XBadVPN2 : 30.. 4, -} - -let TLBNumEntries = 64 -type TLBIndexT = (bits(6)) -let TLBIndexMax : TLBIndexT = 0b111111 - -val MAX : forall 'n. atom('n) -> atom(2 ^ 'n - 1) effect pure -function MAX(n) = pow2(n) - 1 - -let MAX_U64 = MAX(64) /*unsigned(0xffffffffffffffff)*/ -let MAX_VA = MAX(40) /*unsigned(0xffffffffff)*/ -let MAX_PA = MAX(36) /*unsigned(0xfffffffff)*/ - -bitfield TLBEntry : bits(117) = { - pagemask : 116.. 101, - r : 100.. 99, - vpn2 : 98.. 72, - asid : 71.. 64, - g : 63, - valid : 62, - caps1 : 61, - capl1 : 60, - pfn1 : 59.. 36, - c1 : 35.. 33, - d1 : 32, - v1 : 31, - caps0 : 30, - capl0 : 29, - pfn0 : 28.. 5, - c0 : 4.. 2, - d0 : 1, - v0 : 0, -} - -register TLBProbe : bits(1) -register TLBIndex : TLBIndexT -register TLBRandom : TLBIndexT -register TLBEntryLo0 : TLBEntryLoReg -register TLBEntryLo1 : TLBEntryLoReg -register TLBContext : ContextReg -register TLBPageMask : bits(16) -register TLBWired : TLBIndexT -register TLBEntryHi : TLBEntryHiReg -register TLBXContext : XContextReg - -register TLBEntry00 : TLBEntry -register TLBEntry01 : TLBEntry -register TLBEntry02 : TLBEntry -register TLBEntry03 : TLBEntry -register TLBEntry04 : TLBEntry -register TLBEntry05 : TLBEntry -register TLBEntry06 : TLBEntry -register TLBEntry07 : TLBEntry -register TLBEntry08 : TLBEntry -register TLBEntry09 : TLBEntry -register TLBEntry10 : TLBEntry -register TLBEntry11 : TLBEntry -register TLBEntry12 : TLBEntry -register TLBEntry13 : TLBEntry -register TLBEntry14 : TLBEntry -register TLBEntry15 : TLBEntry -register TLBEntry16 : TLBEntry -register TLBEntry17 : TLBEntry -register TLBEntry18 : TLBEntry -register TLBEntry19 : TLBEntry -register TLBEntry20 : TLBEntry -register TLBEntry21 : TLBEntry -register TLBEntry22 : TLBEntry -register TLBEntry23 : TLBEntry -register TLBEntry24 : TLBEntry -register TLBEntry25 : TLBEntry -register TLBEntry26 : TLBEntry -register TLBEntry27 : TLBEntry -register TLBEntry28 : TLBEntry -register TLBEntry29 : TLBEntry -register TLBEntry30 : TLBEntry -register TLBEntry31 : TLBEntry -register TLBEntry32 : TLBEntry -register TLBEntry33 : TLBEntry -register TLBEntry34 : TLBEntry -register TLBEntry35 : TLBEntry -register TLBEntry36 : TLBEntry -register TLBEntry37 : TLBEntry -register TLBEntry38 : TLBEntry -register TLBEntry39 : TLBEntry -register TLBEntry40 : TLBEntry -register TLBEntry41 : TLBEntry -register TLBEntry42 : TLBEntry -register TLBEntry43 : TLBEntry -register TLBEntry44 : TLBEntry -register TLBEntry45 : TLBEntry -register TLBEntry46 : TLBEntry -register TLBEntry47 : TLBEntry -register TLBEntry48 : TLBEntry -register TLBEntry49 : TLBEntry -register TLBEntry50 : TLBEntry -register TLBEntry51 : TLBEntry -register TLBEntry52 : TLBEntry -register TLBEntry53 : TLBEntry -register TLBEntry54 : TLBEntry -register TLBEntry55 : TLBEntry -register TLBEntry56 : TLBEntry -register TLBEntry57 : TLBEntry -register TLBEntry58 : TLBEntry -register TLBEntry59 : TLBEntry -register TLBEntry60 : TLBEntry -register TLBEntry61 : TLBEntry -register TLBEntry62 : TLBEntry -register TLBEntry63 : TLBEntry - -let TLBEntries : vector(64, dec, register(TLBEntry)) = [ - ref TLBEntry63, - ref TLBEntry62, - ref TLBEntry61, - ref TLBEntry60, - ref TLBEntry59, - ref TLBEntry58, - ref TLBEntry57, - ref TLBEntry56, - ref TLBEntry55, - ref TLBEntry54, - ref TLBEntry53, - ref TLBEntry52, - ref TLBEntry51, - ref TLBEntry50, - ref TLBEntry49, - ref TLBEntry48, - ref TLBEntry47, - ref TLBEntry46, - ref TLBEntry45, - ref TLBEntry44, - ref TLBEntry43, - ref TLBEntry42, - ref TLBEntry41, - ref TLBEntry40, - ref TLBEntry39, - ref TLBEntry38, - ref TLBEntry37, - ref TLBEntry36, - ref TLBEntry35, - ref TLBEntry34, - ref TLBEntry33, - ref TLBEntry32, - ref TLBEntry31, - ref TLBEntry30, - ref TLBEntry29, - ref TLBEntry28, - ref TLBEntry27, - ref TLBEntry26, - ref TLBEntry25, - ref TLBEntry24, - ref TLBEntry23, - ref TLBEntry22, - ref TLBEntry21, - ref TLBEntry20, - ref TLBEntry19, - ref TLBEntry18, - ref TLBEntry17, - ref TLBEntry16, - ref TLBEntry15, - ref TLBEntry14, - ref TLBEntry13, - ref TLBEntry12, - ref TLBEntry11, - ref TLBEntry10, - ref TLBEntry09, - ref TLBEntry08, - ref TLBEntry07, - ref TLBEntry06, - ref TLBEntry05, - ref TLBEntry04, - ref TLBEntry03, - ref TLBEntry02, - ref TLBEntry01, - ref TLBEntry00 -] - -register CP0Compare : bits(32) -register CP0Cause : CauseReg -register CP0EPC : bits(64) -register CP0ErrorEPC : bits(64) -register CP0LLBit : bits(1) -register CP0LLAddr : bits(64) -register CP0BadVAddr : bits(64) -register CP0Count : bits(32) -register CP0HWREna : bits(32) -register CP0UserLocal : bits(64) -register CP0ConfigK0 : bits(3) - -bitfield StatusReg : bits(32) = { - CU : 31.. 28, /* co-processor enable bits */ - /* RP/FR/RE/MX/PX not implemented */ - BEV : 22, /* use boot exception vectors (initialised to one) */ - /* TS/SR/NMI not implemented */ - IM : 15.. 8, /* Interrupt mask */ - KX : 7, /* kernel 64-bit enable */ - SX : 6, /* supervisor 64-bit enable */ - UX : 5, /* user 64-bit enable */ - KSU : 4.. 3, /* Processor mode */ - ERL : 2, /* error level (should be initialised to one, but BERI is different) */ - EXL : 1, /* exception level */ - IE : 0, /* interrupt enable */ -} -register CP0Status : StatusReg - -/* Implementation registers -- not ISA defined */ -register branchPending : bits(1) /* Set by branch instructions to implement branch delay */ -register inBranchDelay : bits(1) /* Needs to be set by outside world when in branch delay slot */ -register delayedPC : bits(64) /* Set by branch instructions to implement branch delay */ - -val execute_branch : bits(64) -> unit effect {wreg} -function execute_branch(pc) = { - delayedPC = pc; - branchPending = 0b1; -} - -/* General purpose registers */ - - -/* Special registers For MUL/DIV */ -register HI : bits(64) -register LO : bits(64) - -register GPR : vector(32, dec, bits(64)) - -/* JTAG Uart registers */ - -register UART_WDATA : bits(8) -register UART_WRITTEN : bits(1) -register UART_RDATA : bits(8) -register UART_RVALID : bits(1) - -/* Check whether a given 64-bit vector is a properly sign extended 32-bit word */ -val NotWordVal : bits(64) -> bool effect pure -function NotWordVal (word) = - (word[31] ^^ 32) != word[63..32] - -/* Read numbered GP reg. (r0 is always zero) */ -val rGPR : bits(5) -> bits(64) effect {rreg} -function rGPR idx = { - let i as atom(_) = unsigned(idx) in - if i == 0 then 0x0000000000000000 else GPR[i] -} - -/* Write numbered GP reg. (writes to r0 ignored) */ -val wGPR : (bits(5), bits(64)) -> unit effect {wreg} -function wGPR (idx, v) = { - let i as atom(_) = unsigned(idx) in - if i != 0 then { - /*prerr_string(string_of_int(i)); - prerr_bits(" <- ", v);*/ - GPR[i] = v; - }; -} - -val MEMr = {lem: "MEMr"} : forall 'n, 'n >= 0. - ( bits(64) , atom('n) ) -> (bits(8 * 'n)) effect { rmem } -val MEMr_reserve = {lem: "MEMr_reserve"} : forall 'n, 'n >= 0. - ( bits(64) , atom('n) ) -> (bits(8 * 'n)) effect { rmem } -val MEM_sync = {lem: "MEM_sync"} : - unit -> unit effect { barr } - -val MEMea = {lem: "MEMea"} : forall 'n. - ( bits(64) , atom('n)) -> unit effect { eamem } -val MEMea_conditional = {lem: "MEMea_conditional"} : forall 'n. - ( bits(64) , atom('n)) -> unit effect { eamem } -val MEMval = {lem: "MEMval"} : forall 'n. - ( bits(64) , atom('n), bits(8*'n)) -> unit effect { wmv } -val MEMval_conditional = {lem: "MEMval_conditional"} : forall 'n. - ( bits(64) , atom('n), bits(8*'n)) -> bool effect { wmv } - -/* Extern nops with effects, sometimes useful for faking effect */ -val skip_eamem = "skip" : unit -> unit effect {eamem} -val skip_barr = "skip" : unit -> unit effect {barr} -val skip_wreg = "skip" : unit -> unit effect {wreg} -val skip_rreg = "skip" : unit -> unit effect {rreg} -val skip_wmvt = "skip" : unit -> unit effect {wmvt} -val skip_rmemt = "skip" : unit -> unit effect {rmemt} -val skip_escape = "skip" : unit -> unit effect {escape} - -function MEMr (addr, size) = __MIPS_read(addr, size) -function MEMr_reserve (addr, size) = __MIPS_read(addr, size) -function MEM_sync () = skip_barr() - -function MEMea (addr, size) = skip_eamem() -function MEMea_conditional (addr, size) = skip_eamem() -function MEMval (addr, size, data) = __MIPS_write(addr, size, data) -function MEMval_conditional (addr, size, data) = { __MIPS_write(addr, size, data); true } - -enum Exception = -{ - Interrupt, TLBMod, TLBL, TLBS, AdEL, AdES, Sys, Bp, ResI, CpU, Ov, Tr, C2E, C2Trap, - XTLBRefillL, XTLBRefillS, XTLBInvL, XTLBInvS, MCheck -} - -/* Return the ISA defined code for an exception condition */ -function ExceptionCode (ex) : Exception -> bits(5)= - let x : bits(8) = match ex - { - Interrupt => 0x00, /* Interrupt */ - TLBMod => 0x01, /* TLB modification exception */ - TLBL => 0x02, /* TLB exception (load or fetch) */ - TLBS => 0x03, /* TLB exception (store) */ - AdEL => 0x04, /* Address error (load or fetch) */ - AdES => 0x05, /* Address error (store) */ - Sys => 0x08, /* Syscall */ - Bp => 0x09, /* Breakpoint */ - ResI => 0x0a, /* Reserved instruction */ - CpU => 0x0b, /* Coprocessor Unusable */ - Ov => 0x0c, /* Arithmetic overflow */ - Tr => 0x0d, /* Trap */ - C2E => 0x12, /* C2E coprocessor 2 exception */ - C2Trap => 0x12, /* C2Trap maps to same exception code, different vector */ - XTLBRefillL => 0x02, - XTLBRefillS => 0x03, - XTLBInvL => 0x02, - XTLBInvS => 0x03, - MCheck => 0x18 - } in x[4..0] - - -val SignalExceptionMIPS : forall ('o : Type) . (Exception, bits(64)) -> 'o effect {escape, rreg, wreg} -function SignalExceptionMIPS (ex, kccBase) = - { - /* Only update EPC and BD if not already in EXL mode */ - if (~ (CP0Status.EXL())) then - { - if (inBranchDelay[0]) then - { - CP0EPC = PC - 4; - CP0Cause->BD() = 0b1; - } - else - { - CP0EPC = PC; - CP0Cause->BD() = 0b0; - } - }; - - /* choose an exception vector to branch to. Some are not supported - e.g. Reset */ - vectorOffset = - if (CP0Status.EXL()) then - 0x180 /* Always use common vector if in exception mode already */ - else if ((ex == XTLBRefillL) | (ex == XTLBRefillS)) then - 0x080 - else if (ex == C2Trap) then - 0x280 /* Special vector for CHERI traps */ - else - 0x180; /* Common vector */ - vectorBase : bits(64) = if CP0Status.BEV() then - 0xFFFFFFFFBFC00200 - else - 0xFFFFFFFF80000000; - /* On CHERI we have to subtract KCC.base so that we end up at the - right absolute vector address after indirecting via new PCC */ - nextPC = vectorBase + sign_extend(vectorOffset) - kccBase; - CP0Cause->ExcCode() = ExceptionCode(ex); - CP0Status->EXL() = 0b1; - throw (ISAException()); - } - -/* Defined either in mips_wrappers (directly calling SignalExceptionMIPS) or in cheri_prelude_common (cheri things plus above) */ -val SignalException : forall ('o : Type) . Exception -> 'o effect {escape, rreg, wreg} - -val SignalExceptionBadAddr : forall ('o : Type) . (Exception, bits(64)) -> 'o effect {escape, rreg, wreg} -function SignalExceptionBadAddr(ex, badAddr) = - { - CP0BadVAddr = badAddr; - SignalException(ex); - } - -val SignalExceptionTLB : forall ('o : Type) . (Exception, bits(64)) -> 'o effect {escape, rreg, wreg} -function SignalExceptionTLB(ex, badAddr) = { - CP0BadVAddr = badAddr; - TLBContext->BadVPN2() = (badAddr[31..13]); - TLBXContext->XBadVPN2()= (badAddr[39..13]); - TLBXContext->XR() = (badAddr[63..62]); - TLBEntryHi->R() = (badAddr[63..62]); - TLBEntryHi->VPN2() = (badAddr[39..13]); - SignalException(ex); -} - -enum MemAccessType = {Instruction, LoadData, StoreData} -enum AccessLevel = {User, Supervisor, Kernel} - -val int_of_AccessLevel : AccessLevel -> {|0, 1, 2|} effect pure -function int_of_AccessLevel level = - match level { - User => 0, - Supervisor => 1, - Kernel => 2 - } - -/*! -Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. - */ -val grantsAccess : (AccessLevel, AccessLevel) -> bool -function grantsAccess (currentLevel, requiredLevel) = - int_of_AccessLevel(currentLevel) >= int_of_AccessLevel(requiredLevel) - -/*! -Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. - */ -val getAccessLevel : unit -> AccessLevel effect {rreg} -function getAccessLevel() = - if ((CP0Status.EXL()) | (CP0Status.ERL())) then - Kernel - else match CP0Status.KSU() - { - 0b00 => Kernel, - 0b01 => Supervisor, - 0b10 => User, - _ => User /* behaviour undefined, assume user */ - } - -val checkCP0Access : unit->unit effect{escape, rreg, wreg} -function checkCP0Access () = - { - let accessLevel = getAccessLevel() in - if ((accessLevel != Kernel) & (~(CP0Status.CU()[0]))) then - { - CP0Cause->CE() = 0b00; - SignalException(CpU); - } - } - -val incrementCP0Count : unit -> unit effect {rreg,wreg,escape} -function incrementCP0Count() = { - TLBRandom = (if (TLBRandom == TLBWired) - then (TLBIndexMax) else (TLBRandom - 1)); - - CP0Count = (CP0Count + 1); - if (CP0Count == CP0Compare) then { - CP0Cause->IP() = CP0Cause.IP() | 0x80; /* IP7 is timer interrupt */ - }; - - let ims = CP0Status.IM() in - let ips = CP0Cause.IP() in - let ie = CP0Status.IE() in - let exl = CP0Status.EXL() in - let erl = CP0Status.ERL() in - if ((~(exl)) & (~(erl)) & ie & ((ips & ims) != 0x00)) then - SignalException(Interrupt); -} - -type regno = bits(5) /* a register number */ -type imm16 = bits(16) /* 16-bit immediate */ -/* a commonly used instruction format with three register operands */ -type regregreg = (regno, regno, regno) -/* a commonly used instruction format with two register operands and 16-bit immediate */ -type regregimm16 = (regno, regno, imm16) - -enum decode_failure = { - no_matching_pattern, - unsupported_instruction, - illegal_instruction, - internal_error -} - -/* Used by branch and trap instructions */ -enum Comparison = { - EQ, /* equal */ - NE, /* not equal */ - GE, /* signed greater than or equal */ - GEU,/* unsigned greater than or equal */ - GT, /* signed strictly greater than */ - LE, /* signed less than or equal */ - LT, /* signed strictly less than */ - LTU /* unsigned less than or qual */ -} - -val compare : (Comparison, bits(64), bits(64)) -> bool -function compare (cmp, valA, valB) = - match cmp { - EQ => valA == valB, - NE => valA != valB, - GE => valA >=_s valB, - GEU => valA >=_u valB, - GT => valB <_s valA, - LE => valB >=_s valA, - LT => valA <_s valB, - LTU => valA <_u valB - } -enum WordType = { B, H, W, D} -enum WordTypeUnaligned = { WL, WR, DL, DR } - -val wordWidthBytes : WordType -> range(1, 8) -function wordWidthBytes(w) = - match w { - B => 1, - H => 2, - W => 4, - D => 8 - } - -/* This function checks that memory accesses are naturally aligned - -- it is disabled in favour of BERI specific behaviour below. -function bool isAddressAligned(addr, (WordType) wordType) = - match wordType { - B => true - H => (addr[0] == 0) - W => (addr[1..0] == 0b00) - D => (addr[2..0] == 0b000) - } -*/ - -/* BERI relaxes the natural alignment requirement for loads and stores - but still throws an exception if an access spans a cache line - boundary. Here we assume this is 32 bytes so that we don't have to - worry about clearing multiple tags when an access spans more than - one capability. Capability load/stores are still naturally - aligned. Provided this is a factor of smallest supported page size - (4k) we don't need to worry about accesses spanning page boundaries - either. -*/ -let alignment_width = 16 -val isAddressAligned : (bits(64), WordType) -> bool -function isAddressAligned (addr, wordType) = - let a = unsigned(addr) in - a / alignment_width == (a + wordWidthBytes(wordType) - 1) / alignment_width - -val reverse_endianness = "reverse_endianness" : forall 'W, 'W >= 1. bits(8 * 'W) -> bits(8 * 'W) effect pure - -/* -function rec forall Nat 'W, 'W >= 1. bits(8 * 'W) reverse_endianness' (w, value) = -{ - ([:8 * 'W:]) width = length(value); - if width <= 8 - then value - else value[7..0] : reverse_endianness'(w - 1, value[(width - 1) .. 8]) -} - - - -function rec forall Nat 'W, 'W >= 1. bits(8 * 'W) reverse_endianness ((bits(8 * 'W)) value) = -{ - reverse_endianness'(sizeof 'W, value) -}*/ - -val MEMr_wrapper : forall 'n, 1 <= 'n <= 8 . (bits(64), atom('n)) -> bits(8*'n) effect {rmem, rreg, wreg} -function MEMr_wrapper (addr, size) = - if (addr == 0x000000007f000000) then - { - let rvalid = UART_RVALID in - { - UART_RVALID = [bitzero]; - mask(0x00000000 @ UART_RDATA @ rvalid @ 0b0000000 @ 0x0000) - } - } - else if (addr == 0x000000007f000004) then - mask(0x000000000004ffff) /* Always plenty of write space available and jtag activity */ - else - reverse_endianness(MEMr(addr, size)) /* MEMr assumes little endian */ - -val MEMr_reserve_wrapper : forall 'n, 1 <= 'n <= 8 . ( bits(64) , atom('n) ) -> (bits(8 * 'n)) effect { rmem } -function MEMr_reserve_wrapper (addr , size) = - reverse_endianness(MEMr_reserve(addr, size)) - - -function init_cp0_state () : unit -> unit = { - CP0Status->BEV() = bitone; -} - -val init_cp2_state : unit -> unit effect {wreg} -val cp2_next_pc: unit -> unit effect {rreg, wreg} -val dump_cp2_state : unit -> unit effect {rreg, escape} diff --git a/mips/mips_regfp.sail b/mips/mips_regfp.sail deleted file mode 100644 index 0c77fb9f..00000000 --- a/mips/mips_regfp.sail +++ /dev/null @@ -1,455 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -let GPRs : vector <0, 32, inc, string > = - [ "GPR00", "GPR01", "GPR02", "GPR03", "GPR04", "GPR05", "GPR06", "GPR07", "GPR08", "GPR09", "GPR10", - "GPR11", "GPR12", "GPR13", "GPR14", "GPR15", "GPR16", "GPR17", "GPR18", "GPR19", "GPR20", - "GPR21", "GPR22", "GPR23", "GPR24", "GPR25", "GPR26", "GPR27", "GPR28", "GPR29", "GPR30", "GPR31" - ] - -let CIA_fp = RFull("CIA") -let NIA_fp = RFull("NIA") - -function (regfps,regfps,regfps,niafps,diafp,instruction_kind) initial_analysis ((ast) instr) = { - (regfps) iR = [|| ||]; - (regfps) oR = [|| ||]; - (regfps) aR = [|| ||]; - (instruction_kind) ik = IK_simple; - (niafps) Nias = [|| ||]; - (diafp) Dia = DIAFP_none; - - switch instr { - (DADDIU (rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (DADDU (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DADDI (rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (DADD (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (ADD(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (ADDI(rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (ADDU(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (ADDIU(rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (DSUBU (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSUB (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SUB(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SUBU(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (AND (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (ANDI (rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (OR (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (ORI (rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (NOR (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (XOR (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (XORI (rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (LUI (rt, imm)) => { - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (DSLL (rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSLL32 (rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSLLV (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSRA (rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSRA32 (rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSRAV (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSRL (rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSRL32 (rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (DSRLV (rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SLL(rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SLLV(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SRA(rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SRAV(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SRL(rt, rd, sa)) => { - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SRLV(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SLT(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SLTI(rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (SLTU(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (SLTIU(rs, rt, imm)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (MOVN(rs, rt, rd)) => { - /* XXX don't always write rd */ - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (MOVZ(rs, rt, rd)) => { - /* XXX don't always write rd */ - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (MFHI(rd)) => { - iR = RFull("HI") :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (MFLO(rd)) => { - iR = RFull("LO") :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (MTHI(rs)) => { - oR = RFull("HI") :: oR; - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - } - (MTLO(rs)) => { - oR = RFull("LO") :: oR; - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - } - (MUL(rs, rt, rd)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - if rd == 0 then () else oR = RFull(GPRs[rd]) :: oR; - } - (MULT(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (MULTU(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (DMULT(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (DMULTU(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (MADD(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - iR = RFull("HI") :: RFull ("LO") :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (MADDU(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - iR = RFull("HI") :: RFull ("LO") :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (MSUB(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - iR = RFull("HI") :: RFull ("LO") :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (MSUBU(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - iR = RFull("HI") :: RFull ("LO") :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (DIV(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (DIVU(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (DDIV(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (DDIVU(rs, rt)) => { - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - oR = RFull("HI") :: RFull ("LO") :: oR; - } - (J(offset)) => { - /* XXX actually unconditional jump */ - /*ik = IK_cond_branch;*/ - Dia = DIAFP_concrete((PC + 4)[63..28] : offset : 0b00); - } - (JAL(offset)) => { - /* XXX actually unconditional jump */ - /*ik = IK_cond_branch;*/ - oR = RFull("GPR31") :: oR; - Dia = DIAFP_concrete((PC + 4)[63..28] : offset : 0b00); - } - (JR(rs)) => { - /* XXX actually unconditional jump */ - /*ik = IK_cond_branch;*/ - iR = RFull(GPRs[rs]) :: iR; - Dia = DIAFP_reg(RFull(GPRs[rs])); - } - (JALR(rs, rd)) => { - /* XXX actually unconditional jump */ - /*ik = IK_cond_branch;*/ - iR = RFull(GPRs[rs]) :: iR; - oR = RFull("GPR31") :: oR; - Dia = DIAFP_reg(RFull(GPRs[rs])); - } - (BEQ(rs, rd, imm, ne, likely)) => { - ik = IK_cond_branch; - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if rd == 0 then () else iR = RFull(GPRs[rd]) :: iR; - let offset : bits(64) = (sign_extend(imm : 0b00) + 4) in - Dia = DIAFP_concrete (PC + offset); - } - (BCMPZ(rs, imm, cmp, link, likely)) => { - ik = IK_cond_branch; - if rs == 0 then () else iR = RFull(GPRs[rs]) :: iR; - if link then - oR = RFull("GPR31") :: oR; - let offset : bits(64) = (sign_extend(imm : 0b00) + 4) in - Dia = DIAFP_concrete (PC + offset); - } - (SYSCALL_THREAD_START) => () -/* - - case (SYSCALL) = - case (BREAK) = - case (WAIT) = { - case (TRAPREG(rs, rt, cmp)) = - case (TRAPIMM(rs, imm, cmp)) = -*/ - (Load(width, signed, linked, base, rt, offset)) => { - ik = IK_mem_read (if linked then Read_reserve else Read_plain); - if linked then oR = RFull("CP0LLBit")::RFull("CP0LLAddr")::oR else (); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (Store(width, conditional, base, rt, offset)) => { - ik = IK_mem_write(if conditional then Write_conditional else Write_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if conditional then iR = RFull("CP0LLBit")::iR else (); - if (conditional & (rt != 0)) then oR = RFull(GPRs[rt])::oR else (); - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - } - (LWL(base, rt, offset)) => { - ik = IK_mem_read(Read_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (LWR(base, rt, offset)) => { - ik = IK_mem_read(Read_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (SWL(base, rt, offset)) => { - ik = IK_mem_write(Write_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - } - (SWR(base, rt, offset)) => { - ik = IK_mem_write(Write_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - } - (LDL(base, rt, offset)) => { - ik = IK_mem_read(Read_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (LDR(base, rt, offset)) => { - ik = IK_mem_read(Read_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else oR = RFull(GPRs[rt]) :: oR; - } - (SDL(base, rt, offset)) => { - ik = IK_mem_write(Write_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - } - (SDR(base, rt, offset)) => { - ik = IK_mem_write(Write_plain); - if base == 0 then () else aR = RFull(GPRs[base]) :: aR; - iR = aR; - if rt == 0 then () else iR = RFull(GPRs[rt]) :: iR; - } -/* - case (CACHE(base, op, imm)) = - case (PREF(base, op, imm)) = -*/ - (SYNC) => { - iK = IK_barrier(Barrier_MIPS_SYNC); - } -/* - case (MFC0(rt, rd, sel, double)) - case (HCF) - case (MTC0(rt, rd, sel, double)) - case (TLBWI) - case (TLBWR) - case (TLBR) - case ((TLBP)) - case (RDHWR(rt, rd)) - case (ERET) -*/ - }; - (iR,oR,aR,Nias,Dia,ik) -} diff --git a/mips/mips_ri.sail b/mips/mips_ri.sail deleted file mode 100644 index edce0657..00000000 --- a/mips/mips_ri.sail +++ /dev/null @@ -1,42 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* mips_ri.sail: only use if want unknown instructions to throw - exception (like real hardware) instead of die (convenient for ppcmem) */ - -union clause ast = RI : unit -function clause decode _ = Some(RI()) -function clause execute (RI()) = - SignalException (ResI) - diff --git a/mips/mips_rmem.sail b/mips/mips_rmem.sail deleted file mode 100644 index 1bc47337..00000000 --- a/mips/mips_rmem.sail +++ /dev/null @@ -1,15 +0,0 @@ -/* These instructions are used for RMEM integration only */ - -/* Co-opt syscall 0xfffff for use as thread start in pccmem */ -union clause ast = SYSCALL_THREAD_START : unit -function clause decode (0b000000 @ 0xfffff @ 0b001100) = - Some(SYSCALL_THREAD_START()) -function clause execute (SYSCALL_THREAD_START()) = () - - -/* fake stop fetching instruction for ppcmem, execute doesn't do anything, - decode never produces it */ - -union clause ast = ImplementationDefinedStopFetching : unit -function clause execute (ImplementationDefinedStopFetching()) = () - diff --git a/mips/mips_tlb.sail b/mips/mips_tlb.sail deleted file mode 100644 index a8bb819e..00000000 --- a/mips/mips_tlb.sail +++ /dev/null @@ -1,140 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -val tlbEntryMatch : (bits(2), bits(27), bits(8), TLBEntry) -> bool effect pure -function tlbEntryMatch(r, vpn2, asid, entry) = - let entryValid = entry.valid() in - let entryR = entry.r() in - let entryMask = entry.pagemask() in - let entryVPN = entry.vpn2() in - let entryASID = entry.asid() in - let entryG = entry.g() in - let vpnMask : bits(27) = ~(zero_extend(entryMask)) in - (entryValid & - (r == entryR) & - ((vpn2 & vpnMask) == ((entryVPN) & vpnMask)) & - ((asid == (entryASID)) | (entryG))) - -val tlbSearch : bits(64) -> option(TLBIndexT) effect {rreg} -function tlbSearch(VAddr) = - let r = (VAddr[63..62]) in - let vpn2 = (VAddr[39..13]) in - let asid = TLBEntryHi.ASID() in { - foreach (idx from 0 to 63) { - if(tlbEntryMatch(r, vpn2, asid, reg_deref(TLBEntries[idx]))) then - return Some(to_bits(6, idx)) - }; - None() - } - -/** For given virtual address and accessType returns physical address and -bool flag indicating whether capability stores / loads are permitted for -page (depending on access type). */ - -val TLBTranslate2 : (bits(64), MemAccessType) -> (bits(64), bool) effect {rreg, wreg, undef, escape} -function TLBTranslate2 (vAddr, accessType) = { - let idx = tlbSearch(vAddr) in - match idx { - Some(idx) => - let i as atom(_) = unsigned(idx) in - let entry = reg_deref(TLBEntries[i]) in - let entryMask = entry.pagemask() in - let 'evenOddBit : range(12,28) = match (entryMask) { - 0x0000 => 12, - 0x0003 => 14, - 0x000f => 16, - 0x003f => 18, - 0x00ff => 20, - 0x03ff => 22, - 0x0fff => 24, - 0x3fff => 26, - 0xffff => 28, - _ => undefined - } in - let isOdd = (vAddr[evenOddBit]) in - let (caps : bits(1), capl : bits(1), pfn : bits(24), d : bits(1), v : bits(1)) = - if (isOdd) then - (entry.caps1(), entry.capl1(), entry.pfn1(), entry.d1(), entry.v1()) - else - (entry.caps0(), entry.capl0(), entry.pfn0(), entry.d0(), entry.v0()) in - if (~(v)) then - SignalExceptionTLB(if (accessType == StoreData) then XTLBInvS else XTLBInvL, vAddr) - else if ((accessType == StoreData) & ~(d)) then - SignalExceptionTLB(TLBMod, vAddr) - else - let res : bits(64) = zero_extend(pfn[23..(evenOddBit - 12)] @ vAddr[(evenOddBit - 1) .. 0]) in - (res, bits_to_bool(if (accessType == StoreData) then caps else capl)), - None() => SignalExceptionTLB( - if (accessType == StoreData) then XTLBRefillS else XTLBRefillL, vAddr) - } -} - -/* perform TLB translation. bool is CHERI specific TLB bits noStoreCap/suppressTag */ -val TLBTranslateC : (bits(64), MemAccessType) -> (bits(64), bool) effect {escape, rreg, undef, wreg} -function TLBTranslateC (vAddr, accessType) = - { - let currentAccessLevel = getAccessLevel() in - let compat32 = (vAddr[61..31] == 0b1111111111111111111111111111111) in - let (requiredLevel, addr) : (AccessLevel, option(bits(64))) = match (vAddr[63..62]) { - 0b11 => match (compat32, vAddr[30..29]) { /* xkseg */ - (true, 0b11) => (Kernel, None() : option(bits(64))), /* kseg3 mapped 32-bit compat */ - (true, 0b10) => (Supervisor, None() : option(bits(64))), /* sseg mapped 32-bit compat */ - (true, 0b01) => (Kernel, Some(0x00000000 @ 0b000 @ vAddr[28..0])), /* kseg1 unmapped uncached 32-bit compat */ - (true, 0b00) => (Kernel, Some(0x00000000 @ 0b000 @ vAddr[28..0])), /* kseg0 unmapped cached 32-bit compat */ - (_, _) => (Kernel, None() : option(bits(64))) /* xkseg mapped */ - }, - 0b10 => (Kernel, Some(0b00000 @ vAddr[58..0])), /* xkphys bits 61-59 are cache mode (ignored) */ - 0b01 => (Supervisor, None() : option(bits(64))), /* xsseg - supervisor mapped */ - 0b00 => (User, None() : option(bits(64))) /* xuseg - user mapped */ - } in - if not(grantsAccess(currentAccessLevel, requiredLevel)) then - SignalExceptionBadAddr(if (accessType == StoreData) then AdES else AdEL, vAddr) - else - let (pa, c) : (bits(64), bool) = match addr { - Some(a) => (a, false), - None() => if ((~(compat32)) & (unsigned(vAddr[61..0]) > MAX_VA)) then - SignalExceptionBadAddr(if (accessType == StoreData) then AdES else AdEL, vAddr) - else - TLBTranslate2(vAddr, accessType) - } - in if (unsigned(pa) > MAX_PA) then - SignalExceptionBadAddr(if (accessType == StoreData) then AdES else AdEL, vAddr) - else - (pa, c) - } - -/* TLB translate function for MIPS (throws away capability flag) */ -val TLBTranslate : (bits(64), MemAccessType) -> bits(64) effect {rreg, wreg, escape, undef} -function TLBTranslate (vAddr, accessType) = - let (addr, c) = TLBTranslateC(vAddr, accessType) in addr diff --git a/mips/mips_tlb_stub.sail b/mips/mips_tlb_stub.sail deleted file mode 100644 index c42e4764..00000000 --- a/mips/mips_tlb_stub.sail +++ /dev/null @@ -1,48 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -$ifndef _MIPS_TLB_STUB -$define _MIPS_TLB_STUB - -val tlbEntryMatch : (bits(2), bits(27), bits(8), TLBEntry) -> bool effect pure -function tlbSearch(VAddr) : bits(64) -> option(TLBIndexT) = None() - -val TLBTranslate2 : (bits(64), MemAccessType) -> (bits(64), bool) effect pure -function TLBTranslate (vAddr, accessType) : (bits(64), MemAccessType) -> bits(64) = - vAddr - -val TLBTranslateC : (bits(64), MemAccessType) -> (bits(64), bool) effect pure -function TLBTranslateC (vAddr, accessType) : (bits(64), MemAccessType) -> (bits(64), bool) = (vAddr, false) - -$endif diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail deleted file mode 100644 index 43e759b9..00000000 --- a/mips/mips_wrappers.sail +++ /dev/null @@ -1,90 +0,0 @@ -/*========================================================================*/ -/* */ -/* Copyright (c) 2015-2017 Robert M. Norton */ -/* Copyright (c) 2015-2017 Kathyrn Gray */ -/* All rights reserved. */ -/* */ -/* This software was developed by the University of Cambridge Computer */ -/* Laboratory as part of the Rigorous Engineering of Mainstream Systems */ -/* (REMS) project, funded by EPSRC grant EP/K008528/1. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ -/*========================================================================*/ - -/* mips_wrappers.sail: wrappers functions and hooks for CHERI extensibility - (mostly identity functions here) */ - -val MEMw_wrapper : forall 'n, 1 <= 'n <= 8. (bits(64), atom('n), bits(8 * 'n)) -> unit effect {eamem, wmv, wreg} - -function MEMw_wrapper(addr, size, data) = - let ledata = reverse_endianness(data) in - if (addr == 0x000000007f000000) then - { - UART_WDATA = ledata[7..0]; - UART_WRITTEN = bitone; - } else { - MEMea(addr, size); - MEMval(addr, size, ledata); - } - -val MEMw_conditional_wrapper : forall 'n, 1 <= 'n <= 8. (bits(64), atom('n), bits(8 * 'n)) -> bool effect {eamem, wmv} - -function MEMw_conditional_wrapper(addr, size, data) = - { - MEMea_conditional(addr, size); - MEMval_conditional(addr, size, reverse_endianness(data)) - } - -val addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) -function addrWrapper(addr, accessType, width) = - addr - -val addrWrapperUnaligned : (bits(64), MemAccessType, WordTypeUnaligned) -> bits(64) -function addrWrapperUnaligned(addr, accessType, width) = - addr - -$ifdef _MIPS_TLB_STUB -val TranslatePC : bits(64) -> bits(64) effect {rreg, wreg, escape} -$else -val TranslatePC : bits(64) -> bits(64) effect {rreg, wreg, escape, undef} -$endif - -function TranslatePC (vAddr) = { - incrementCP0Count(); - if (vAddr[1..0] != 0b00) then /* bad PC alignment */ - (SignalExceptionBadAddr(AdEL, vAddr)) - else - TLBTranslate(vAddr, Instruction) -} - -let have_cp2 = false - -function SignalException (ex) = SignalExceptionMIPS(ex, 0x0000000000000000) - -val ERETHook : unit -> unit -function ERETHook() = () - -function init_cp2_state () = skip_wreg() -function cp2_next_pc() = {skip_wreg(); skip_rreg()} -function dump_cp2_state () = {skip_rreg(); skip_escape();} diff --git a/mips/prelude.sail b/mips/prelude.sail deleted file mode 100644 index 094f82e8..00000000 --- a/mips/prelude.sail +++ /dev/null @@ -1,223 +0,0 @@ -default Order dec - -val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg} -/* sneaky deref with no effect necessary for bitfield writes */ -val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a - -/* this is here because if we don't have it before including vector_dec - we get infinite loops caused by interaction with bool/bit casts */ -val eq_bit2 = "eq_bit" : (bit, bit) -> bool -overload operator == = {eq_bit2} - -$include <smt.sail> -$include <flow.sail> -$include <arith.sail> -$include <option.sail> -$include <vector_dec.sail> - -val eq_anything = {ocaml: "(fun (x, y) -> x = y)", lem: "eq", coq: "generic_eq", _:"eq_anything"} : forall ('a : Type). ('a, 'a) -> bool -overload operator == = {eq_anything} - -val not_vec = {c:"not_bits", _:"not_vec"} : forall 'n. bits('n) -> bits('n) - -overload ~ = {not_bool, not_vec} - -val not = {coq:"negb", _:"not"} : bool -> bool - -val neq_vec = {lem: "neq"} : forall 'n. (bits('n), bits('n)) -> bool -function neq_vec (x, y) = not_bool(eq_bits(x, y)) - -val neq_anything = {lem: "neq", coq: "generic_neq"} : forall ('a : Type). ('a, 'a) -> bool -function neq_anything (x, y) = not_bool(x == y) - -overload operator != = {neq_atom, neq_int, neq_vec, neq_anything} - -val and_bits = {c:"and_bits", _: "and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -overload operator & = {and_bool, and_bits} - -val or_bits = {c: "or_bits", _: "or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -overload operator | = {or_bool, or_bits} - -val cast cast_unit_vec : bit -> bits(1) - -function cast_unit_vec b = match b { - bitzero => 0b0, - _ => 0b1 -} - -val print = "print_endline" : string -> unit - -val "prerr_endline" : string -> unit - -val "prerr_string" : string -> unit - -val putchar = {c:"sail_putchar", _:"putchar"} : int -> unit - -val concat_str = {lem: "stringAppend", coq: "String.append", _: "concat_str"} : (string, string) -> string - -val string_of_int = "string_of_int" : int -> string -/* Unused? -val DecStr : int -> string - -val HexStr : int -> string -*/ -val BitStr = "string_of_bits" : forall 'n. bits('n) -> string - -val xor_vec = {c: "xor_bits" , _: "xor_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -val int_power = {ocaml: "int_power", lem: "pow", coq: "Z.pow"} : (int, int) -> int - -overload operator ^ = {xor_vec, int_power} - -val add_range = {ocaml: "add_int", lem: "integerAdd", coq: "add_range", c: "add_int"} : forall 'n 'm 'o 'p. - (range('n, 'm), range('o, 'p)) -> range('n + 'o, 'm + 'p) - -val add_vec = "add_vec" : forall 'n. (bits('n), bits('n)) -> bits('n) - -val add_vec_int = "add_vec_int" : forall 'n. (bits('n), int) -> bits('n) - -overload operator + = {add_range, add_int, add_vec, add_vec_int} - -val sub_range = {ocaml: "sub_int", lem: "integerMinus", coq: "sub_range"} : forall 'n 'm 'o 'p. - (range('n, 'm), range('o, 'p)) -> range('n - 'p, 'm - 'o) - -val sub_vec = {c : "sub_bits", _:"sub_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) - -val sub_vec_int = {c:"sub_bits_int", _: "sub_vec_int"} : forall 'n. (bits('n), int) -> bits('n) - -val negate_range = {ocaml: "minus_big_int", lem: "integerNegate", coq: "negate_range"} : forall 'n 'm. range('n, 'm) -> range(- 'm, - 'n) - -overload operator - = {sub_range, sub_int, sub_vec, sub_vec_int} - -overload negate = {negate_range, negate_int} - -overload operator * = {mult_int} - -val quotient_nat = {ocaml: "quotient", lem: "integerDiv", coq: "Z.div"} : (nat, nat) -> nat - -val quotient = {ocaml: "quotient", lem: "integerDiv", coq: "Z.mod"} : (int, int) -> int - -overload operator / = {quotient_nat, quotient} - -val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot", coq: "Z.quot", _ : "tdiv_int"} : (int, int) -> int -val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod", coq: "Z.rem", _ : "tmod_int"} : (int, int) -> int - -val modulus = {ocaml: "modulus", lem: "hardware_mod", coq: "euclid_modulo", _ : "tmod_int"} : forall 'n, 'n > 0 . (int, atom('n)) -> range(0, 'n - 1) - -overload operator % = {modulus} - -val min_nat = {lem: "min", coq: "Z.min", _: "min_int"} : (nat, nat) -> nat - -val min_int = {lem: "min", coq: "Z.min", _: "min_int"} : (int, int) -> int - -val max_nat = {lem: "max", coq: "Z.max", _: "max_int"} : (nat, nat) -> nat - -val max_int = {lem: "max", coq: "Z.max", _: "max_int"} : (int, int) -> int - -val min_atom = {ocaml: "min_int", lem: "min", coq: "min_atom", c:"min_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c <= 'a & 'c <= 'b . atom('c)} - -val max_atom = {ocaml: "max_int", lem: "max", coq: "max_atom", c:"max_int"} : forall 'a 'b . (atom('a), atom('b)) -> {'c, ('c = 'a | 'c = 'b) & 'c >= 'a & 'c >= 'b . atom('c)} - -overload min = {min_atom, min_nat, min_int} - -overload max = {max_atom, max_nat, max_int} - -val __WriteRAM = "write_ram" : forall 'n 'm. - (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> bool effect {wmv} - -val __MIPS_write : forall 'n. (bits(64), atom('n), bits(8 * 'n)) -> unit effect {wmv} -function __MIPS_write (addr, width, data) = let _ = __WriteRAM(64, width, 0x0000_0000_0000_0000, addr, data) in () - -val __ReadRAM = "read_ram" : forall 'n 'm, 'n >= 0. - (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem} - -val __MIPS_read : forall 'n, 'n >= 0. (bits(64), atom('n)) -> bits(8 * 'n) effect {rmem} -function __MIPS_read (addr, width) = __ReadRAM(64, width, 0x0000_0000_0000_0000, addr) - -infix 8 ^^ -val operator ^^ = {lem: "replicate_bits"} : forall 'n 'm, 'm >= 0 . (bits('n), atom('m)) -> bits('n * 'm) -function operator ^^ (bs, n) = replicate_bits (bs, n) - -val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n) - -union exception = { - ISAException : unit, - Error_not_implemented : string, - Error_misaligned_access : unit, - Error_EBREAK : unit, - Error_internal_error : unit -} - -val mips_sign_extend : forall 'n 'm , 'm >= 'n . bits('n) -> bits('m) -val mips_zero_extend : forall 'n 'm , 'm >= 'n . bits('n) -> bits('m) - -function mips_sign_extend v = sail_sign_extend(v, sizeof('m)) -function mips_zero_extend v = sail_zero_extend(v, sizeof('m)) - -overload sign_extend = {mips_sign_extend} -overload zero_extend = {mips_zero_extend} - -val zeros : forall 'n, 'n >= 0 . unit -> bits('n) -function zeros() = replicate_bits (0b0,'n) - -val ones : forall 'n, 'n >= 0 . unit -> bits('n) -function ones() = replicate_bits (0b1,'n) - -infix 4 <_s -infix 4 >=_s -infix 4 <_u -infix 4 >=_u - -val operator <_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool -val operator >=_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool -val operator <_u : forall 'n, 'n >= 0. (bits('n), bits('n)) -> bool -val operator >=_u : forall 'n, 'n >= 0. (bits('n), bits('n)) -> bool - -function operator <_s (x, y) = signed(x) < signed(y) -function operator >=_s (x, y) = signed(x) >= signed(y) -function operator <_u (x, y) = unsigned(x) < unsigned(y) -function operator >=_u (x, y) = unsigned(x) >= unsigned(y) - -val cast bool_to_bits : bool -> bits(1) -function bool_to_bits x = if x then 0b1 else 0b0 - -val cast bit_to_bool : bit -> bool -function bit_to_bool b = match b { - bitone => true, - _ => false -} - -val cast bits_to_bool : bits(1) -> bool -function bits_to_bool x = bit_to_bool(x[0]) - -infix 1 >> -infix 1 << -infix 1 >>_s - -val "shift_bits_right" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) effect {undef} -val "shift_bits_left" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) effect {undef} - -val "shiftl" : forall 'm 'n, 'n >= 0. (bits('m), atom('n)) -> bits('m) -val "shiftr" : forall 'm 'n, 'n >= 0. (bits('m), atom('n)) -> bits('m) - -overload operator >> = {shift_bits_right, shiftr} -overload operator << = {shift_bits_left, shiftl} -val operator >>_s = "shift_bits_right_arith" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) effect {undef} - -infix 7 *_s -val operator *_s = "mults_vec" : forall 'n . (bits('n), bits('n)) -> bits(2 * 'n) -infix 7 *_u -val operator *_u = "mult_vec" : forall 'n . (bits('n), bits('n)) -> bits(2 * 'n) - -/*! -\function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. -*/ -val to_bits : forall 'l, 'l >= 0 .(atom('l), int) -> bits('l) -function to_bits (l, n) = get_slice_int(l, n, 0) - -val mask : forall 'm 'n , 'm >= 'n > 0 . bits('m) -> bits('n) -function mask bs = bs['n - 1 .. 0] - -val "get_time_ns" : unit -> int diff --git a/mips/sim.dts b/mips/sim.dts deleted file mode 100644 index d1720441..00000000 --- a/mips/sim.dts +++ /dev/null @@ -1,79 +0,0 @@ -/dts-v1/; -/ { - model = "SRI/Cambridge BERI simulation"; - compatible = "sri-cambridge,beri-sim"; - #address-cells = <1>; - #size-cells = <1>; - sri-cambridge,build-time = <0 1527247299>; - sri-cambridge,build-host = "TODO"; - sri-cambridge,build-path = "TODO"; - sri-cambridge,build-source-path = "TODO"; - sri-cambridge,build-source-revision = "TODO"; - - cpus { - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - enable-method = "spin-table"; - - cpu@0 { - device-type = "cpu"; - compatible = "sri-cambridge,beri"; - - reg = <0 1>; - status = "okay"; - }; - }; - - cpuintc: cpuintc@0 { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - /* THE PIC IS A LIE! - FreeBSD panics if there isn't one even though - we don't actually need one if we put the UART - in polled mode. We can get away with just pointing - FreeBSD at some plain memory and telling it that - is a PIC... */ - beripic0: beripic@7f804000 { - compatible = "sri-cambridge,beri-pic"; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0x7f804000 0x400 - 0x7f806000 0x10 - 0x7f806080 0x10 - 0x7f806100 0x10>; - interrupts = < 2 3 4 5 6 >; - hard-interrupt-sources = <64>; - soft-interrupt-sources = <64>; - interrupt-parent = <&cpuintc>; - }; - soc { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <1>; - - compatible = "simple-bus", "mips,mips4k"; - ranges; - - memory { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - serial@7f000000 { - compatible = "altera,jtag_uart-11_0"; - reg = <0x7f000000 0x40>; - /* Removing these two lines puts the UART - in polled mode which is necessary because - we don't have a PIC or a UART capable of - generating interrupts. Fortunately FreeBSD - copes. - interrupts = <0>; - interrupt-parent = <&beripic0>;*/ - }; - }; -}; diff --git a/test/run_tests.sh b/test/run_tests.sh index 336a70f9..5e6fe691 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -46,9 +46,3 @@ printf "RISCV spec tests\n" printf "==========================================\n" ./riscv/run_tests.sh - -printf "\n==========================================\n" -printf "CHERI spec tests\n" -printf "==========================================\n" - -./cheri/run_tests.sh |