sail/riscv, branch sail2

More cleanup

2020-07-31T12:37:17+00:00

Merge branch 'sail2' into rmem_interpreter

2018-12-28T15:12:00+00:00

RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it and tests.

2018-12-20T13:49:49+00:00

Add hooks to call cgen stub file for RISC-V

2018-12-13T16:20:48+00:00

Fix all tests with type checking changes

2018-12-11T19:54:57+00:00

RISC-V: update the riscv/readme to point to the new repository.

2018-11-30T18:29:04+00:00

RISC-V: more tidying up of the Spike interface.

2018-11-30T01:45:34+00:00

RISC-V: implement WFI in the platform model.

2018-11-29T17:52:36+00:00

The initial implementation tries to optimize for simulator execution, especially for OS boots.

RISC-V: factor the execution trace.

2018-11-29T17:52:36+00:00

This is now split into instructions, regs, memory and platform, each
controlled individually.  Currently all are enabled and not connected to
any command-line options, so a recompile is needed for trace tuning.

RISC-V: no ldu for rv64i

2018-11-29T17:38:12+00:00