sail/riscv/Makefile, branch sail2 Formal specification language for ISAs RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it and tests. 2018-12-20T13:49:49+00:00 Robert Norton 2018-12-20T13:49:39+00:00 d99dd3833e8ebf89c586cc5316582a3c62ad7997 






Add hooks to call cgen stub file for RISC-V
2018-12-13T16:20:48+00:00

Alasdair Armstrong

2018-12-13T16:20:48+00:00

b167a59affdb6428fa0656a092b335a3a6899d56












Fix all tests with type checking changes
2018-12-11T19:54:57+00:00

Alasdair Armstrong

2018-12-11T19:54:14+00:00

ab4b9ca4f7cab45b6a2a13d0ef125dcf9c276a06












RISC-V: more tidying up of the Spike interface.
2018-11-30T01:45:34+00:00

Prashanth Mundkur

2018-11-30T01:45:34+00:00

c87a2b9cbdac1df22d38f82fd8314fe4acdfb6c9












Add RVFI DII version of the RISC-V simulator for TestRIG
2018-11-12T16:10:04+00:00

Brian Campbell

2018-11-12T16:10:04+00:00

4d652c426f57e5255ef8c1d828c53abcbb69d722

The new riscv_rvfi target should still be usable as a normal simulator,
but also has extra registers in the model for the RVFI DII protocol and
code to update them, and the driver has a -r option to enable RVFI mode.





The new riscv_rvfi target should still be usable as a normal simulator,
but also has extra registers in the model for the RVFI DII protocol and
code to update them, and the driver has a -r option to enable RVFI mode.







RISC-V: separate jalr execute clause for seq model and rmem.
2018-10-23T22:45:09+00:00

Prashanth Mundkur

2018-10-23T21:00:31+00:00

852929bb8b47993bcb642ada41802383a308c9c2












RISC-V: Initial splitting of instructions across multiple files.
2018-10-23T22:45:09+00:00

Prashanth Mundkur

2018-10-23T20:07:47+00:00

578877f6080d4026ce863c863e3db7bcb230e28b












RISC-V: Allow Spike linkage to be conditionally enabled.
2018-10-23T22:32:15+00:00

Prashanth Mundkur

2018-09-19T00:17:36+00:00

a665e2160692e509b75966ceb96b8eb3a84a8375












RISC-V: An initial C Sail model linked against Spike for testing.
2018-10-23T22:32:15+00:00

Prashanth Mundkur

2018-09-11T01:51:19+00:00

a6842cd2393827a3d3263079313c988b2ce116df












RISC-V: Refactor c platform bits.
2018-10-23T22:32:15+00:00

Prashanth Mundkur

2018-09-10T19:16:42+00:00

2cef8d0c31a09ea4fac9a48faff882dde4e98641