sail/risc-v, branch sail2 Formal specification language for ISAs Updates to interpreter 2018-01-03T15:46:23+00:00 Alasdair Armstrong 2018-01-03T15:46:23+00:00 90ca4e03c240675b1830a5e48cea5f6c9e412b2a Experimenting with porting riscv model to new typechecker 
Experimenting with porting riscv model to new typechecker
renamed hgen to gen 2017-12-04T14:47:38+00:00 Shaked Flur 2017-12-04T14:47:38+00:00 748318f8af7b82a01bb151f1bfcb466d0fc8291f 






match what rmem (ppcmem2) expects from ISA Makefiles
2017-11-30T15:40:43+00:00

Shaked Flur

2017-11-30T15:40:43+00:00

9e1309ab7c1a137324c88c272c5a76c4c8bce016












renaming
2017-11-23T15:50:13+00:00

Shaked Flur

2017-11-23T15:50:13+00:00

16c269d6f26fd69d8788c448b87f4bb479a6ef66












added RISCV_ prefix to some values to stop Lem from renaming them
2017-11-23T13:32:42+00:00

Shaked Flur

2017-11-23T13:32:42+00:00

9ab1c6514c38968bcbdf5847ecb811072f731982












RISC-V parser checks
2017-11-07T11:45:06+00:00

Shaked Flur

2017-11-07T11:45:06+00:00

6b86efcb6e1042d4933b67eaf3a7b3eff1fac256












added RISC-V "fence r,r"
2017-11-01T14:17:08+00:00

Shaked Flur

2017-11-01T14:17:08+00:00

8e5d44d17c71cf946e65e15de8df42de2af4c652












fixed release acquire semantics of AMOs
2017-10-26T10:40:35+00:00

Shaked Flur

2017-10-26T10:40:35+00:00

dc62ae8cf283cdf71c0cd2001d57abc77bc52673












fixed JALR: do the register write first to allow po-later reads
2017-10-01T11:02:07+00:00

Shaked Flur

2017-10-01T11:02:07+00:00

fcf8270b4f46b4cd92534807292694bfd6d14457












fixed the RISC-V Makefile
2017-09-27T13:34:18+00:00

Shaked Flur

2017-09-27T13:34:18+00:00

4c0d3acebf8fd37b3ef1481ac282f5c47464310f