// Testbench for CPU components

`timescale 1ms/1ms


module tb;
   wire clk, reset;
   reg [4:0] read1;
   reg [4:0] read2; 
   wire [63:0] val1;
   wire [63:0] val2;   
   reg [4:0]   write;
   reg [63:0]  write_data;
   reg 	       write_en;

   regs r
     (.clk(clk), .reset(reset), 
      .reg_read1(read1), .reg_read2(read2),
      .reg_write(write), .write_data(write_data), .write_en(write_en),
      .reg_read1_out(val1), .reg_read2_out(val2)
      );     
   
   initial begin;
      #100;
      read1 = 1;
      read2 = 2;
      $display("%d %d", val1[31:0], val2[31:0]);      
      #200;
      write = 1;
      write_data = 10;
      write_en = 1;
      #250;      
      write_en = 0;      
      #300;
      write = 2;
      write_data = 20;
      write_en = 1;
      #350;
      write_en = 0;
      #400;
      read1 = 3;
      read2 = 4;
      #450
	read1 = 1;
      read2 = 2;
      $display("%d %d", val1[31:0], val2[31:0]);
      #500;
      $stop;	
   end
   
   
endmodule // regs_tb