`timescale 1ms/1ms

module regs(
	    input wire 	      clk, reset,
	    input wire [4:0]  reg_read1, [4:0] reg_read2,
	    input wire [4:0]  reg_write,
	    input wire [63:0] write_data,
	    input wire 	      write_en,
	    output reg [63:0] reg_read1_out, 
	    output reg [63:0] reg_read2_out
	    );
   
   reg [63:0] 		      reg_array [31:0];  // 2D array of all regs, including pc
   
   function write_reg;
      input reg [4:0] 	      regid;
      input reg [63:0] 	      data;
      begin
	 // if (regid > 0 || regid <= 32)  // Must not write <x0 and x32>
	 reg_array[regid] = data;	 
     	 write_reg = 1;
      end
   endfunction // write_reg

   function [63:0] read_reg;
      input reg [4:0] regid;
      begin
	 read_reg = reg_array[regid];
      end
   endfunction // read_reg

   always @(write_en) begin
      write_reg(reg_write, write_data);
   end
   
   always @* begin
      assign reg_read1_out = read_reg(reg_read1);
      assign reg_read2_out = read_reg(reg_read2);     
   end
   
   
endmodule // regs