module alu(
	   input wire [3:0]  op,
	   input wire [63:0] in_x,
	   input wire [63:0] in_y,
	   output reg [63:0] out
	   );

   always @* begin
      case (op)
	4'b0000: out = in_x & in_y;                     // and
	4'b0001: out = in_x | in_y;                     // or
	4'b0010: out = in_x + in_y;                     // add
	4'b0011: out = in_x - in_y;                     // sub
	4'b0100: out = $signed(in_x) >>> $signed(in_y); // sra signed
	4'b0101: out = in_x < in_y;                     // stlu
	4'b0110: out = in_x ^ in_y;                     // xor
	4'b0111: out = in_x >> in_y;                    // srl
	4'b1000: out = $signed(in_x) < $signed(in_y);   // slt signed
	4'b1001: out = in_x << in_y;                    // sll
	4'b1010: out = ~(in_x | in_y);                  // nor
	4'b1011: out = $signed(in_x) >= $signed(in_y);  // sge
	4'b1100: out = in_x >= in_y;                    // sgeu
	4'b1101: out = in_x == in_y;                    // seq
	4'b1110: out = in_x != in_y;                    // sne
	4'b1111: out = 0;                               // invalid
      endcase
   end // always @ *
   
endmodule // alu