From 0dbd928ceefed09d65276211c70d0137b4734011 Mon Sep 17 00:00:00 2001
From: Paul Sokolovsky
Date: Sat, 24 Oct 2015 02:26:10 +0300
Subject: Makefiles: Remove duplicate object files when linking.

Scenario: module1 depends on some common file from lib/, so specifies it
in its SRC_MOD, and the same situation with module2, then common file
from lib/ eventually ends up listed twice in $(OBJ), which leads to link
errors.

Make is equipped to deal with such situation easily, quoting the manual:
"The value of $^ omits duplicate prerequisites, while $+ retains them and
preserves their order." So, just use $^ consistently in all link targets.
---
 stmhal/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'stmhal')

diff --git a/stmhal/Makefile b/stmhal/Makefile
index e50bf3b0f..222e19b32 100644
--- a/stmhal/Makefile
+++ b/stmhal/Makefile
@@ -285,7 +285,7 @@ $(BUILD)/firmware.hex: $(BUILD)/firmware.elf
 
 $(BUILD)/firmware.elf: $(OBJ)
 	$(ECHO) "LINK $@"
-	$(Q)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
+	$(Q)$(LD) $(LDFLAGS) -o $@ $^ $(LIBS)
 	$(Q)$(SIZE) $@
 
 MAKE_PINS = boards/make-pins.py
-- 
cgit v1.2.3