From b9741cd8f84a2f49e3ea00382bfa71d994bc83ff Mon Sep 17 00:00:00 2001
From: Rami Ali
Date: Mon, 5 Dec 2016 17:04:56 +1100
Subject: stmhal/hal: Update ST32CubeF7 HAL files to V1.1.2.
These files originate from the STM32Cube_FW_F7_V1.5.0 software package
from ST. Newlines are unixified and trailing whitespace is removed.
---
stmhal/hal/f7/src/stm32f7xx_hal.c | 54 +-
stmhal/hal/f7/src/stm32f7xx_hal_adc.c | 758 ++++--
stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c | 571 ++--
stmhal/hal/f7/src/stm32f7xx_hal_can.c | 431 ++-
stmhal/hal/f7/src/stm32f7xx_hal_cortex.c | 46 +-
stmhal/hal/f7/src/stm32f7xx_hal_dac.c | 24 +-
stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c | 18 +-
stmhal/hal/f7/src/stm32f7xx_hal_dma.c | 1025 ++++---
stmhal/hal/f7/src/stm32f7xx_hal_flash.c | 65 +-
stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c | 463 +++-
stmhal/hal/f7/src/stm32f7xx_hal_gpio.c | 27 +-
stmhal/hal/f7/src/stm32f7xx_hal_i2c.c | 3984 ++++++++++++++++------------
stmhal/hal/f7/src/stm32f7xx_hal_i2s.c | 31 +-
stmhal/hal/f7/src/stm32f7xx_hal_pcd.c | 199 +-
stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c | 24 +-
stmhal/hal/f7/src/stm32f7xx_hal_pwr.c | 14 +-
stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c | 14 +-
stmhal/hal/f7/src/stm32f7xx_hal_rcc.c | 268 +-
stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c | 249 +-
stmhal/hal/f7/src/stm32f7xx_hal_rng.c | 18 +-
stmhal/hal/f7/src/stm32f7xx_hal_rtc.c | 24 +-
stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c | 46 +-
stmhal/hal/f7/src/stm32f7xx_hal_sd.c | 254 +-
stmhal/hal/f7/src/stm32f7xx_hal_spi.c | 2888 +++++++++++++-------
stmhal/hal/f7/src/stm32f7xx_hal_tim.c | 100 +-
stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c | 119 +-
stmhal/hal/f7/src/stm32f7xx_hal_uart.c | 1072 +++++---
stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c | 9 +-
stmhal/hal/f7/src/stm32f7xx_ll_usb.c | 72 +-
29 files changed, 8159 insertions(+), 4708 deletions(-)
(limited to 'stmhal/hal/f7/src')
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal.c b/stmhal/hal/f7/src/stm32f7xx_hal.c
index b92d22e6c..a790e7a85 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -68,11 +68,11 @@
* @{
*/
/**
- * @brief STM32F7xx HAL Driver version number V1.0.1
+ * @brief STM32F7xx HAL Driver version number V1.1.2
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@@ -242,7 +242,7 @@ __weak void HAL_MspDeInit(void)
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+ HAL_SYSTICK_Config(SystemCoreClock/1000);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
@@ -309,7 +309,7 @@ __weak uint32_t HAL_GetTick(void)
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
- * @note ThiS function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
@@ -327,7 +327,7 @@ __weak void HAL_Delay(__IO uint32_t Delay)
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
@@ -343,7 +343,7 @@ __weak void HAL_SuspendTick(void)
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
@@ -370,7 +370,7 @@ uint32_t HAL_GetHalVersion(void)
*/
uint32_t HAL_GetREVID(void)
{
- return((DBGMCU->IDCODE) >> 16);
+ return((DBGMCU->IDCODE) >> 16U);
}
/**
@@ -485,6 +485,38 @@ void HAL_DisableFMCMemorySwapping(void)
SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
}
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+/**
+* @brief Enable the Internal FLASH Bank Swapping.
+*
+* @note This function can be used only for STM32F77xx/STM32F76xx devices.
+*
+* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
+* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))
+*
+* @retval None
+*/
+void HAL_EnableMemorySwappingBank(void)
+{
+ SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
+}
+
+/**
+* @brief Disable the Internal FLASH Bank Swapping.
+*
+* @note This function can be used only for STM32F77xx/STM32F76xx devices.
+*
+* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
+* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM))
+*
+* @retval None
+*/
+void HAL_DisableMemorySwappingBank(void)
+{
+ CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
+}
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
/**
* @}
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_adc.c b/stmhal/hal/f7/src/stm32f7xx_hal_adc.c
index 0c5f83b20..b8da090f0 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_adc.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@@ -164,7 +164,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -258,10 +258,12 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
/* Check ADC handle */
if(hadc == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
@@ -284,29 +286,45 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
if(hadc->State == HAL_ADC_STATE_RESET)
{
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
}
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
- /* Set ADC parameters */
- ADC_Init(hadc);
+ /* Set ADC parameters */
+ ADC_Init(hadc);
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
/* Release Lock */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -317,29 +335,43 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
/* Check ADC handle */
if(hadc == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
- /* DeInit the low level hardware */
- HAL_ADC_MspDeInit(hadc);
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed. */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* DeInit the low level hardware */
+ HAL_ADC_MspDeInit(hadc);
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_RESET;
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -350,6 +382,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_MspInit could be implemented in the user file
*/
@@ -363,6 +397,8 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_MspDeInit could be implemented in the user file
*/
@@ -409,18 +445,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if an injected conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
- }
-
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -437,26 +462,62 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
- }
- else
- {
- /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* Enable the selected ADC software conversion for regular group */
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
}
}
@@ -476,11 +537,27 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
- /* Disable the Peripheral */
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
@@ -488,6 +565,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
/**
* @brief Poll for regular conversion complete
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function.
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param Timeout: Timeout value in millisecond.
@@ -507,7 +592,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -521,29 +606,46 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
{
- /* Check for the Timeout */
+ /* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
{
- hadc->State= HAL_ADC_STATE_TIMEOUT;
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
/* Process unlocked */
__HAL_UNLOCK(hadc);
+
return HAL_TIMEOUT;
}
}
}
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
/* Return ADC state */
@@ -566,6 +668,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
uint32_t tickstart = 0;
/* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EVENT_TYPE(EventType));
/* Get tick */
@@ -577,32 +680,38 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
{
- hadc->State= HAL_ADC_STATE_TIMEOUT;
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
/* Process unlocked */
__HAL_UNLOCK(hadc);
+
return HAL_TIMEOUT;
}
}
}
- /* Check analog watchdog flag */
+ /* Analog watchdog (level out of window) event */
if(EventType == ADC_AWD_EVENT)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
- /* Clear the ADCx's analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
}
+ /* Overrun event */
else
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- /* Clear the ADCx's Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
/* Return ADC state */
@@ -627,21 +736,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if an injected conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
- }
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
-
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -658,32 +753,65 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
}
}
- /* Enable the ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
- /* Enable the ADC end of conversion interrupt for regular group */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
- {
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+ /* Enable end of conversion interrupt for regular group */
+ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
}
- }
- else
- {
- /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
- if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ else
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
}
}
@@ -702,17 +830,30 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
{
- /* Disable the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Disable the ADC end of conversion interrupt for injected group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+ /* Process locked */
+ __HAL_LOCK(hadc);
- /* Enable the Peripheral */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
@@ -738,55 +879,44 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check End of conversion flag for regular channels */
if(tmp1 && tmp2)
{
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
}
- if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
{
- if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
- {
- /* DISABLE the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
- /* DISABLE the ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- }
- else
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
- if (hadc->NbrOfCurrentConversionRank == 0)
- {
- hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
- }
-
- /* Decrement the number of conversion when an interrupt occurs */
- hadc->NbrOfCurrentConversionRank--;
-
- /* Check if all conversions are finished */
- if(hadc->NbrOfCurrentConversionRank == 0)
- {
- /* DISABLE the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-
- /* DISABLE the ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- }
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
- /* Clear the ADCx flag for regular end of conversion */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
@@ -794,31 +924,41 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check End of conversion flag for injected channels */
if(tmp1 && tmp2)
{
- /* Check if a regular conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_REG)
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
}
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2)
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, scan sequence on going or by automatic injected */
+ /* conversion from group regular (same conditions as group regular */
+ /* interruption disabling above). */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE))))
{
- /* DISABLE the ADC end of conversion interrupt for injected group */
+ /* Disable ADC end of single conversion interrupt on group injected */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
/* Conversion complete callback */
HAL_ADCEx_InjectedConvCpltCallback(hadc);
- /* Clear the ADCx flag for injected end of conversion */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
@@ -826,14 +966,17 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check Analog watchdog flag */
if(tmp1 && tmp2)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
- /* Clear the ADCx's Analog watchdog flag */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
+ /* Level out of window callback */
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
- /* Level out of window callback */
- HAL_ADC_LevelOutOfWindowCallback(hadc);
+ /* Clear the ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
+ }
}
tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
@@ -841,17 +984,21 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check Overrun flag */
if(tmp1 && tmp2)
{
- /* Change ADC state to overrun state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ /* Note: On STM32F7, ADC overrun can be set through other parameters */
+ /* refer to description of parameter "EOCSelection" for more */
+ /* details. */
/* Set ADC error code to overrun */
- hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- /* Clear the Overrun flag */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
/* Error callback */
HAL_ADC_ErrorCallback(hadc);
+
+ /* Clear the Overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
}
@@ -874,30 +1021,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Process locked */
__HAL_LOCK(hadc);
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- /* Enable ADC DMA mode */
- hadc->Instance->CR2 |= ADC_CR2_DMA;
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -914,11 +1038,85 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
}
}
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= ADC_CR2_SWSTART;
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode */
+ hadc->Instance->CR2 |= ADC_CR2_DMA;
+
+ /* Start the DMA channel */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ {
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
+ else
+ {
+ /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
}
/* Return function status */
@@ -933,23 +1131,42 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
- /* Disable the Peripheral */
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable the selected ADC DMA mode */
+ hadc->Instance->CR2 &= ~ADC_CR2_DMA;
- /* Disable the selected ADC DMA mode */
- hadc->Instance->CR2 &= ~ADC_CR2_DMA;
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
- /* Disable the ADC DMA Stream */
- HAL_DMA_Abort(hadc->DMA_Handle);
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -972,6 +1189,8 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_ConvCpltCallback could be implemented in the user file
*/
@@ -985,6 +1204,8 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
*/
@@ -998,6 +1219,8 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
*/
@@ -1005,12 +1228,20 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
/**
* @brief Error ADC callback.
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_ErrorCallback could be implemented in the user file
*/
@@ -1057,14 +1288,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Process locked */
__HAL_LOCK(hadc);
- /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
- if (sConfig->Channel > ADC_CHANNEL_9)
- {
- /* Clear the old sample time */
- hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
-
- /* Set the new sample time */
- hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+ /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+ if (sConfig->Channel > ADC_CHANNEL_9)
+ {
+ /* Clear the old sample time */
+ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
+
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ /* Set the new sample time */
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
+ }
+ else
+ {
+ /* Set the new sample time */
+ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
+ }
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
@@ -1110,13 +1349,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
ADC->CCR |= ADC_CCR_VBATE;
}
- /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
+ /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
- if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
+ if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
@@ -1137,6 +1376,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/**
* @brief Configures the analog watchdog.
+ * @note Analog watchdog thresholds can be modified while ADC conversion
+ * is on going.
+ * In this case, some constraints must be taken into account:
+ * the programmed threshold values are effective from the next
+ * ADC EOC (end of unitary conversion).
+ * Considering that registers write delay may happen due to
+ * bus activity, this might cause an uncertainty on the
+ * effective timing of the new programmed threshold values.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
@@ -1225,7 +1472,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* the configuration information for the specified ADC.
* @retval HAL state
*/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
{
/* Return ADC state */
return hadc->State;
@@ -1346,21 +1593,49 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
+ /* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
}
else
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
}
-
- HAL_ADC_ConvCpltCallback(hadc);
}
/**
@@ -1385,12 +1660,15 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hadc->State= HAL_ADC_STATE_ERROR;
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
HAL_ADC_ErrorCallback(hadc);
}
+/**
+ * @}
+ */
/**
* @}
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c
index a5b4718ce..cee4e1c55 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -131,10 +131,10 @@
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
/** @addtogroup ADCEx_Private_Functions
* @{
*/
+/* Private function prototypes -----------------------------------------------*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
@@ -142,14 +142,14 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Functions ADC Exported Functions
* @{
*/
/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
+ * @brief Extended features functions
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -182,17 +182,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if a regular conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_REG)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ;
- }
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
@@ -201,7 +191,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay for temperature sensor stabilization time */
+ /* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
@@ -210,31 +200,58 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
}
}
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if(tmp1 && tmp2)
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
}
- }
- else
- {
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if((hadc->Instance == ADC1) && tmp1 && tmp2)
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if(tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
+ }
+ else
+ {
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
@@ -249,25 +266,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0;
- uint32_t tmp1 = 0, tmp2 =0;
+ uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
- /* Check if a regular conversion is ongoing */
- if(hadc->State == HAL_ADC_STATE_BUSY_REG)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_INJ;
- }
-
- /* Set ADC error code to none */
- hadc->ErrorCode = HAL_ADC_ERROR_NONE;
+ /* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
@@ -276,7 +280,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay for temperature sensor stabilization time */
+ /* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
@@ -285,60 +289,122 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
}
}
- /* Enable the ADC end of conversion interrupt for injected group */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+ /* Check if a regular conversion is ongoing */
+ /* Note: On this device, there is no ADC error code fields related to */
+ /* conversions on group injected only. In case of conversion on */
+ /* going on group regular, no error code is reset. */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
- /* Enable the ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
- /* Check if Multimode enabled */
- if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
- {
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if(tmp1 && tmp2)
+ /* Clear injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+
+ /* Enable end of conversion interrupt for injected channels */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Check if Multimode enabled */
+ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if(tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
}
- }
- else
- {
- tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
- tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
- if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ else
{
- /* Enable the selected ADC software conversion for injected group */
- hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
+ tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
+ if((hadc->Instance == ADC1) && tmp1 && tmp2)
+ {
+ /* Enable the selected ADC software conversion for injected group */
+ hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
+ }
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
/* Return function status */
return HAL_OK;
}
/**
- * @brief Disables ADC and stop conversion of injected channels.
- *
- * @note Caution: This function will stop also regular channels.
- *
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval HAL status.
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
{
- /* Disable the Peripheral */
- __HAL_ADC_DISABLE(hadc);
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -371,16 +437,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
}
- /* Check if a regular conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_REG)
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
+ (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
- }
- else
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ;
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
/* Return ADC state */
@@ -388,30 +470,65 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
}
/**
- * @brief Disables the interrupt and stop ADC conversion of injected channels.
- *
- * @note Caution: This function will stop also regular channels.
- *
- * @param hadc: pointer to a ADC_HandleTypeDef structure that contains
- * the configuration information for the specified ADC.
- * @retval HAL status.
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @param hadc: ADC handle
+ * @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
{
- /* Disable the ADC end of conversion interrupt for regular group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- /* Disable the ADC end of conversion interrupt for injected group */
- __HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Enable the Peripheral */
- __HAL_ADC_DISABLE(hadc);
+ /* Process locked */
+ __HAL_LOCK(hadc);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Stop potential conversion and disable ADC peripheral */
+ /* Conditioned to: */
+ /* - No conversion on the other group (regular group) is intended to */
+ /* continue (injected and regular groups stop conversion and ADC disable */
+ /* are common) */
+ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
+ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
+ HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
+ {
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
+ __HAL_ADC_DISABLE(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -433,8 +550,9 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
/* Check the parameters */
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
- /* Clear the ADCx's flag for injected end of conversion */
- __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
+ /* Clear injected group conversion flag to have similar behaviour as */
+ /* regular group: reading data register also clears end of conversion flag. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Return the selected ADC converted value */
switch(InjectedRank)
@@ -488,35 +606,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
/* Process locked */
__HAL_LOCK(hadc);
- /* Enable ADC overrun interrupt */
- __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-
- if (hadc->Init.DMAContinuousRequests != DISABLE)
- {
- /* Enable the selected ADC DMA request after last transfer */
- ADC->CCR |= ADC_CCR_DDS;
- }
- else
- {
- /* Disable the selected ADC EOC rising on each regular channel conversion */
- ADC->CCR &= ~ADC_CCR_DDS;
- }
-
- /* Set the DMA transfer complete callback */
- hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
-
- /* Set the DMA half transfer complete callback */
- hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
-
- /* Set the DMA error callback */
- hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
-
- /* Enable the DMA Stream */
- HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
@@ -533,15 +622,80 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
}
}
- /* if no external trigger present enable software conversion of regular channels */
- if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ /* Start conversion if ADC is effectively enabled */
+ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
- /* Enable the selected ADC software conversion for regular group */
- hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
- }
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular group operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* If conversions on group regular are also triggering group injected, */
+ /* update ADC state. */
+ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
+ /* State machine update: Check if an injected conversion is ongoing */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to conversions on group regular */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ if (hadc->Init.DMAContinuousRequests != DISABLE)
+ {
+ /* Enable the selected ADC DMA request after last transfer */
+ ADC->CCR |= ADC_CCR_DDS;
+ }
+ else
+ {
+ /* Disable the selected ADC EOC rising on each regular channel conversion */
+ ADC->CCR &= ~ADC_CCR_DDS;
+ }
+
+ /* Enable the DMA Stream */
+ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
+
+ /* if no external trigger present enable software conversion of regular channels */
+ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
+ {
+ /* Enable the selected ADC software conversion for regular group */
+ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+ }
+ }
/* Return function status */
return HAL_OK;
@@ -555,29 +709,42 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
/* Process locked */
__HAL_LOCK(hadc);
- /* Enable the Peripheral */
+ /* Stop potential conversion on going, on regular and injected groups */
+ /* Disable ADC peripheral */
__HAL_ADC_DISABLE(hadc);
- /* Disable ADC overrun interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+ /* Check if ADC is effectively disabled */
+ if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
+ {
+ /* Disable the selected ADC DMA mode for multimode */
+ ADC->CCR &= ~ADC_CCR_DDS;
- /* Disable the selected ADC DMA request after last transfer */
- ADC->CCR &= ~ADC_CCR_DDS;
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
- /* Disable the ADC DMA Stream */
- HAL_DMA_Abort(hadc->DMA_Handle);
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return HAL_OK;
+ return tmp_hal_status;
}
/**
@@ -601,6 +768,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
*/
@@ -626,7 +795,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
- assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
@@ -636,6 +804,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ }
+
/* Process locked */
__HAL_LOCK(hadc);
@@ -669,13 +842,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Set the SQx bits for the selected rank */
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
- /* Select external trigger to start conversion */
- hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
- hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ /* Select external trigger to start conversion */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
- /* Select external trigger polarity */
- hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
- hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ /* Select external trigger polarity */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
+ }
+ else
+ {
+ /* Reset the external trigger */
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
+ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
+ }
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
@@ -793,21 +980,49 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
{
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Check if an injected conversion is ready */
- if(hadc->State == HAL_ADC_STATE_EOC_INJ)
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ /* Note: On STM32F7, there is no independent flag of end of sequence. */
+ /* The test of scan sequence on going is done either with scan */
+ /* sequence disabled or with end of conversion flag set to */
+ /* of end of sequence. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) &&
+ (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
+ HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
}
else
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
}
-
- HAL_ADC_ConvCpltCallback(hadc);
}
/**
@@ -832,7 +1047,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
{
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hadc->State= HAL_ADC_STATE_ERROR;
+ hadc->State= HAL_ADC_STATE_ERROR_DMA;
/* Set ADC error code to DMA error */
hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
HAL_ADC_ErrorCallback(hadc);
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_can.c b/stmhal/hal/f7/src/stm32f7xx_hal_can.c
index 0f5d8a313..100336e44 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_can.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_can.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -18,7 +18,8 @@
==============================================================================
[..]
(#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
-@- In case you are using CAN2 only, you have to enable the CAN1 clock.
(#) CAN pins configuration
@@ -31,8 +32,12 @@
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
(#) Receive a CAN frame using HAL_CAN_Receive() function.
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -73,7 +78,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -165,7 +170,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
- uint32_t InitStatus = 3;
+ uint32_t InitStatus = CAN_INITSTATUS_FAILED;
uint32_t tickstart = 0;
/* Check CAN handle */
@@ -222,11 +227,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
}
/* Check acknowledge */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_INITSTATUS_FAILED;
- }
- else
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
/* Set the time triggered communication mode */
if (hcan->Init.TTCM == ENABLE)
@@ -293,32 +294,28 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
((uint32_t)hcan->Init.SJW) | \
((uint32_t)hcan->Init.BS1) | \
((uint32_t)hcan->Init.BS2) | \
- ((uint32_t)hcan->Init.Prescaler - 1);
+ ((uint32_t)hcan->Init.Prescaler - 1);
/* Request leave initialisation */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Check acknowledged */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
- InitStatus = CAN_INITSTATUS_FAILED;
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
}
- else
+
+ /* Check acknowledged */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_SUCCESS;
}
@@ -357,6 +354,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
{
uint32_t filternbrbitpos = 0;
+ CAN_TypeDef *can_ip;
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
@@ -367,83 +365,100 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+#if defined (CAN3)
+ /* Check the CAN instance */
+ if(hcan->Instance == CAN3)
+ {
+ can_ip = CAN3;
+ }
+ else
+ {
+ can_ip = CAN1;
+ }
+#else
+ can_ip = CAN1;
+#endif
/* Initialisation mode for the filter */
- CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
+ can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
+#if defined (CAN2)
/* Select the start slave bank */
- CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
- CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+ can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
+#endif
/* Filter Deactivation */
- CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
+ can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
/* 16-bit scale for the filter */
- CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
+ can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
- CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
{
/* 32-bit scale for the filter */
- CAN1->FS1R |= filternbrbitpos;
+ can_ip->FS1R |= filternbrbitpos;
+
/* 32-bit identifier or First 32-bit identifier */
- CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+
/* 32-bit mask or Second 32-bit identifier */
- CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
{
/*Id/Mask mode for the filter*/
- CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
+ can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/*Identifier list mode for the filter*/
- CAN1->FM1R |= (uint32_t)filternbrbitpos;
+ can_ip->FM1R |= (uint32_t)filternbrbitpos;
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
{
/* FIFO 0 assignation for the filter */
- CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
+ can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
}
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
{
/* FIFO 1 assignation for the filter */
- CAN1->FFA1R |= (uint32_t)filternbrbitpos;
+ can_ip->FFA1R |= (uint32_t)filternbrbitpos;
}
/* Filter activation */
if (sFilterConfig->FilterActivation == ENABLE)
{
- CAN1->FA1R |= filternbrbitpos;
+ can_ip->FA1R |= filternbrbitpos;
}
/* Leave the initialisation mode for the filter */
- CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
/* Return function status */
return HAL_OK;
@@ -490,6 +505,8 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspInit could be implemented in the user file
*/
@@ -503,6 +520,8 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspDeInit could be implemented in the user file
*/
@@ -538,7 +557,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
*/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
- uint32_t transmitmailbox = 5;
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
uint32_t tickstart = 0;
/* Check the parameters */
@@ -546,40 +565,38 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
+ /* Process locked */
+ __HAL_LOCK(hcan);
- /* Select one empty transmit mailbox */
- if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmitmailbox = 0;
- }
- else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmitmailbox = 1;
- }
- else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmitmailbox = 2;
- }
- else
- {
- transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- }
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
+
+ /* Select one empty transmit mailbox */
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
- if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
- {
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if (hcan->pTxMsg->IDE == CAN_ID_STD)
@@ -597,8 +614,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
}
/* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
@@ -613,8 +630,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Check End of transmission flag */
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
@@ -635,19 +652,16 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_OK;
}
@@ -656,9 +670,6 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
/* Return function status */
return HAL_ERROR;
}
@@ -672,16 +683,16 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
*/
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
{
- uint32_t transmitmailbox = 5;
- uint32_t tmp = 0;
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
- tmp = hcan->State;
- if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
@@ -689,96 +700,84 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/* Select one empty transmit mailbox */
if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
- transmitmailbox = 0;
+ transmitmailbox = CAN_TXMAILBOX_0;
}
else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
- transmitmailbox = 1;
- }
- else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmitmailbox = 2;
+ transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
- transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ transmitmailbox = CAN_TXMAILBOX_2;
}
- if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
- ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
- ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
- ((uint32_t)hcan->pTxMsg->Data[0]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
- ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
- ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
- ((uint32_t)hcan->pTxMsg->Data[4]));
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
- /* Enable Error warning Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
- /* Enable Error passive Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[0]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
+ ((uint32_t)hcan->pTxMsg->Data[4]));
- /* Enable Bus-off Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
- /* Enable Last error code Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- /* Enable Error Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
- /* Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
+ /* Enable Error warning, Error passive, Bus-off,
+ Last error and Error Interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
- }
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
}
else
{
- return HAL_BUSY;
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
}
return HAL_OK;
@@ -874,19 +873,16 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
}
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
/* Return function status */
return HAL_OK;
}
@@ -925,20 +921,13 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- /* Enable Error warning Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-
- /* Enable Error passive Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-
- /* Enable Bus-off Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-
- /* Enable Last error code Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-
- /* Enable Error Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+ /* Enable Error warning, Error passive, Bus-off,
+ Last error and Error Interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
/* Process unlocked */
__HAL_UNLOCK(hcan);
@@ -1120,8 +1109,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Set CAN error code to EWG error */
hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
- /* Clear Error Warning Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);
}
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
@@ -1132,8 +1119,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Set CAN error code to EPV error */
hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
- /* Clear Error Passive Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);
}
tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
@@ -1144,8 +1129,6 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Set CAN error code to BOF error */
hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
- /* Clear Bus-Off Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);
}
tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
@@ -1192,6 +1175,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
/* Call the Error call Back in case of Errors */
if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
{
+ /* Clear ERRI Flag */
+ hcan->Instance->MSR = CAN_MSR_ERRI;
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
/* Call Error callback function */
@@ -1207,6 +1192,8 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxCpltCallback could be implemented in the user file
*/
@@ -1220,6 +1207,8 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxCpltCallback could be implemented in the user file
*/
@@ -1233,6 +1222,8 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
@@ -1297,20 +1288,13 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
- /* Disable Error warning Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-
- /* Disable Error passive Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-
- /* Disable Bus-off Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-
- /* Disable Last error code Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-
- /* Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
@@ -1385,20 +1369,13 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
- /* Disable Error warning Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-
- /* Disable Error passive Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-
- /* Disable Bus-off Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-
- /* Disable Last error code Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-
- /* Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c b/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c
index e8008351e..b7dd19ad5 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_cortex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -269,6 +269,46 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
*/
#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU and clear the control register*/
+ MPU->CTRL = 0;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Ensure MPU setting take effects */
+ __DSB();
+ __ISB();
+}
+
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dac.c b/stmhal/hal/f7/src/stm32f7xx_hal_dac.c
index 77adc6120..a37465bcd 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_dac.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -143,7 +143,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -302,6 +302,9 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
@@ -315,6 +318,9 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
@@ -682,6 +688,9 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallback could be implemented in the user file
*/
@@ -695,6 +704,9 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
*/
@@ -708,6 +720,9 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
@@ -721,6 +736,9 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c
index ca6d12b95..a7b803e9b 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -269,6 +269,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
*/
@@ -282,6 +285,9 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
@@ -295,6 +301,9 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
@@ -308,6 +317,9 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdac);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_dma.c b/stmhal/hal/f7/src/stm32f7xx_hal_dma.c
index 1bb953aa3..92f0d975c 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_dma.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -19,7 +19,7 @@
(#) Enable and configure the peripheral to be connected to the DMA Stream
(except for internal SRAM/FLASH memories: no initialization is
necessary) please refer to Reference manual for connection between peripherals
- and DMA requests .
+ and DMA requests.
(#) For a given Stream, program the required configuration through the following parameters:
Transfer Direction, Source and Destination data formats,
@@ -27,13 +27,17 @@
Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+ -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+ __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+
*** Polling mode IO operation ***
=================================
[..]
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
+ address and destination address and the Length of data to be transferred.
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
case a fixed Timeout can be configured by User depending from his application.
+ (+) Use HAL_DMA_Abort() function to abort the current transfer.
*** Interrupt mode IO operation ***
===================================
@@ -51,7 +55,7 @@
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
- (#) Use HAL_DMA_Abort() function to abort the current transfer
+ (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
@@ -72,11 +76,6 @@
(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
- (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
- (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
[..]
@@ -86,7 +85,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -128,12 +127,19 @@
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register */
+ __IO uint32_t Reserved0;
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA_Private_Constants
* @{
*/
- #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
+ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
/**
* @}
*/
@@ -143,42 +149,8 @@
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
- * @brief Sets the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
- * @retval HAL status
- */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* Clear DBM bit */
- hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
-
- /* Configure DMA Stream data length */
- hdma->Instance->NDTR = DataLength;
-
- /* Peripheral to Memory */
- if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- {
- /* Configure DMA Stream destination address */
- hdma->Instance->PAR = DstAddress;
-
- /* Configure DMA Stream source address */
- hdma->Instance->M0AR = SrcAddress;
- }
- /* Memory to Peripheral */
- else
- {
- /* Configure DMA Stream source address */
- hdma->Instance->PAR = SrcAddress;
-
- /* Configure DMA Stream destination address */
- hdma->Instance->M0AR = DstAddress;
- }
-}
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
/**
* @}
@@ -208,7 +180,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
*/
/**
- * @brief Initializes the DMA according to the specified
+ * @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and create the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
@@ -216,7 +188,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
+ uint32_t tickstart = HAL_GetTick();
+ DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
@@ -244,9 +218,31 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
}
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA Stream is effectively disabled */
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Get the CR register value */
tmp = hdma->Instance->CR;
@@ -286,11 +282,29 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
+
+ if (DMA_CheckFifoParam(hdma) != HAL_OK)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -308,6 +322,8 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
+ DMA_Base_Registers *regs;
+
/* Check the DMA peripheral state */
if(hdma == NULL)
{
@@ -317,36 +333,39 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
{
- return HAL_ERROR;
+ /* Return error status */
+ return HAL_BUSY;
}
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
/* Reset DMA Streamx control register */
- hdma->Instance->CR = 0;
+ hdma->Instance->CR = 0U;
/* Reset DMA Streamx number of data to transfer register */
- hdma->Instance->NDTR = 0;
+ hdma->Instance->NDTR = 0U;
/* Reset DMA Streamx peripheral address register */
- hdma->Instance->PAR = 0;
+ hdma->Instance->PAR = 0U;
/* Reset DMA Streamx memory 0 address register */
- hdma->Instance->M0AR = 0;
+ hdma->Instance->M0AR = 0U;
/* Reset DMA Streamx memory 1 address register */
- hdma->Instance->M1AR = 0;
+ hdma->Instance->M1AR = 0U;
/* Reset DMA Streamx FIFO control register */
- hdma->Instance->FCR = (uint32_t)0x00000021;
+ hdma->Instance->FCR = (uint32_t)0x00000021U;
+
+ /* Get DMA steam Base Address */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
- /* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -393,25 +412,37 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
/* Process locked */
__HAL_LOCK(hdma);
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
- return HAL_OK;
+ /* Return error status */
+ status = HAL_BUSY;
+ }
+ return status;
}
/**
@@ -425,40 +456,53 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- /* Process locked */
- __HAL_LOCK(hdma);
+ HAL_StatusTypeDef status = HAL_OK;
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
+ /* Process locked */
+ __HAL_LOCK(hdma);
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Enable the transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
- /* Enable the Half transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
- /* Enable the transfer Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+ /* Enable Common interrupts*/
+ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+ hdma->Instance->FCR |= DMA_IT_FE;
- /* Enable the FIFO Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ hdma->Instance->CR |= DMA_IT_HT;
+ }
- /* Enable the direct mode Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
+ /* Return error status */
+ status = HAL_BUSY;
+ }
- return HAL_OK;
+ return status;
}
/**
@@ -475,37 +519,86 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
- uint32_t tickstart = 0;
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
- /* Disable the stream */
- __HAL_DMA_DISABLE(hdma);
+ uint32_t tickstart = HAL_GetTick();
- /* Get tick */
- tickstart = HAL_GetTick();
+ if(hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
- /* Check if the DMA Stream is effectively disabled */
- while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ /* Disable all the transfer interrupts */
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ hdma->Instance->FCR &= ~(DMA_IT_FE);
+
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+ hdma->Instance->CR &= ~(DMA_IT_HT);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_TIMEOUT;
+ /* Check if the DMA Stream is effectively disabled */
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
- return HAL_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
}
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
}
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ return HAL_OK;
+}
- /* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
+/**
+ * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ if(hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set Abort State */
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+ }
return HAL_OK;
}
@@ -515,155 +608,140 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param CompleteLevel: Specifies the DMA level complete.
+ * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+ * This model could be used for debug purpose.
+ * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
* @param Timeout: Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
{
- uint32_t temp, tmp, tmp1, tmp2;
- uint32_t tickstart = 0;
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t mask_cpltlevel;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t tmpisr;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* No transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode and double buffering mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Transfer Complete flag */
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
}
else
{
/* Half Transfer Complete flag */
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
}
- /* Get tick */
- tickstart = HAL_GetTick();
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ tmpisr = regs->ISR;
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
{
- tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
- if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
+ /* Check for the Timeout (Not applicable in circular mode)*/
+ if(Timeout != HAL_MAX_DELAY)
{
- if(tmp != RESET)
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
- /* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- }
- if(tmp1 != RESET)
- {
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
- /* Clear the FIFO error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
- }
- if(tmp2 != RESET)
- {
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
- /* Clear the Direct Mode error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ return HAL_TIMEOUT;
}
- /* Change the DMA state */
- hdma->State= HAL_DMA_STATE_ERROR;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ /* Get the ISR register value */
+ tmpisr = regs->ISR;
- return HAL_ERROR;
+ if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+ /* Clear the transfer error flag */
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
}
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+
+ if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_TIMEOUT;
+ /* Clear the FIFO error flag */
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;
- return HAL_TIMEOUT;
- }
+ /* Clear the Direct Mode error flag */
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
}
}
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
{
- /* Multi_Buffering mode enabled */
- if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ HAL_DMA_Abort(hdma);
- /* Current memory buffer used is Memory 0 */
- if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_MEM0;
- }
- /* Current memory buffer used is Memory 1 */
- else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_MEM1;
- }
- }
- else
- {
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State= HAL_DMA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the level transfer complete flag */
+ if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
- /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
- are complete) */
- hdma->State = HAL_DMA_STATE_READY_MEM0;
- }
/* Process Unlocked */
__HAL_UNLOCK(hdma);
+
+ hdma->State = HAL_DMA_STATE_READY;
}
else
{
- /* Multi_Buffering mode enabled */
- if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
- {
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Current memory buffer used is Memory 0 */
- if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
- }
- /* Current memory buffer used is Memory 1 */
- else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
- {
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
- }
- }
- else
- {
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
- }
+ /* Clear the half transfer and transfer complete flags */
+ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
}
- return HAL_OK;
+
+ return status;
}
/**
@@ -674,145 +752,140 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
+ uint32_t tmpisr;
+ __IO uint32_t count = 0;
+ uint32_t timeout = SystemCoreClock / 9600;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+ tmpisr = regs->ISR;
+
/* Transfer Error Interrupt management ***************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
{
/* Disable the transfer error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+ hdma->Instance->CR &= ~(DMA_IT_TE);
/* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
}
}
/* FIFO Error Interrupt management ******************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET)
+ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
{
- /* Disable the FIFO Error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
-
/* Clear the FIFO error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
}
}
/* Direct Mode Error Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET)
+ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
{
- /* Disable the direct mode Error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
-
/* Clear the direct mode error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
}
}
/* Half Transfer Complete Interrupt management ******************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
{
+ /* Clear the half transfer complete flag */
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+
/* Multi_Buffering mode enabled */
- if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
{
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
/* Current memory buffer used is Memory 0 */
- if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
{
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
}
/* Current memory buffer used is Memory 1 */
- else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+ else
{
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
+ if(hdma->XferM1HalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferM1HalfCpltCallback(hdma);
+ }
}
}
else
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
{
/* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ hdma->Instance->CR &= ~(DMA_IT_HT);
}
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
- }
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
}
}
}
/* Transfer Complete Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
{
- if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+ /* Clear the transfer complete flag */
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+
+ if(HAL_DMA_STATE_ABORT == hdma->State)
{
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ /* Disable all the transfer interrupts */
+ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ hdma->Instance->FCR &= ~(DMA_IT_FE);
- /* Current memory buffer used is Memory 1 */
- if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+ if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ {
+ hdma->Instance->CR &= ~(DMA_IT_HT);
+ }
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ if(hdma->XferAbortCallback != NULL)
+ {
+ hdma->XferAbortCallback(hdma);
+ }
+ return;
+ }
+
+ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+ {
+ /* Current memory buffer used is Memory 0 */
+ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
{
if(hdma->XferM1CpltCallback != NULL)
{
@@ -820,8 +893,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->XferM1CpltCallback(hdma);
}
}
- /* Current memory buffer used is Memory 0 */
- else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+ /* Current memory buffer used is Memory 1 */
+ else
{
if(hdma->XferCpltCallback != NULL)
{
@@ -833,22 +906,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
else
{
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
{
/* Disable the transfer complete interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
- }
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ hdma->Instance->CR &= ~(DMA_IT_TC);
- /* Update error code */
- hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY_MEM0;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
if(hdma->XferCpltCallback != NULL)
{
@@ -858,6 +926,169 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
}
}
}
+
+ /* manage error case */
+ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ {
+ if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+ {
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+
+ do
+ {
+ if (++count > timeout)
+ {
+ break;
+ }
+ }
+ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ if(hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID: User Callback identifer
+ * a DMA_HandleTypeDef structure as parameter.
+ * @param pCallback: pointer to private callbacsk function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_M1CPLT_CB_ID:
+ hdma->XferM1CpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ hdma->XferM1HalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID: User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_M1CPLT_CB_ID:
+ hdma->XferM1CpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ hdma->XferM1HalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferM1CpltCallback = NULL;
+ hdma->XferM1HalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
}
/**
@@ -905,6 +1136,172 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
* @}
*/
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Clear DBM bit */
+ hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+ /* Configure DMA Stream data length */
+ hdma->Instance->NDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Stream destination address */
+ hdma->Instance->PAR = DstAddress;
+
+ /* Configure DMA Stream source address */
+ hdma->Instance->M0AR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Stream source address */
+ hdma->Instance->PAR = SrcAddress;
+
+ /* Configure DMA Stream destination address */
+ hdma->Instance->M0AR = DstAddress;
+ }
+}
+
+/**
+ * @brief Returns the DMA Stream base address depending on stream number
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval Stream base address
+ */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
+
+ /* lookup table for necessary bitshift of flags within status registers */
+ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+ hdma->StreamIndex = flagBitshiftOffset[stream_number];
+
+ if (stream_number > 3U)
+ {
+ /* return pointer to HISR and HIFCR */
+ hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
+ }
+ else
+ {
+ /* return pointer to LISR and LIFCR */
+ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
+ }
+
+ return hdma->StreamBaseAddress;
+}
+
+/**
+ * @brief Check compatibility between FIFO threshold level and size of the memory burst
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp = hdma->Init.FIFOThreshold;
+
+ /* Memory Data size equal to Byte */
+ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+ {
+ switch (tmp)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_FULL:
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Memory Data size equal to Half-Word */
+ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ switch (tmp)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ status = HAL_ERROR;
+ break;
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ status = HAL_ERROR;
+ break;
+ case DMA_FIFO_THRESHOLD_FULL:
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Memory Data size equal to Word */
+ else
+ {
+ switch (tmp)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ status = HAL_ERROR;
+ break;
+ case DMA_FIFO_THRESHOLD_FULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ return status;
+}
+
/**
* @}
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_flash.c b/stmhal/hal/f7/src/stm32f7xx_hal_flash.c
index b5ca6dcf4..b28b2768d 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_flash.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -118,8 +118,8 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+#define SECTOR_MASK ((uint32_t)0xFFFFFF07U)
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
/**
* @}
*/
@@ -327,6 +327,9 @@ void HAL_FLASH_IRQHandler(void)
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
switch (pFlash.ProcedureOnGoing)
{
case FLASH_PROC_SECTERASE :
@@ -341,9 +344,6 @@ void HAL_FLASH_IRQHandler(void)
/* Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(temp);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
/* Increment sector number */
temp = ++pFlash.Sector;
FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
@@ -352,13 +352,11 @@ void HAL_FLASH_IRQHandler(void)
{
/* No more sectors to Erase, user callback can be called.*/
/* Reset Sector and stop Erase sectors procedure */
- pFlash.Sector = temp = 0xFFFFFFFF;
+ pFlash.Sector = temp = 0xFFFFFFFFU;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(temp);
/* Sector Erase procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
break;
}
@@ -370,8 +368,6 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_EndOfOperationCallback(0);
/* MAss Erase procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
break;
}
@@ -382,8 +378,6 @@ void HAL_FLASH_IRQHandler(void)
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
/* Programming procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
break;
}
default :
@@ -392,7 +386,7 @@ void HAL_FLASH_IRQHandler(void)
}
/* Check FLASH operation error flags */
- if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
{
switch (pFlash.ProcedureOnGoing)
{
@@ -400,7 +394,7 @@ void HAL_FLASH_IRQHandler(void)
{
/* return the faulty sector */
temp = pFlash.Sector;
- pFlash.Sector = 0xFFFFFFFF;
+ pFlash.Sector = 0xFFFFFFFFU;
break;
}
case FLASH_PROC_MASSERASE :
@@ -415,16 +409,14 @@ void HAL_FLASH_IRQHandler(void)
temp = pFlash.Address;
break;
}
- default :
- break;
+ default :
+ break;
}
/*Save the Error code*/
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(temp);
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR );
/*Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
@@ -455,9 +447,11 @@ void HAL_FLASH_IRQHandler(void)
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
- */
+ the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+ */
}
/**
@@ -471,8 +465,10 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+ the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
@@ -637,14 +633,20 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
}
}
- if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
- FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
+
/* If there is an error flag set */
return HAL_OK;
@@ -774,6 +776,11 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
*/
static void FLASH_SetErrorCode(void)
{
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+ }
+
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
@@ -794,10 +801,8 @@ static void FLASH_SetErrorCode(void)
pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
}
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
- }
+ /* Clear error programming flags */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
}
/**
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c
index 359f09eed..b6f2a3e3c 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -14,13 +14,13 @@
##### Flash Extension features #####
==============================================================================
- [..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and
+ [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx
devices contains the following additional features
(+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
capability (RWW)
(+) Dual bank memory organization
- (+) PCROP protection for all banks
+ (+) Dual boot mode
##### How to use this driver #####
==============================================================================
@@ -39,18 +39,12 @@
(++) Set the Read protection Level
(++) Set the BOR level
(++) Program the user Option Bytes
- (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
- (++) Extended space (bank 2) erase function
- (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
- (++) Dual Boot activation
- (++) Write protection configuration for bank 2
- (++) PCROP protection configuration and control for both banks
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -96,8 +90,8 @@
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+#define SECTOR_MASK 0xFFFFFF07U
+#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */
/**
* @}
*/
@@ -117,11 +111,9 @@ extern FLASH_ProcessTypeDef pFlash;
* @{
*/
/* Option bytes control */
-static void FLASH_MassErase(uint8_t VoltageRange);
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level);
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
static uint32_t FLASH_OB_GetUser(void);
@@ -130,6 +122,15 @@ static uint8_t FLASH_OB_GetRDP(void);
static uint32_t FLASH_OB_GetBOR(void);
static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
+#if defined (FLASH_OPTCR_nDBANK)
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
+ uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
+#else
+static void FLASH_MassErase(uint8_t VoltageRange);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
+#endif /* FLASH_OPTCR_nDBANK */
+
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
@@ -182,12 +183,16 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
if(status == HAL_OK)
{
/*Initialization of SectorError variable*/
- *SectorError = 0xFFFFFFFF;
+ *SectorError = 0xFFFFFFFFU;
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
+#if defined (FLASH_OPTCR_nDBANK)
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+#else
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
+#endif /* FLASH_OPTCR_nDBANK */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
@@ -208,9 +213,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- /* If the erase operation is completed, disable the SER Bit */
- FLASH->CR &= (~FLASH_CR_SER);
- FLASH->CR &= SECTOR_MASK;
+ /* If the erase operation is completed, disable the SER Bit and SNB Bits */
+ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
if(status != HAL_OK)
{
@@ -259,7 +263,11 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
/*Mass erase to be done*/
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+#if defined (FLASH_OPTCR_nDBANK)
+ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+#else
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
+#endif /* FLASH_OPTCR_nDBANK */
}
else
{
@@ -281,7 +289,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
}
/**
- * @brief Program option bytes
+ * @brief Program option bytes
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
@@ -322,12 +330,23 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
/* USER configuration */
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
{
+#if defined (FLASH_OPTCR_nDBANK)
+ status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
+ pOBInit->USERConfig & OB_IWDG_SW,
+ pOBInit->USERConfig & OB_STOP_NO_RST,
+ pOBInit->USERConfig & OB_STDBY_NO_RST,
+ pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
+ pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
+ pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
+ pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
+#else
status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
pOBInit->USERConfig & OB_IWDG_SW,
pOBInit->USERConfig & OB_STOP_NO_RST,
pOBInit->USERConfig & OB_STDBY_NO_RST,
pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
+#endif /* FLASH_OPTCR_nDBANK */
}
/* BOR Level configuration */
@@ -355,7 +374,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
}
/**
- * @brief Get the Option byte configuration
+ * @brief Get the Option byte configuration
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
@@ -364,7 +383,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
- OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
+ OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
/*Get WRP*/
pOBInit->WRPSector = FLASH_OB_GetWRP();
@@ -378,17 +397,17 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/*Get BOR Level*/
pOBInit->BORLevel = FLASH_OB_GetBOR();
- /*Get Boot Address when Boot pin = 0 */
+ /*Get Boot Address when Boot pin = 0 */
pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
/*Get Boot Address when Boot pin = 1 */
pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
}
-
/**
* @}
*/
+#if defined (FLASH_OPTCR_nDBANK)
/**
* @brief Full erase of FLASH memory sectors
* @param VoltageRange: The device voltage range which defines the erase parallelism.
@@ -401,21 +420,38 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
* the operation will be done by word (32-bit)
* @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
+ * @param Banks: Banks to be erased
+ * This parameter can be one of the following values:
+ * @arg FLASH_BANK_1: Bank1 to be erased
+ * @arg FLASH_BANK_2: Bank2 to be erased
+ * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
*
* @retval HAL Status
*/
-static void FLASH_MassErase(uint8_t VoltageRange)
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
{
- uint32_t tmp_psize = 0;
-
/* Check the parameters */
assert_param(IS_VOLTAGERANGE(VoltageRange));
+ assert_param(IS_FLASH_BANK(Banks));
/* if the previous operation is completed, proceed to erase all sectors */
FLASH->CR &= CR_PSIZE_MASK;
- FLASH->CR |= tmp_psize;
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
+ if(Banks == FLASH_BANK_BOTH)
+ {
+ /* bank1 & bank2 will be erased*/
+ FLASH->CR |= FLASH_MER_BIT;
+ }
+ else if(Banks == FLASH_BANK_2)
+ {
+ /*Only bank2 will be erased*/
+ FLASH->CR |= FLASH_CR_MER2;
+ }
+ else
+ {
+ /*Only bank1 will be erased*/
+ FLASH->CR |= FLASH_CR_MER1;
+ }
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
@@ -463,10 +499,16 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
}
+ /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+ if(Sector > FLASH_SECTOR_11)
+ {
+ Sector += 4;
+ }
+
/* If the previous operation is completed, proceed to erase the sector */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
- FLASH->CR &= SECTOR_MASK;
+ CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
FLASH->CR |= FLASH_CR_STRT;
@@ -476,104 +518,191 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
}
/**
- * @brief Enable the write protection of the desired bank1 or bank 2 sectors
- *
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
- *
- * @param WRPSector: specifies the sector(s) to be write protected.
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval uint32_t FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
+}
+
+/**
+ * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param Wwdg: Selects the IWDG mode
* This parameter can be one of the following values:
- * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
- * @arg OB_WRP_SECTOR_All
- *
- * @retval HAL FLASH State
+ * @arg OB_WWDG_SW: Software WWDG selected
+ * @arg OB_WWDG_HW: Hardware WWDG selected
+ * @param Iwdg: Selects the WWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param Stop: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param Stdby: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
+ * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
+ * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
+ * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
+ * @param NDBank: Flash Single Bank mode enabled.
+ * This parameter can be one of the following values:
+ * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
+ * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)
+ * @param NDBoot: Flash Dual boot mode disable.
+ * This parameter can be one of the following values:
+ * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
+ * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
+
+ * @retval HAL Status
*/
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
+ uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
{
+ uint32_t useroptionmask = 0x00;
+ uint32_t useroptionvalue = 0x00;
+
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_OB_WRP_SECTOR(WRPSector));
+ assert_param(IS_OB_WWDG_SOURCE(Wwdg));
+ assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+ assert_param(IS_OB_STOP_SOURCE(Stop));
+ assert_param(IS_OB_STDBY_SOURCE(Stdby));
+ assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
+ assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
+ assert_param(IS_OB_NDBANK(NDBank));
+ assert_param(IS_OB_NDBOOT(NDBoot));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- /*Write protection enabled on sectors */
- FLASH->OPTCR &= (~WRPSector);
+ useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
+ FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
+ FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
+
+ useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
+
+ /* Update User Option Byte */
+ MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
}
return status;
}
/**
- * @brief Disable the write protection of the desired bank1 or bank 2 sectors
- *
- * @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash sector i if CortexM4
- * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
- *
- * @param WRPSector: specifies the sector(s) to be write protected.
+ * @brief Return the FLASH User Option Byte value.
+ * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
+ * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
+ */
+static uint32_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
+}
+#else
+
+/**
+ * @brief Full erase of FLASH memory sectors
+ * @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
- * @arg OB_WRP_Sector_All
- *
+ * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
*
* @retval HAL Status
*/
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
+static void FLASH_MassErase(uint8_t VoltageRange)
{
- HAL_StatusTypeDef status = HAL_OK;
-
/* Check the parameters */
- assert_param(IS_OB_WRP_SECTOR(WRPSector));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
- if(status == HAL_OK)
- {
- /* Write protection disabled on sectors */
- FLASH->OPTCR |= (WRPSector);
- }
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
- return status;
+ /* if the previous operation is completed, proceed to erase all sectors */
+ FLASH->CR &= CR_PSIZE_MASK;
+ FLASH->CR |= FLASH_CR_MER;
+ FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
+ /* Data synchronous Barrier (DSB) Just after the write operation
+ This will force the CPU to respect the sequence of instruction (no optimization).*/
+ __DSB();
}
-
-
-
/**
- * @brief Set the read protection level.
- * @param Level: specifies the read protection level.
+ * @brief Erase the specified FLASH memory sector
+ * @param Sector: FLASH sector to erase
+ * The value of this parameter depend on device used within the same series
+ * @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
- * @arg OB_RDP_LEVEL_0: No protection
- * @arg OB_RDP_LEVEL_1: Read protection of the memory
- * @arg OB_RDP_LEVEL_2: Full chip protection
- *
- * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+ * the operation will be done by byte (8-bit)
+ * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+ * the operation will be done by half word (16-bit)
+ * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+ * the operation will be done by word (32-bit)
+ * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+ * the operation will be done by double word (64-bit)
*
- * @retval HAL Status
+ * @retval None
*/
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
{
- HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tmp_psize = 0;
/* Check the parameters */
- assert_param(IS_OB_RDP_LEVEL(Level));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ assert_param(IS_FLASH_SECTOR(Sector));
+ assert_param(IS_VOLTAGERANGE(VoltageRange));
- if(status == HAL_OK)
+ if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
+ {
+ tmp_psize = FLASH_PSIZE_BYTE;
+ }
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
+ {
+ tmp_psize = FLASH_PSIZE_HALF_WORD;
+ }
+ else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
+ {
+ tmp_psize = FLASH_PSIZE_WORD;
+ }
+ else
{
- MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_RDP, Level);
+ tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
}
- return status;
+ /* If the previous operation is completed, proceed to erase the sector */
+ FLASH->CR &= CR_PSIZE_MASK;
+ FLASH->CR |= tmp_psize;
+ FLASH->CR &= SECTOR_MASK;
+ FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Data synchronous Barrier (DSB) Just after the write operation
+ This will force the CPU to respect the sequence of instruction (no optimization).*/
+ __DSB();
+}
+
+/**
+ * @brief Return the FLASH Write Protection Option Bytes value.
+ * @retval uint32_t FLASH Write Protection Option Bytes value
+ */
+static uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
}
/**
@@ -604,7 +733,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint32_t Level)
* @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
* @retval HAL Status
*/
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby )
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
{
uint32_t useroptionmask = 0x00;
uint32_t useroptionvalue = 0x00;
@@ -637,6 +766,119 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint3
}
+/**
+ * @brief Return the FLASH User Option Byte value.
+ * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
+ * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
+ */
+static uint32_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));
+}
+#endif /* FLASH_OPTCR_nDBANK */
+
+/**
+ * @brief Enable the write protection of the desired bank1 or bank2 sectors
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash sector i if CortexM7
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WRPSector: specifies the sector(s) to be write protected.
+ * This parameter can be one of the following values:
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
+ * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
+ * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
+ * @arg OB_WRP_SECTOR_All
+ *
+ * @retval HAL FLASH State
+ */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /*Write protection enabled on sectors */
+ FLASH->OPTCR &= (~WRPSector);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Disable the write protection of the desired bank1 or bank 2 sectors
+ *
+ * @note When the memory read protection level is selected (RDP level = 1),
+ * it is not possible to program or erase the flash sector i if CortexM4
+ * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+ *
+ * @param WRPSector: specifies the sector(s) to be write protected.
+ * This parameter can be one of the following values:
+ * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
+ * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
+ * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
+ * @arg OB_WRP_Sector_All
+ *
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP_SECTOR(WRPSector));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ /* Write protection disabled on sectors */
+ FLASH->OPTCR |= (WRPSector);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set the read protection level.
+ * @param Level: specifies the read protection level.
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
+ *
+ * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+ *
+ * @retval HAL Status
+ */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP_LEVEL(Level));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ if(status == HAL_OK)
+ {
+ *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
+ }
+
+ return status;
+}
+
/**
* @brief Set the BOR Level.
* @param Level: specifies the Option Bytes BOR Reset Level.
@@ -693,37 +935,16 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_
if(BootOption == OPTIONBYTE_BOOTADDR_0)
{
MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
- }
- else
- {
- MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
- }
+ }
+ else
+ {
+ MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
+ }
}
return status;
}
-/**
- * @brief Return the FLASH User Option Byte value.
- * @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
- * and RST_STDBY(Bit2).
- */
-static uint32_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
-}
-
-/**
- * @brief Return the FLASH Write Protection Option Bytes value.
- * @retval uint32_t FLASH Write Protection Option Bytes value
- */
-static uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
-}
-
/**
* @brief Returns the FLASH Read Protection level.
* @retval FlagStatus FLASH ReadOut Protection Status:
@@ -736,11 +957,11 @@ static uint8_t FLASH_OB_GetRDP(void)
{
uint8_t readstatus = OB_RDP_LEVEL_0;
- if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_0)
+ if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
{
readstatus = OB_RDP_LEVEL_0;
}
- else if (((FLASH->OPTCR & FLASH_OPTCR_RDP) >> 8) == OB_RDP_LEVEL_2)
+ else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
{
readstatus = OB_RDP_LEVEL_2;
}
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c b/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c
index daec5d625..1cba15df6 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -95,7 +95,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -141,15 +141,15 @@
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
-#define GPIO_MODE ((uint32_t)0x00000003)
-#define EXTI_MODE ((uint32_t)0x10000000)
-#define GPIO_MODE_IT ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT ((uint32_t)0x00020000)
-#define RISING_EDGE ((uint32_t)0x00100000)
-#define FALLING_EDGE ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
-
-#define GPIO_NUMBER ((uint32_t)16)
+#define GPIO_MODE ((uint32_t)0x00000003U)
+#define EXTI_MODE ((uint32_t)0x10000000U)
+#define GPIO_MODE_IT ((uint32_t)0x00010000U)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
+#define RISING_EDGE ((uint32_t)0x00100000U)
+#define FALLING_EDGE ((uint32_t)0x00200000U)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
+
+#define GPIO_NUMBER ((uint32_t)16U)
/**
* @}
*/
@@ -514,6 +514,9 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c b/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c
index 2c51ee21d..66a154edc 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -21,7 +21,7 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -33,15 +33,16 @@
(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx Stream
+ (+++) Configure the DMA Tx or Rx stream
(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx stream
- (#) Configure the Communication Clock Timing, Own Address1, Master Addressing Mode, Dual Addressing mode,
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
@@ -65,70 +66,133 @@
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
+
+
+ *** Interrupt mode IO sequential operation ***
+ ===================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+ several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and with a final stop condition in both cases
+
+ (+) Differents sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
+ (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
- (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
HAL_I2C_Mem_Write_IT()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
HAL_I2C_Mem_Read_IT()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
- (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
+ (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
- (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
HAL_I2C_Mem_Write_DMA()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
HAL_I2C_Mem_Read_DMA()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -138,8 +202,9 @@
(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
+ (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
@@ -150,7 +215,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -192,52 +257,104 @@
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup I2C_Private_Constants I2C Private Constants
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup I2C_Private_Define I2C Private Define
* @{
*/
-#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*State) == HAL_I2C_STATE_BUSY_TX) ? \
+ ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
+ ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions I2C Private Functions
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
+/* Private functions to handle DMA transfer */
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-
-static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c);
-
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+/* Private functions to handle IT transfer */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
+
+/* Private functions to handle IT transfer */
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions for I2C transfer IRQ handler */
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+
+/* Private functions to flush TXDR register */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
+
+/* Private functions to handle start, restart or stop a transfer */
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
@@ -257,7 +374,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialize the I2Cx peripheral:
+ deinitialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
@@ -282,9 +399,9 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
/**
* @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * in the I2C_InitTypeDef and initialize the associated handle.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
@@ -309,6 +426,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
}
@@ -323,18 +441,17 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ /* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if(hi2c->Init.OwnAddress1 != 0)
+
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- }
- else /* I2C_ADDRESSINGMODE_10BIT */
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- }
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
@@ -347,6 +464,9 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
@@ -359,14 +479,16 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
return HAL_OK;
}
/**
- * @brief DeInitializes the I2C peripheral.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief DeInitialize the I2C peripheral.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
@@ -389,8 +511,9 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
HAL_I2C_MspDeInit(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Release Lock */
__HAL_UNLOCK(hi2c);
@@ -399,27 +522,33 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief I2C MSP Init.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Initialize the I2C MSP.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
/**
- * @brief I2C MSP DeInit
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief DeInitialize the I2C MSP.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
@@ -489,9 +618,10 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
/**
* @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -499,44 +629,47 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t sizetmp = 0;
+ uint32_t tickstart = 0;
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_BUSY;
+ return HAL_TIMEOUT;
}
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
/* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- /* Size > 255, need to set RELOAD bit */
- if(Size > 255)
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
- sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
- sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
}
- do
+ while(hi2c->XferSize > 0)
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -548,35 +681,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
}
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*pData++);
- sizetmp--;
- Size--;
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
- if((sizetmp == 0)&&(Size!=0))
+ if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
{
- /* Wait until TXE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ /* Wait until TCR flag is set */
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(Size > 255)
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
-
- }while(Size > 0);
+ }
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -595,6 +727,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -609,9 +742,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/**
* @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -619,78 +753,87 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t sizetmp = 0;
+ uint32_t tickstart = 0;
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_BUSY;
+ return HAL_TIMEOUT;
}
- /* Process Locked */
- __HAL_LOCK(hi2c);
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
/* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- /* Size > 255, need to set RELOAD bit */
- if(Size > 255)
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
- do
+ while(hi2c->XferSize > 0)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
}
- /* Write data to RXDR */
- (*pData++) =hi2c->Instance->RXDR;
- sizetmp--;
- Size--;
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
- if((sizetmp == 0)&&(Size!=0))
+ if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(Size > 255)
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
-
- }while(Size > 0);
+ }
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -709,6 +852,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -723,8 +867,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/**
* @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -732,24 +876,34 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
-
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -763,7 +917,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -775,17 +929,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Wait until DIR flag is set Transmitter mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
- do
+ while(hi2c->XferCount > 0)
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -800,22 +954,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
}
- /* Read data from TXDR */
- hi2c->Instance->TXDR = (*pData++);
- Size--;
- }while(Size > 0);
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
else
{
@@ -827,7 +981,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -838,6 +992,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -852,8 +1007,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/**
* @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -861,24 +1016,34 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
-
- /* Process Locked */
+ /* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -889,20 +1054,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
/* Wait until DIR flag is reset Receiver mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(Size > 0)
+ while(hi2c->XferCount > 0)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferCount--;
+ }
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -914,12 +1088,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
}
/* Read data from RXDR */
- (*pData++) = hi2c->Instance->RXDR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferCount--;
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -938,18 +1112,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
-
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -963,23 +1137,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
}
/**
- * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ uint32_t xfermode = 0;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
@@ -988,30 +1160,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
- }
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1020,11 +1192,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
to avoid the risk of I2C interrupt handle execution before current
process unlock */
-
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
@@ -1035,23 +1206,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
}
/**
- * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ uint32_t xfermode = 0;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
@@ -1060,30 +1229,30 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1095,7 +1264,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI );
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
}
@@ -1106,9 +1275,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
}
/**
- * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1117,23 +1286,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1145,7 +1313,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_TXI );
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
@@ -1156,9 +1324,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
}
/**
- * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1167,23 +1335,22 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
{
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1195,7 +1362,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI);
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
@@ -1206,23 +1373,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
}
/**
- * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ uint32_t xfermode = 0;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
@@ -1231,18 +1396,25 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MASTER_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
/* Set the I2C DMA transfer complete callback */
@@ -1251,43 +1423,32 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
/* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
- }
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
return HAL_OK;
}
else
@@ -1297,23 +1458,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
}
/**
- * @brief Receive in master mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ uint32_t xfermode = 0;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
@@ -1322,53 +1481,69 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MASTER_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+ if(hi2c->XferSize > 0)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ }
return HAL_OK;
}
else
@@ -1378,9 +1553,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
}
/**
- * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1396,12 +1571,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- hi2c->XferSize = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
@@ -1409,51 +1588,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* If 10bits addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- {
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
- }
-
- /* Wait until DIR flag is set Transmitter mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, I2C_TIMEOUT_BUSY) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
return HAL_OK;
}
@@ -1464,9 +1619,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
}
/**
- * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1482,12 +1637,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
@@ -1495,37 +1654,28 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, Size);
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Wait until DIR flag is set Receiver mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, I2C_TIMEOUT_DIR) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
- }
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
return HAL_OK;
}
else
@@ -1535,8 +1685,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
}
/**
* @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1547,7 +1697,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t Sizetmp = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1559,19 +1709,28 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1587,23 +1746,22 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
}
- /* Set NBYTES to write and reload if size > 255 */
- /* Size > 255, need to set RELOAD bit */
- if(Size > 255)
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- Sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- Sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
do
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1615,37 +1773,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
}
- /* Write data to DR */
- hi2c->Instance->TXDR = (*pData++);
- Sizetmp--;
- Size--;
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
- if((Sizetmp == 0)&&(Size!=0))
+ if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
- if(Size > 255)
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- Sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- Sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
- }while(Size > 0);
+ }while(hi2c->XferCount > 0);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1664,6 +1821,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1678,8 +1836,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/**
* @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1690,7 +1848,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t Sizetmp = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1702,19 +1860,28 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
- {
- return HAL_BUSY;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferISR = NULL;
+
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1731,59 +1898,55 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
/* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- /* Size > 255, need to set RELOAD bit */
- if(Size > 255)
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- Sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- Sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
do
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Read data from RXDR */
- (*pData++) = hi2c->Instance->RXDR;
-
- /* Decrement the Size counter */
- Sizetmp--;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
- if((Sizetmp == 0)&&(Size!=0))
+ if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(Size > 255)
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- Sizetmp = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,Size, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- Sizetmp = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
-
- }while(Size > 0);
+ }while(hi2c->XferCount > 0);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1802,6 +1965,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1814,9 +1978,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
}
}
/**
- * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1826,6 +1990,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ uint32_t tickstart = 0;
+ uint32_t xfermode = 0;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1844,22 +2011,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1875,16 +2052,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
}
- /* Set NBYTES to write and reload if size > 255 */
- /* Size > 255, need to set RELOAD bit */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1896,7 +2065,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- __HAL_I2C_ENABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
@@ -1907,9 +2076,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/**
- * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1919,6 +2088,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ uint32_t tickstart = 0;
+ uint32_t xfermode = 0;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1937,21 +2109,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1967,16 +2150,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
}
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- /* Size > 255, need to set RELOAD bit */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1988,7 +2163,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
}
@@ -1998,9 +2173,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
}
/**
- * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2010,6 +2185,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ uint32_t tickstart = 0;
+ uint32_t xfermode = 0;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2028,31 +2206,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -2068,36 +2247,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
}
}
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
- }
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
return HAL_OK;
}
else
@@ -2107,9 +2288,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
}
/**
- * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2119,6 +2300,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ uint32_t tickstart = 0;
+ uint32_t xfermode = 0;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2137,30 +2321,32 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
- if(Size > 255)
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
else
{
- hi2c->XferSize = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
-
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -2176,28 +2362,37 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
}
- /* Set NBYTES to write and reload if size > 255 and generate RESTART */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
- }
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
return HAL_OK;
}
else
@@ -2209,8 +2404,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/**
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param Trials: Number of trials
* @param Timeout: Timeout duration
@@ -2262,7 +2457,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
{
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2281,7 +2476,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
else
{
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2300,7 +2495,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
hi2c->Instance->CR2 |= I2C_CR2_STOP;
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2322,204 +2517,629 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
return HAL_BUSY;
}
}
-/**
- * @}
- */
-
-/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
/**
- * @brief This function handles I2C event interrupt request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
*/
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- /* I2C in mode Transmitter ---------------------------------------------------*/
- if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI | I2C_IT_ADDRI)) == SET))
- {
- /* Slave mode selected */
- if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX)
- {
- I2C_SlaveTransmit_ISR(hi2c);
- }
- }
+ uint32_t xfermode = 0;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI)) == SET))
+ if(hi2c->State == HAL_I2C_STATE_READY)
{
- /* Master mode selected */
- if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX))
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* If size > MAX_NBYTE_SIZE, use reload mode */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_MasterTransmit_ISR(hi2c);
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
}
- }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
- /* I2C in mode Receiver ----------------------------------------------------*/
- if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI | I2C_IT_ADDRI)) == SET))
- {
- /* Slave mode selected */
- if (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX)
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
{
- I2C_SlaveReceive_ISR(hi2c);
+ xferrequest = I2C_NO_STARTSTOP;
}
+
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ return HAL_OK;
}
- if (((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) || (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)) && (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI)) == SET))
+ else
{
- /* Master mode selected */
- if ((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
- {
- I2C_MasterReceive_ISR(hi2c);
- }
+ return HAL_BUSY;
}
}
/**
- * @brief This function handles I2C error interrupt request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval None
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
*/
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- /* I2C Bus error interrupt occurred ------------------------------------*/
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+ uint32_t xfermode = 0;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
- /* Clear BERR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
- }
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
+ if(hi2c->State == HAL_I2C_STATE_READY)
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
- /* Clear OVR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
- }
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERRI) == SET))
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_IT;
- /* Clear ARLO flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
}
+}
- /* Call the Error Callback in case of Error detected */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData: Pointer to data buffer
+ * @param Size: Amount of data to be sent
+ * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
+
+ /* Enable the Address Match interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
{
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Disable the Address Match interrupt */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ /* Set State at HAL_I2C_STATE_ABORT */
+ hi2c->State = HAL_I2C_STATE_ABORT;
+
+ /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
+ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
+ I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles I2C event interrupt request.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ /* Get current IT Flags and IT sources value */
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+ /* I2C events treatment -------------------------------------*/
+ if(hi2c->XferISR != NULL)
+ {
+ hi2c->XferISR(hi2c, itflags, itsources);
+ }
+}
+
+/**
+ * @brief This function handles I2C error interrupt request.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ uint32_t itflags = READ_REG(hi2c->Instance->ISR);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+
+ /* I2C Bus error interrupt occurred ------------------------------------*/
+ if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ }
+
+ /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ }
+
+ /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+ if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ {
+ hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ {
+ I2C_ITError(hi2c, hi2c->ErrorCode);
}
}
/**
- * @brief Master Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Master Tx Transfer completed callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Master Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Master Rx Transfer completed callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
*/
}
-/** @brief Slave Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+/** @brief Slave Tx Transfer completed callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Slave Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Slave Rx Transfer completed callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
+ * @param AddrMatchCode: Address Match Code
+ * @retval None
+ */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AddrCallback() could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback() could be implemented in the user file
*/
}
/**
- * @brief Memory Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Memory Tx Transfer completed callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemTxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Memory Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Memory Rx Transfer completed callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_MemRxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief I2C error callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief I2C error callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback could be implemented in the user file
*/
}
+/**
+ * @brief I2C abort callback.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file
+ */
+}
+
/**
* @}
*/
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State, Mode and Error functions
*
@verbatim
===============================================================================
- ##### Peripheral State and Errors functions #####
+ ##### Peripheral State, Mode and Error functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
@@ -2530,19 +3150,31 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
*/
/**
- * @brief Returns the I2C state.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Return the I2C handle state.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
+ /* Return I2C handle state */
return hi2c->State;
}
/**
- * @brief Return the I2C error code
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * @brief Returns the I2C Master, Slave, Memory or no mode.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL mode
+ */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->Mode;
+}
+
+/**
+* @brief Return the I2C error code.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
@@ -2564,104 +3196,109 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
*/
/**
- * @brief Handle Interrupt Flags Master Transmit Mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags: Interrupt flags to handle.
+ * @param ITSources: Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t DevAddress;
+ uint16_t devaddress = 0;
/* Process Locked */
__HAL_LOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
- {
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
- if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ {
+ if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
{
- DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
- if(hi2c->XferCount > 255)
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- hi2c->XferSize = 255;
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
hi2c->XferSize = hi2c->XferCount;
+ if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
}
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Wrong size Status regarding TCR flag event */
- hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Call TxCpltCallback() if no stop mode is set */
+ if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSequentialCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
}
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
+ else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
if(hi2c->XferCount == 0)
{
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSequentialCplt(hi2c);
+ }
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Wrong size Status regarding TCR flag event */
- hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Wrong size Status regarding TC flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- {
- /* Disable ERR, TC, STOP, NACK, TXI interrupt */
- __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_TXI );
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
- {
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
- else
- {
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
- }
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
}
/* Process Unlocked */
@@ -2671,192 +3308,200 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Handle Interrupt Flags Master Receive Mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags: Interrupt flags to handle.
+ * @param ITSources: Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c)
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t DevAddress;
-
- /* Process Locked */
+ /* Process locked */
__HAL_LOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TCR) == SET)
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
- if((hi2c->XferSize == 0)&&(hi2c->XferCount!=0))
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0*/
+ /* So clear Flag NACKF only */
+ if(hi2c->XferCount == 0)
{
- DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- if(hi2c->XferCount > 255)
+ if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
+ (hi2c->State == HAL_I2C_STATE_LISTEN))
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
- I2C_TransferConfig(hi2c,DevAddress,255, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- hi2c->XferSize = 255;
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSequentialCplt(hi2c);
}
else
{
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferCount, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- hi2c->XferSize = hi2c->XferCount;
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Wrong size Status regarding TCR flag event */
- hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TC) == SET)
+ else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
{
- if(hi2c->XferCount == 0)
+ if(hi2c->XferCount > 0)
{
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- /* Wrong size Status regarding TCR flag event */
- hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
- HAL_I2C_ErrorCallback(hi2c);
- }
+ if((hi2c->XferCount == 0) && \
+ (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSequentialCplt(hi2c);
+ }
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
{
- /* Disable ERR, TC, STOP, NACK, TXI interrupt */
- __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_RXI );
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+ I2C_ITAddrCplt(hi2c, ITFlags);
+ }
+ else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ {
+ /* Write data to TXDR only if XferCount not reach "0" */
+ /* A TXIS flag can be set, during STOP treatment */
+ /* Check if all Datas have already been sent */
+ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+ if(hi2c->XferCount > 0)
{
- HAL_I2C_MemRxCpltCallback(hi2c);
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
}
else
{
- HAL_I2C_MasterRxCpltCallback(hi2c);
+ if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSequentialCplt(hi2c);
+ }
}
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Check if STOPF is set */
+ if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
-
}
/**
- * @brief Handle Interrupt Flags Slave Transmit Mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags: Interrupt flags to handle.
+ * @param ITSources: Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- /* Process locked */
+ uint16_t devaddress = 0;
+ uint32_t xfermode = 0;
+
+ /* Process Locked */
__HAL_LOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
- /* Check that I2C transfer finished */
- /* if yes, normal usecase, a NACK is sent by the MASTER when Transfer is finished */
- /* Mean XferCount == 0*/
- /* So clear Flag NACKF only */
- if(hi2c->XferCount == 0)
- {
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- }
- else
- {
- /* if no, error usecase, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
- /* Call the Error callback to prevent upper layer */
- HAL_I2C_ErrorCallback(hi2c);
- }
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- }
- /* Check first if STOPF is set */
- /* to prevent a Write Data in TX buffer */
- /* which is stuck in TXDR until next */
- /* communication with Master */
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- {
- /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
- __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI );
+ /* Disable TC interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ if(hi2c->XferCount != 0)
+ {
+ /* Recover Slave address */
+ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Prepare the new XferSize to transfer */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = I2C_AUTOEND_MODE;
+ }
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Set the new XferSize in Nbytes register */
+ I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == SET)
- {
- /* Write data to TXDR only if XferCount not reach "0" */
- /* A TXIS flag can be set, during STOP treatment */
- if(hi2c->XferCount > 0)
+ /* Enable DMA Request */
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
{
- /* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
+ else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2865,56 +3510,48 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_ISR(I2C_HandleTypeDef *hi2c)
}
/**
- * @brief Handle Interrupt Flags Slave Receive Mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags: Interrupt flags to handle.
+ * @param ITSources: Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- /* Process Locked */
+ /* Process locked */
__HAL_LOCK(hi2c);
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) != RESET)
+ if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+ /* So clear Flag NACKF only */
+ if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+ else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- hi2c->XferSize--;
- hi2c->XferCount--;
- }
- else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
- /* Disable ERRI, TCI, STOPI, NACKI, ADDRI, RXI, TXI interrupt */
- __HAL_I2C_DISABLE_IT(hi2c,I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_RXI );
-
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- HAL_I2C_SlaveRxCpltCallback(hi2c);
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
}
/* Process Unlocked */
@@ -2925,20 +3562,21 @@ static HAL_StatusTypeDef I2C_SlaveReceive_ISR(I2C_HandleTypeDef *hi2c)
/**
* @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
* @param Timeout: Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -2963,7 +3601,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -2980,7 +3618,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
}
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2990,20 +3628,21 @@ return HAL_OK;
/**
* @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
* @param Timeout: Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3028,7 +3667,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3045,7 +3684,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* Wait until TC flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3054,748 +3693,642 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/**
- * @brief DMA I2C master transmit process complete callback.
- * @param hdma: DMA handle
+ * @brief I2C Address complete process callback.
+ * @param hi2c: I2C handle.
+ * @param ITFlags: Interrupt flags to handle.
* @retval None
*/
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
- uint16_t DevAddress;
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ uint8_t transferdirection = 0;
+ uint16_t slaveaddrcode = 0;
+ uint16_t ownadd1code = 0;
+ uint16_t ownadd2code = 0;
- /* Check if last DMA request was done with RELOAD */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ /* In case of Listen state, need to inform upper layer of address match code event */
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ transferdirection = I2C_GET_DIR(hi2c);
+ slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
+ ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
+ ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ /* If 10bits addressing mode is selected */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ slaveaddrcode = ownadd1code;
+ hi2c->AddrEventCount++;
+ if(hi2c->AddrEventCount == 2)
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
+ /* Reset Address Event counter */
+ hi2c->AddrEventCount = 0;
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->XferCount = 0;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- hi2c->pBuffPtr += hi2c->XferSize;
- hi2c->XferCount -= hi2c->XferSize;
- if(hi2c->XferCount > 255)
- {
- hi2c->XferSize = 255;
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ }
}
else
{
- hi2c->XferSize = hi2c->XferCount;
- }
+ slaveaddrcode = ownadd2code;
- DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
}
+ }
+ /* else 7 bits addressing mode is selected */
+ else
+ {
+ /* Disable ADDR Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
- {
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->XferCount = 0;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
}
}
+ /* Else clear address flag only */
else
{
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
}
}
/**
- * @brief DMA I2C slave transmit process complete callback.
- * @param hdma: DMA handle
+ * @brief I2C Master sequential complete process.
+ * @param hi2c: I2C handle.
* @retval None
*/
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal Use case, a AF is generated by master */
- /* to inform slave the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ /* No Generate Stop, to permit restart mode */
+ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->XferISR = NULL;
- hi2c->XferCount = 0;
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MasterTxCpltCallback(hi2c);
}
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
else
{
- HAL_I2C_SlaveTxCpltCallback(hi2c);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ hi2c->XferISR = NULL;
+
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MasterRxCpltCallback(hi2c);
}
}
/**
- * @brief DMA I2C master receive process complete callback
- * @param hdma: DMA handle
+ * @brief I2C Slave sequential complete process.
+ * @param hi2c: I2C handle.
* @retval None
*/
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- uint16_t DevAddress;
+ /* Reset I2C handle mode */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Check if last DMA request was done with RELOAD */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
- hi2c->XferCount = 0;
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- hi2c->pBuffPtr += hi2c->XferSize;
- hi2c->XferCount -= hi2c->XferSize;
- if(hi2c->XferCount > 255)
- {
- hi2c->XferSize = 255;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+}
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
+/**
+ * @brief I2C Master complete process.
+ * @param hi2c: I2C handle.
+ * @param ITFlags: Interrupt flags to handle.
+ * @retval None
+ */
+static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
+ /* Reset handle parameters */
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->XferISR = NULL;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ if((ITFlags & I2C_FLAG_AF) != RESET)
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Set acknowledge error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
- hi2c->XferCount = 0;
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Disable Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
}
- else
+ /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
+ hi2c->State = HAL_I2C_STATE_READY;
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- hi2c->XferCount = 0;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
hi2c->State = HAL_I2C_STATE_READY;
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
- HAL_I2C_ErrorCallback(hi2c);
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
}
else
{
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
HAL_I2C_MasterRxCpltCallback(hi2c);
}
}
}
/**
- * @brief DMA I2C slave receive process complete callback.
- * @param hdma: DMA handle
+ * @brief I2C Slave complete process.
+ * @param hi2c: I2C handle.
+ * @param ITFlags: Interrupt flags to handle.
* @retval None
*/
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+
+ /* Disable all interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* If a DMA is ongoing, Update handle size context */
+ if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
+ ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize)
{
+ hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c);
+ hi2c->XferCount += hi2c->XferSize;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- else
+ }
+
+ /* Store Last receive data if any */
+ if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+
+ if((hi2c->XferSize > 0))
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- /* Clear STOPF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY) != HAL_OK)
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->State = HAL_I2C_STATE_READY;
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->State = HAL_I2C_STATE_READY;
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- hi2c->XferCount = 0;
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
+ /* Call the Slave Rx Complete callback */
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
}
else
{
- HAL_I2C_SlaveRxCpltCallback(hi2c);
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the Slave Tx Complete callback */
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
}
}
/**
- * @brief DMA I2C Memory Write process complete callback
- * @param hdma : DMA handle
+ * @brief I2C Listen complete process.
+ * @param hi2c: I2C handle.
+ * @param ITFlags: Interrupt flags to handle.
* @retval None
*/
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
- uint16_t DevAddress;
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Reset handle parameters */
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferISR = NULL;
- /* Check if last DMA request was done with RELOAD */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ /* Store Last receive data if any */
+ if(((ITFlags & I2C_FLAG_RXNE) != RESET))
{
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ /* Read data from RXDR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if((hi2c->XferSize > 0))
{
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->XferCount = 0;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- else
- {
- hi2c->pBuffPtr += hi2c->XferSize;
- hi2c->XferCount -= hi2c->XferSize;
- if(hi2c->XferCount > 255)
- {
- hi2c->XferSize = 255;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
+ }
- DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ /* Disable all Interrupts*/
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
-
- /* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, I2C_TIMEOUT_TXIS) != HAL_OK)
- {
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+}
- hi2c->XferCount = 0;
+/**
+ * @brief I2C interrupts error process.
+ * @param hi2c: I2C handle.
+ * @param ErrorCode: Error code to handle.
+ * @retval None
+ */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+ /* Reset handle parameters */
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferCount = 0;
+
+ /* Set new error code */
+ hi2c->ErrorCode |= ErrorCode;
+
+ /* Disable Interrupts */
+ if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Disable all interrupts, except interrupts related to LISTEN state */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- }
+ /* keep HAL_I2C_STATE_LISTEN if set */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
{
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
+ /* Disable all interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Set HAL_I2C_STATE_READY */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->XferISR = NULL;
+ }
- /* Disable DMA Request */
+ /* Abort DMA TX transfer if any */
+ if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
- hi2c->XferCount = 0;
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_MemTxCpltCallback(hi2c);
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
-}
-
-/**
- * @brief DMA I2C Memory Read process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- uint16_t DevAddress;
-
- /* Check if last DMA request was done with RELOAD */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
+ /* Abort DMA RX transfer if any */
+ else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
- /* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, I2C_TIMEOUT_TCR) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- hi2c->pBuffPtr += hi2c->XferSize;
- hi2c->XferCount -= hi2c->XferSize;
- if(hi2c->XferCount > 255)
- {
- hi2c->XferSize = 255;
- }
- else
- {
- hi2c->XferSize = hi2c->XferCount;
- }
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
- DevAddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
+ {
+ hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if size > 255 */
- if( (hi2c->XferSize == 255) && (hi2c->XferSize < hi2c->XferCount) )
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
- }
- else
- {
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, I2C_TIMEOUT_RXNE) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+}
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+/**
+ * @brief I2C Tx data register flush process.
+ * @param hi2c: I2C handle.
+ * @retval None
+ */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+ /* If a pending TXIS flag is set */
+ /* Write a dummy data in TXDR to clear it */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ {
+ hi2c->Instance->TXDR = 0x00;
+ }
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Flush TX register if not empty */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ }
+}
- hi2c->XferCount = 0;
+/**
+ * @brief DMA I2C master transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
- }
- }
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* If last transfer, enable STOP interrupt */
+ if(hi2c->XferCount == 0)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
}
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
else
{
- /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_STOPF) != HAL_OK)
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
+
+ /* Set the XferSize to transfer */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
}
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
+}
- /* Disable DMA Request */
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+/**
+ * @brief DMA I2C slave transmit process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+}
+
+/**
+ * @brief DMA I2C master receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- hi2c->XferCount = 0;
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* If last transfer, enable STOP interrupt */
+ if(hi2c->XferCount == 0)
+ {
+ /* Enable STOP interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+ }
+ /* else prepare a new DMA transfer and enable TCReload interrupt */
+ else
+ {
+ /* Update Buffer pointer */
+ hi2c->pBuffPtr += hi2c->XferSize;
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ /* Set the XferSize to transfer */
+ if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
- HAL_I2C_ErrorCallback(hi2c);
+ hi2c->XferSize = MAX_NBYTE_SIZE;
}
else
{
- HAL_I2C_MemRxCpltCallback(hi2c);
+ hi2c->XferSize = hi2c->XferCount;
}
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
}
}
+/**
+ * @brief DMA I2C slave receive process complete callback.
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+}
+
/**
* @brief DMA I2C communication error callback.
- * @param hdma : DMA handle
+ * @param hdma: DMA handle
* @retval None
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
@@ -3805,60 +4338,67 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- hi2c->XferCount = 0;
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+}
- hi2c->State = HAL_I2C_STATE_READY;
+/**
+ * @brief DMA I2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+ /* Reset AbortCpltCallback */
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- HAL_I2C_ErrorCallback(hi2c);
+ /* Check if come from abort from user */
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
+ {
+ hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
}
/**
* @brief This function handles I2C Communication Timeout.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Flag: specifies the I2C flag to check.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param Flag: Specifies the I2C flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hi2c->State= HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hi2c->State= HAL_I2C_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
}
}
}
@@ -3867,19 +4407,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
/**
* @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = HAL_GetTick();
-
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
@@ -3887,10 +4426,11 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3904,29 +4444,28 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/**
* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0x00;
- tickstart = HAL_GetTick();
-
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout) != HAL_OK)
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3939,18 +4478,22 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/**
* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0x00;
- tickstart = HAL_GetTick();
-
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
+ /* Check if a NACK is detected */
+ if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check if a STOPF is detected */
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
@@ -3962,6 +4505,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3970,7 +4514,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
@@ -3986,31 +4530,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
/**
* @brief This function handles Acknowledge failed detection during an I2C Communication.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0x00;
- tickstart = HAL_GetTick();
-
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
- /* Generate stop if necessary only in case of I2C peripheral in MASTER mode */
- if((hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
- || (hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX))
- {
- /* No need to generate the STOP condition if AUTOEND mode is enabled */
- /* Generate the STOP condition only in case of SOFTEND mode is enabled */
- if((hi2c->Instance->CR2 & I2C_AUTOEND_MODE) != I2C_AUTOEND_MODE)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
- }
-
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
@@ -4018,9 +4547,11 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_TIMEOUT;
@@ -4034,11 +4565,15 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -4051,20 +4586,13 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hi2c: I2C handle.
- * @param DevAddress: specifies the slave address to be programmed.
- * @param Size: specifies the number of bytes to be programmed.
+ * @param DevAddress: Specifies the slave address to be programmed.
+ * @param Size: Specifies the number of bytes to be programmed.
* This parameter must be a value between 0 and 255.
- * @param Mode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_RELOAD_MODE: Enable Reload mode .
- * @arg I2C_AUTOEND_MODE: Enable Automatic end mode.
- * @arg I2C_SOFTEND_MODE: Enable Software end mode.
- * @param Request: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_NO_STARTSTOP: Don't Generate stop and start condition.
- * @arg I2C_GENERATE_STOP: Generate stop condition (Size should be set to 0).
- * @arg I2C_GENERATE_START_READ: Generate Restart for read request.
- * @arg I2C_GENERATE_START_WRITE: Generate Restart for write request.
+ * @param Mode: New state of the I2C START condition generation.
+ * This parameter can be a value of @ref I2C_RELOAD_END_MODE.
+ * @param Request: New state of the I2C START condition generation.
+ * This parameter can be a value of I2C_START_STOP_MODE.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
@@ -4091,8 +4619,144 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
}
/**
- * @}
+ * @brief Manage the enabling of Interrupts.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0;
+
+ if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ {
+ if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+
+ if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+ else
+ {
+ if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK, and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+ }
+
+ /* Enable interrupts only at the end */
+ /* to avoid the risk of I2C interrupt handle execution before */
+ /* all interrupts requested done */
+ __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Manage the disabling of Interrupts.
+ * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
+ * @retval HAL status
*/
+static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ uint32_t tmpisr = 0;
+
+ if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Disable TC and TXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Disable TC and RXI interrupts */
+ tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ {
+ /* Disable NACK and STOP interrupts */
+ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+ }
+
+ if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Disable ADDR, NACK and STOP interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= I2C_IT_STOPI;
+ }
+
+ if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+
+ /* Disable interrupts only at the end */
+ /* to avoid a breaking situation like at "t" time */
+ /* all disable interrupts request are not done */
+ __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+
+ return HAL_OK;
+}
/**
* @}
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c b/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c
index f0fd09a07..9d56dbf77 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_i2s.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -379,6 +379,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
*/
@@ -392,6 +395,9 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
*/
@@ -526,7 +532,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
{
/* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
{
/* Set the error code and execute error callback*/
hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
@@ -1202,6 +1208,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
*/
@@ -1215,6 +1224,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
@@ -1228,6 +1240,9 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
@@ -1241,6 +1256,9 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
@@ -1254,6 +1272,9 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
*/
@@ -1326,7 +1347,7 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
/* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
switch(hi2s->Init.ClockSource)
{
- case I2S_CLOCK_SYSCLK :
+ case I2S_CLOCK_PLL :
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c b/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c
index 1e132b9e8..09943a6a8 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -24,12 +24,12 @@
(#) Fill parameters of Init structure in HCD handle
- (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
- (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+ (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -38,14 +38,14 @@
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
- (#)Enable HCD transmission and reception:
+ (#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State= HAL_PCD_STATE_READY;
/* Activate LPM */
- if (hpcd->Init.lpm_enable == 1)
+ if (hpcd->Init.lpm_enable ==1)
{
HAL_PCDEx_ActivateLPM(hpcd);
}
@@ -203,7 +203,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief DeInitializes the PCD peripheral
+ * @brief DeInitializes the PCD peripheral.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -235,6 +235,9 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
@@ -247,6 +250,9 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implemented in the user file
*/
@@ -256,7 +262,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @}
*/
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
@@ -301,7 +307,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief This function handles PCD interrupt request.
+ * @brief Handle PCD interrupt request.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -310,7 +316,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
uint32_t fifoemptymsk = 0, temp = 0;
- USB_OTG_EPTypeDef *ep;
+ USB_OTG_EPTypeDef *ep = NULL;
+ uint32_t hclk = 200000000;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -372,6 +379,11 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
+ /* Clear Status Phase Received interrupt */
+ if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+ {
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+ }
}
epnum++;
ep_intr >>= 1;
@@ -462,7 +474,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Suspend Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
-
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
@@ -508,7 +519,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
else
{
- USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+ USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
}
@@ -537,7 +548,74 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
+
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+ latency to the Data FIFO */
+
+ /* Get hclk frequency value */
+ hclk = HAL_RCC_GetHCLKFreq();
+
+ if((hclk >= 14200000)&&(hclk < 15000000))
+ {
+ /* hclk Clock Range between 14.2-15 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 15000000)&&(hclk < 16000000))
+ {
+ /* hclk Clock Range between 15-16 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 16000000)&&(hclk < 17200000))
+ {
+ /* hclk Clock Range between 16-17.2 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 17200000)&&(hclk < 18500000))
+ {
+ /* hclk Clock Range between 17.2-18.5 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 18500000)&&(hclk < 20000000))
+ {
+ /* hclk Clock Range between 18.5-20 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 20000000)&&(hclk < 21800000))
+ {
+ /* hclk Clock Range between 20-21.8 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 21800000)&&(hclk < 24000000))
+ {
+ /* hclk Clock Range between 21.8-24 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 24000000)&&(hclk < 27700000))
+ {
+ /* hclk Clock Range between 24-27.7 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else if((hclk >= 27700000)&&(hclk < 32000000))
+ {
+ /* hclk Clock Range between 27.7-32 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
+
+ else /* if(hclk >= 32000000) */
+ {
+ /* hclk Clock Range between 32-200 MHz */
+ hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
+ }
}
HAL_PCD_ResetCallback(hpcd);
@@ -612,136 +690,168 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Data out stage callbacks
+ * @brief Data OUT stage callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
- * @brief Data IN stage callbacks
+ * @brief Data IN stage callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
- * @brief Setup stage callback
+ * @brief Setup stage callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
/**
- * @brief USB Start Of Frame callbacks
+ * @brief USB Start Of Frame callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
/**
- * @brief USB Reset callbacks
+ * @brief USB Reset callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
-
/**
- * @brief Suspend event callbacks
+ * @brief Suspend event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
/**
- * @brief Resume event callbacks
+ * @brief Resume event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO OUT callbacks
+ * @brief Incomplete ISO OUT callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Incomplete ISO IN callbacks
+ * @brief Incomplete ISO IN callback.
* @param hpcd: PCD handle
* @param epnum: endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
/**
- * @brief Connection event callbacks
+ * @brief Connection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
/**
- * @brief Disconnection event callbacks
+ * @brief Disconnection event callback.
* @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
@@ -767,7 +877,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Connect the USB device
+ * @brief Connect the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -780,7 +890,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Disconnect the USB device
+ * @brief Disconnect the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -793,7 +903,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief Set the USB Device address
+ * @brief Set the USB Device address.
* @param hpcd: PCD handle
* @param address: new device address
* @retval HAL status
@@ -806,7 +916,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
return HAL_OK;
}
/**
- * @brief Open and configure an endpoint
+ * @brief Open and configure an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param ep_mps: endpoint max packet size
@@ -850,7 +960,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/**
- * @brief Deactivate an endpoint
+ * @brief Deactivate an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -879,7 +989,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
- * @brief Receive an amount of data
+ * @brief Receive an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the reception buffer
@@ -920,7 +1030,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
/**
- * @brief Get Received Data Size
+ * @brief Get Received Data Size.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval Data Size
@@ -930,7 +1040,7 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
}
/**
- * @brief Send an amount of data
+ * @brief Send an amount of data.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param pBuf: pointer to the transmission buffer
@@ -972,7 +1082,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
/**
- * @brief Set a STALL condition over an endpoint
+ * @brief Set a STALL condition over an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -1007,7 +1117,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Clear a STALL condition over in an endpoint
+ * @brief Clear a STALL condition over in an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -1037,7 +1147,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief Flush an endpoint
+ * @brief Flush an endpoint.
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
@@ -1061,7 +1171,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
- * @brief HAL_PCD_ActivateRemoteWakeup : Active remote wake-up signalling
+ * @brief Activate remote wakeup signalling.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -1071,14 +1181,14 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
- /* Activate Remote wake-up signaling */
+ /* Activate Remote wakeup signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
return HAL_OK;
}
/**
- * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wake-up signalling
+ * @brief De-activate remote wakeup signalling.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -1086,7 +1196,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- /* De-activate Remote wake-up signaling */
+ /* De-activate Remote wakeup signaling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
}
@@ -1110,7 +1220,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief Return the PCD state
+ * @brief Return the PCD handle state.
* @param hpcd: PCD handle
* @retval HAL state
*/
@@ -1132,8 +1242,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
*/
/**
- * @brief DCD_WriteEmptyTxFifo
- * check FIFO for the next packet to be loaded
+ * @brief Check FIFO for the next packet to be loaded.
* @param hpcd: PCD handle
* @param epnum : endpoint number
* @retval HAL status
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c
index 69b0d5ad1..12fca1745 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,7 +103,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
if(fifo == 0)
{
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
else
{
@@ -114,8 +114,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin
}
/* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
-
+ hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
return HAL_OK;
@@ -135,7 +134,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
}
/**
- * @brief HAL_PCDEx_ActivateLPM : active LPM Feature
+ * @brief Activate LPM Feature
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -152,7 +151,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief HAL_PCDEx_DeActivateLPM : de-active LPM feature
+ * @brief DeActivate LPM feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -168,13 +167,20 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
}
/**
- * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer
+ * @brief Send LPM message to user layer callback.
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PCDEx_LPM_Callback could be implemented in the user file
+ */
}
/**
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c b/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c
index 6d7d5660b..e8258192f 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,10 +63,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
-#define PVD_MODE_IT ((uint32_t)0x00010000)
-#define PVD_MODE_EVT ((uint32_t)0x00020000)
-#define PVD_RISING_EDGE ((uint32_t)0x00000001)
-#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+#define PVD_MODE_IT ((uint32_t)0x00010000U)
+#define PVD_MODE_EVT ((uint32_t)0x00020000U)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
/**
* @}
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c
index 19ca4c8ce..e77873b40 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -157,6 +157,10 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
/* Enable Backup regulator */
PWR->CSR1 |= PWR_CSR1_BRE;
+ /* Workaround for the following hardware bug: */
+ /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
+ PWR->CSR1 |= PWR_CSR1_EIWUP;
+
/* Get tick */
tickstart = HAL_GetTick();
@@ -182,6 +186,10 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
/* Disable Backup regulator */
PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
+ /* Workaround for the following hardware bug: */
+ /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
+ PWR->CSR1 |= PWR_CSR1_EIWUP;
+
/* Get tick */
tickstart = HAL_GetTick();
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c
index e62c5e051..f8f51d01f 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -56,7 +56,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -119,7 +119,6 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
-const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@@ -227,7 +226,7 @@ void HAL_RCC_DeInit(void)
/* Reset PLLCFGR register */
CLEAR_REG(RCC->PLLCFGR);
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
+ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
/* Reset PLLI2SCFGR register */
CLEAR_REG(RCC->PLLI2SCFGR);
@@ -238,6 +237,9 @@ void HAL_RCC_DeInit(void)
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
}
/**
@@ -246,6 +248,12 @@ void HAL_RCC_DeInit(void)
* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+ * supported by this function. User should request a transition to LSE Off
+ * first and then LSE On or LSE Bypass.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this function. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@@ -271,21 +279,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
- /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
- __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
@@ -450,21 +443,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
- /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
- __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@@ -513,6 +491,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+#if defined (RCC_PLLCFGR_PLLR)
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
@@ -530,11 +511,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Configure the main PLL clock source, multiplication and division factors. */
+#if defined (RCC_PLLCFGR_PLLR)
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PLLM,
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
+#endif
+
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
@@ -611,8 +602,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
assert_param(IS_FLASH_LATENCY(FLatency));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
@@ -626,161 +617,87 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
return HAL_ERROR;
}
+ }
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
- /* HSI is selected as System Clock Source */
- else
+ }
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
+ }
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
+ __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
- }
- /* Decreasing the CPU frequency */
- else
- {
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration -------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- return HAL_ERROR;
- }
- }
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
- else
+ }
+ else
+ {
+ while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
+ }
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
@@ -790,7 +707,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
return HAL_ERROR;
}
- }
+ }
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
@@ -806,6 +723,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@@ -981,12 +901,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
{
/* HSE used as PLL clock source */
- //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
- // dpgeorge: Adjust the way the arithmetic is done so it retains
- // precision for the case that pllm doesn't evenly divide HSE_VALUE.
- // Must be sure not to overflow, so divide by 4 first. HSE_VALUE
- // should be a multiple of 4 (being a multiple of 100 is enough).
- pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
+ pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
}
else
{
@@ -1011,14 +926,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
* @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated within this function
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
return SystemCoreClock;
}
@@ -1031,7 +943,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
}
/**
@@ -1043,7 +955,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
}
/**
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c
index e04960d33..0cc2395f4 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -109,17 +109,19 @@
@endverbatim
* @{
*/
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
- * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
+ * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
*
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
* the RTC clock source; in this case the Backup domain will be reset in
* order to modify the RTC Clock source, as consequence RTC registers (including
- * the backup registers) and RCC_BDCR register are set to their reset values.
+ * the backup registers) are set to their reset values.
*
* @retval HAL status
*/
@@ -200,27 +202,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
+ /* Check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
+ /* Enable write access to Backup domain */
+ PWR->CR1 |= PWR_CR1_DBP;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
- /* Wait for Backup domain Write protection disable */
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ /* Wait for Backup domain Write protection disable */
+ while((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+ if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+ {
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -231,8 +238,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
+ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@@ -246,8 +253,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*------------------------------------ TIM configuration --------------------------------------*/
@@ -407,12 +414,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
{
pllsaiused = 1;
}
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
{
@@ -423,7 +431,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
}
- /*------------------------------------- SDMMC Configuration ------------------------------------*/
+ /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
{
/* Check the parameters */
@@ -433,6 +441,38 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
}
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+ /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
+
+ /* Configure the SDMMC2 clock source */
+ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
+ }
+
+ /*------------------------------------- DFSDM1 Configuration -------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+ /* Configure the DFSDM1 interface clock source */
+ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+ }
+
+ /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
+ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+ /* Configure the DFSDM interface clock source */
+ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+ }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
@@ -512,7 +552,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
- assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
@@ -564,7 +603,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
- if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
{
/* check for PLLSAIQ Parameter */
@@ -600,7 +639,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
}
-#if defined(STM32F756xx) || defined(STM32F746xx)
+#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{
@@ -619,7 +658,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
}
-#endif /* STM32F756xx || STM32F746xx */
+#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
@@ -651,7 +690,8 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t tempreg = 0;
/* Set all possible values for the extended clock type parameter------------*/
- PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
@@ -660,8 +700,22 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
- RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
+ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\
+ RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO;
+#else
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
+ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
+ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
+ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
+ RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
+ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
+ RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
RCC_PERIPHCLK_CLK48;
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Get the PLLI2S Clock configuration -----------------------------------------------*/
PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
@@ -734,9 +788,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Get the CK48 clock configuration -----------------------------------------------*/
PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
- /* Get the SDMMC clock configuration -----------------------------------------------*/
+ /* Get the SDMMC1 clock configuration -----------------------------------------------*/
PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+ /* Get the SDMMC2 clock configuration -----------------------------------------------*/
+ PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
+
+ /* Get the DFSDM clock configuration -----------------------------------------------*/
+ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
+
+ /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
+ PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
/* Get the RTC Clock configuration -----------------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
@@ -751,6 +816,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
}
}
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
@@ -764,16 +830,100 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
uint32_t tmpreg = 0;
- /* This variable used to store the SAI clock frequency (value in Hz) */
+ /* This variable is used to store the SAI clock frequency (value in Hz) */
uint32_t frequency = 0;
- /* This variable used to store the VCO Input (value in Hz) */
+ /* This variable is used to store the VCO Input (value in Hz) */
uint32_t vcoinput = 0;
- /* This variable used to store the SAI clock source */
+ /* This variable is used to store the SAI clock source */
uint32_t saiclocksource = 0;
- if ((PeriphClk == RCC_PERIPHCLK_SAI1) || (PeriphClk == RCC_PERIPHCLK_SAI2))
+
+ if (PeriphClk == RCC_PERIPHCLK_SAI1)
+ {
+ saiclocksource = RCC->DCKCFGR1;
+ saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
+ switch (saiclocksource)
+ {
+ case 0: /* PLLSAI is the clock source for SAI1 */
+ {
+ /* Configure the PLLSAI division factor */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+ tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
+ frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
+ frequency = frequency/(tmpreg);
+ break;
+ }
+ case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
+ {
+ /* Configure the PLLI2S division factor */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the PLL Source is HSI (Internal Clock) */
+ vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+ }
+ else
+ {
+ /* In Case the PLL Source is HSE (External Clock) */
+ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+ }
+
+ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+ tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
+ frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
+ frequency = frequency/(tmpreg);
+ break;
+ }
+ case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
+ {
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+ }
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+ case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the main PLL Source is HSI */
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* In Case the main PLL Source is HSE */
+ frequency = HSE_VALUE;
+ }
+ break;
+ }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+ default :
+ {
+ break;
+ }
+ }
+ }
+
+ if (PeriphClk == RCC_PERIPHCLK_SAI2)
{
saiclocksource = RCC->DCKCFGR1;
- saiclocksource &= (RCC_DCKCFGR1_SAI1SEL | RCC_DCKCFGR1_SAI2SEL);
+ saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
switch (saiclocksource)
{
case 0: /* PLLSAI is the clock source for SAI*/
@@ -800,8 +950,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = frequency/(tmpreg);
break;
}
- case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI*/
- case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI*/
+ case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
@@ -826,18 +975,34 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = frequency/(tmpreg);
break;
}
- case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI*/
- case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI*/
+ case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
{
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
+#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
+ case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
+ {
+ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+ {
+ /* In Case the main PLL Source is HSI */
+ frequency = HSI_VALUE;
+ }
+ else
+ {
+ /* In Case the main PLL Source is HSE */
+ frequency = HSE_VALUE;
+ }
+ break;
+ }
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
default :
{
break;
}
}
}
+
return frequency;
}
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rng.c b/stmhal/hal/f7/src/stm32f7xx_hal_rng.c
index e4b3d2038..a9c116953 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rng.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rng.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -187,6 +187,9 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspInit must be implemented in the user file.
*/
@@ -200,6 +203,9 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspDeInit must be implemented in the user file.
*/
@@ -441,6 +447,9 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
@@ -454,6 +463,9 @@ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrng);
+
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c b/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c
index 83bfcc658..af604feb2 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -384,6 +384,9 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspInit could be implemented in the user file
*/
@@ -397,6 +400,9 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_MspDeInit could be implemented in the user file
*/
@@ -509,7 +515,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
/* Configure the RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
@@ -576,6 +582,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/* Get subseconds values from the correspondent registers*/
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
+ /* Get SecondFraction structure field from the corresponding register field*/
+ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
+
/* Get the TR register */
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
@@ -620,9 +629,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
hrtc->State = HAL_RTC_STATE_BUSY;
- if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
{
- sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
@@ -1345,6 +1354,9 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c
index c541b7b29..3289c2430 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -243,6 +243,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
/* Enable IT timestamp */
@@ -590,6 +593,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
hrtc->Instance->TAMPCR |= tmpreg;
+ if(sTamper->Tamper == RTC_TAMPER_1)
+ {
+ /* Clear RTC Tamper 1 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+ }
+ else if(sTamper->Tamper == RTC_TAMPER_2)
+ {
+ /* Clear RTC Tamper 2 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+ else
+ {
+ /* Clear RTC Tamper 3 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+ }
+
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
@@ -728,6 +747,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_TimeStampEventCallback could be implemented in the user file
*/
@@ -741,6 +763,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_Tamper1EventCallback could be implemented in the user file
*/
@@ -754,6 +779,9 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_Tamper2EventCallback could be implemented in the user file
*/
@@ -766,6 +794,9 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
*/
@@ -1073,6 +1104,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
+ /* Clear RTC Wake Up timer Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
@@ -1193,6 +1227,9 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
*/
@@ -1753,6 +1790,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
*/
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RTC_AlarmBEventCallback could be implemented in the user file
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_sd.c b/stmhal/hal/f7/src/stm32f7xx_hal_sd.c
index 6157b029e..8a0bffbe1 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_sd.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_sd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_sd.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@@ -149,7 +149,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -206,67 +206,67 @@
SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
SDMMC_FLAG_DBCKEND))
-#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000)
+#define SDMMC_CMD0TIMEOUT ((uint32_t)0x00010000U)
/**
* @brief Mask for errors Card Status R1 (OCR Register)
*/
-#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
-#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
-#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
-#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
-#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
-#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
+#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
+#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
+#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
+#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
+#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
+#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
+#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
+#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
+#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
+#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
+#define SD_OCR_CC_ERROR ((uint32_t)0x00100000U)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
+#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
+#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
+#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
+#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
+#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
+#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000U)
+#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
+#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
/**
* @brief Masks for R6 Response
*/
-#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
-#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
-#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
+#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
+#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
+#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
-#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
-#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)
-#define SD_STD_CAPACITY ((uint32_t)0x00000000)
-#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)
+#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
+#define SD_HIGH_CAPACITY ((uint32_t)0x40000000U)
+#define SD_STD_CAPACITY ((uint32_t)0x00000000U)
+#define SD_CHECK_PATTERN ((uint32_t)0x000001AAU)
-#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
-#define SD_ALLZERO ((uint32_t)0x00000000)
+#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
+#define SD_ALLZERO ((uint32_t)0x00000000U)
-#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
-#define SD_CARD_LOCKED ((uint32_t)0x02000000)
+#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
+#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
+#define SD_CARD_LOCKED ((uint32_t)0x02000000U)
-#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
-#define SD_0TO7BITS ((uint32_t)0x000000FF)
-#define SD_8TO15BITS ((uint32_t)0x0000FF00)
-#define SD_16TO23BITS ((uint32_t)0x00FF0000)
-#define SD_24TO31BITS ((uint32_t)0xFF000000)
-#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
+#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
+#define SD_0TO7BITS ((uint32_t)0x000000FFU)
+#define SD_8TO15BITS ((uint32_t)0x0000FF00U)
+#define SD_16TO23BITS ((uint32_t)0x00FF0000U)
+#define SD_24TO31BITS ((uint32_t)0xFF000000U)
+#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
-#define SD_HALFFIFO ((uint32_t)0x00000008)
-#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)
+#define SD_HALFFIFO ((uint32_t)0x00000008U)
+#define SD_HALFFIFOBYTES ((uint32_t)0x00000020U)
/**
* @brief Command Class Supported
*/
-#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
-#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
-#define SD_CCCC_ERASE ((uint32_t)0x00000020)
+#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080U)
+#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040U)
+#define SD_CCCC_ERASE ((uint32_t)0x00000020U)
/**
* @brief Following commands are SD Card Specific commands.
@@ -413,6 +413,9 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_MspInit could be implemented in the user file
*/
@@ -425,6 +428,9 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_MspDeInit could be implemented in the user file
*/
@@ -453,14 +459,14 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @param hsd: SD handle
- * @param pReadBuffer: pointer to the buffer that will contain the received data
- * @param BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
+ * @param pReadBuffer: pointer to the buffer that will contain the received data
+ * @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to read
* @retval SD Card error state
*/
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -470,16 +476,10 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
- uint32_t ReadAddr;
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
BlockSize = 512;
- ReadAddr = BlockNumber;
- }
- else
- {
- // should not overflow for standard-capacity cards
- ReadAddr = BlockNumber * BlockSize;
+ ReadAddr /= 512;
}
/* Set Block Size for Card */
@@ -518,7 +518,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_
sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
}
- sdmmc_cmdinitstructure.Argument = ReadAddr;
+ sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr;
SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
/* Read block(s) in polling mode */
@@ -636,13 +636,13 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_
* transfer is managed by polling mode.
* @param hsd: SD handle
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
- * @param BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
+ * @param WriteAddr: Address from where data is to be written
* @param BlockSize: SD card Data block size
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of SD blocks to write
* @retval SD Card error state
*/
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -654,16 +654,10 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32
/* Initialize data control register */
hsd->Instance->DCTRL = 0;
- uint32_t WriteAddr;
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
BlockSize = 512;
- WriteAddr = BlockNumber;
- }
- else
- {
- // should not overflow for standard-capacity cards
- WriteAddr = BlockNumber * BlockSize;
+ WriteAddr /= 512;
}
/* Set Block Size for Card */
@@ -693,7 +687,7 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32
sdmmc_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
}
- sdmmc_cmdinitstructure.Argument = WriteAddr;
+ sdmmc_cmdinitstructure.Argument = (uint32_t)WriteAddr;
SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
/* Check for error conditions */
@@ -852,13 +846,13 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber(SD_HandleTypeDef *hsd, uint32
* to check the completion of the read process
* @param hsd: SD handle
* @param pReadBuffer: Pointer to the buffer that will contain the received data
- * @param BlockNumber: Block number from where data is to be read (byte address = BlockNumber * BlockSize)
+ * @param ReadAddr: Address from where data is to be read
* @param BlockSize: SD card Data block size
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to read.
* @retval SD Card error state
*/
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -898,16 +892,10 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uin
/* Enable the DMA Channel */
HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
- uint32_t ReadAddr;
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
BlockSize = 512;
- ReadAddr = BlockNumber;
- }
- else
- {
- // should not overflow for standard-capacity cards
- ReadAddr = BlockNumber * BlockSize;
+ ReadAddr /= 512;
}
/* Set Block Size for Card */
@@ -947,7 +935,7 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uin
sdmmc_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
}
- sdmmc_cmdinitstructure.Argument = ReadAddr;
+ sdmmc_cmdinitstructure.Argument = (uint32_t)ReadAddr;
SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
/* Check for error conditions */
@@ -974,13 +962,13 @@ HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uin
* to check the completion of the write process (by SD current status polling).
* @param hsd: SD handle
* @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
- * @param BlockNumber: Block number to where data is to be written (byte address = BlockNumber * BlockSize)
+ * @param WriteAddr: Address from where data is to be read
* @param BlockSize: the SD card Data block size
* @note BlockSize must be 512 bytes.
* @param NumberOfBlocks: Number of blocks to write
* @retval SD Card error state
*/
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint32_t BlockNumber, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
{
SDMMC_CmdInitTypeDef sdmmc_cmdinitstructure;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -1020,16 +1008,10 @@ HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_BlockNumber_DMA(SD_HandleTypeDef *hsd, ui
/* Enable SDMMC DMA transfer */
__HAL_SD_SDMMC_DMA_ENABLE(hsd);
- uint32_t WriteAddr;
if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
BlockSize = 512;
- WriteAddr = BlockNumber;
- }
- else
- {
- // should not overflow for standard-capacity cards
- WriteAddr = BlockNumber * BlockSize;
+ WriteAddr /= 512;
}
/* Set Block Size for Card */
@@ -1395,6 +1377,9 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
*/
__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_XferCpltCallback could be implemented in the user file
*/
@@ -1407,6 +1392,9 @@ __weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
*/
__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_XferErrorCallback could be implemented in the user file
*/
@@ -1420,6 +1408,9 @@ __weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
*/
__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
*/
@@ -1433,6 +1424,9 @@ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
*/
__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
*/
@@ -1446,6 +1440,9 @@ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
*/
__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
*/
@@ -1459,6 +1456,9 @@ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
*/
__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
*/
@@ -1499,7 +1499,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->RCA = (uint16_t)(hsd->RCA);
/* Byte 0 */
- tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
+ tmp = (hsd->CSD[0] & 0xFF000000U) >> 24;
pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);
pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
pCardInfo->SD_csd.Reserved1 = tmp & 0x03;
@@ -1517,16 +1517,16 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
/* Byte 4 */
- tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
+ tmp = (hsd->CSD[1] & 0xFF000000U) >> 24;
pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
/* Byte 5 */
- tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
+ tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16;
pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F);
/* Byte 6 */
- tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
+ tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8;
pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);
pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
@@ -1538,23 +1538,23 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
/* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
/* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
/* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
/* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ;
@@ -1565,23 +1565,23 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
{
/* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
+ tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU);
pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
/* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24);
pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
/* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+ tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16);
pCardInfo->SD_csd.DeviceSize |= (tmp);
/* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+ tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8);
- pCardInfo->CardCapacity = ((pCardInfo->SD_csd.DeviceSize + 1ULL)) * 512 * 1024;
+ pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);
pCardInfo->CardBlockSize = 512;
}
else
@@ -1599,7 +1599,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
/* Byte 12 */
- tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24);
pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
@@ -1627,7 +1627,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_csd.Reserved4 = 1;
/* Byte 0 */
- tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ManufacturerID = tmp;
/* Byte 1 */
@@ -1643,7 +1643,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_cid.ProdName1 = tmp << 24;
/* Byte 4 */
- tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ProdName1 |= tmp << 16;
/* Byte 5 */
@@ -1659,7 +1659,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_cid.ProdName2 = tmp;
/* Byte 8 */
- tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ProdRev = tmp;
/* Byte 9 */
@@ -1675,7 +1675,7 @@ HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTy
pCardInfo->SD_cid.ProdSN |= tmp << 8;
/* Byte 12 */
- tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24);
pCardInfo->SD_cid.ProdSN |= tmp;
/* Byte 13 */
@@ -1840,7 +1840,7 @@ HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
SDMMC_DataConfig(hsd->Instance, &sdmmc_datainitstructure);
/* Send CMD6 switch mode */
- sdmmc_cmdinitstructure.Argument = 0x80FFFF01;
+ sdmmc_cmdinitstructure.Argument = 0x80FFFF01U;
sdmmc_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;
SDMMC_SendCommand(hsd->Instance, &sdmmc_cmdinitstructure);
@@ -2121,55 +2121,55 @@ HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatu
pCardStatus->SECURED_MODE = (uint8_t)tmp;
/* Byte 2 */
- tmp = (sd_status[2] & 0xFF);
- pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
+ tmp = (sd_status[0] & 0x00FF0000) >> 16;
+ pCardStatus->SD_CARD_TYPE = (uint16_t)(tmp << 8);
/* Byte 3 */
- tmp = (sd_status[3] & 0xFF);
- pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
+ tmp = (sd_status[0] & 0xFF000000) >> 24;
+ pCardStatus->SD_CARD_TYPE |= (uint16_t)tmp;
/* Byte 4 */
- tmp = (sd_status[4] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
+ tmp = (sd_status[1] & 0xFF);
+ pCardStatus->SIZE_OF_PROTECTED_AREA = (uint32_t)(tmp << 24);
/* Byte 5 */
- tmp = (sd_status[5] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
+ tmp = (sd_status[1] & 0xFF00) >> 8;
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 16);
/* Byte 6 */
- tmp = (sd_status[6] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
+ tmp = (sd_status[1] & 0xFF0000) >> 16;
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)(tmp << 8);
/* Byte 7 */
- tmp = (sd_status[7] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
+ tmp = (sd_status[1] & 0xFF000000) >> 24;
+ pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint32_t)tmp;
/* Byte 8 */
- tmp = (sd_status[8] & 0xFF);
+ tmp = (sd_status[2] & 0xFF);
pCardStatus->SPEED_CLASS = (uint8_t)tmp;
/* Byte 9 */
- tmp = (sd_status[9] & 0xFF);
+ tmp = (sd_status[2] & 0xFF00) >> 8;
pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
/* Byte 10 */
- tmp = (sd_status[10] & 0xF0) >> 4;
+ tmp = (sd_status[2] & 0xF00000) >> 20;
pCardStatus->AU_SIZE = (uint8_t)tmp;
/* Byte 11 */
- tmp = (sd_status[11] & 0xFF);
- pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
+ tmp = (sd_status[2] & 0xFF000000) >> 24;
+ pCardStatus->ERASE_SIZE = (uint16_t)(tmp << 8);
/* Byte 12 */
- tmp = (sd_status[12] & 0xFF);
- pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
+ tmp = (sd_status[3] & 0xFF);
+ pCardStatus->ERASE_SIZE |= (uint16_t)tmp;
/* Byte 13 */
- tmp = (sd_status[13] & 0xFC) >> 2;
+ tmp = (sd_status[3] & 0xFC00) >> 10;
pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
/* Byte 13 */
- tmp = (sd_status[13] & 0x3);
+ tmp = (sd_status[3] & 0x0300) >> 8;
pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
return errorstate;
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_spi.c b/stmhal/hal/f7/src/stm32f7xx_hal_spi.c
index 999877937..4bb5a4847 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_spi.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_spi.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -11,6 +11,7 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -21,7 +22,7 @@
(#) Declare a SPI_HandleTypeDef handle structure, for example:
SPI_HandleTypeDef hspi;
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
(##) Enable the SPIx interface clock
(##) SPI pins configuration
(+++) Enable the clock for the SPI GPIOs
@@ -30,19 +31,19 @@
(+++) Configure the SPIx interrupt priority
(+++) Enable the NVIC SPI IRQ handle
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
+ (+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customised HAL_SPI_MspInit() API.
+ by calling the customized HAL_SPI_MspInit() API.
[..]
Circular mode restriction:
(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
@@ -51,12 +52,72 @@
(#) The CRC feature is not managed when the DMA circular mode is enabled
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -101,15 +162,15 @@
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
-#define SPI_DEFAULT_TIMEOUT 50
+#define SPI_DEFAULT_TIMEOUT 100U
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
+/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -119,31 +180,39 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
@@ -184,8 +253,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
*/
/**
- * @brief Initializes the SPI according to the specified parameters
- * in the SPI_InitTypeDef and create the associated handle.
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
@@ -195,7 +264,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
uint32_t frxth;
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
@@ -205,18 +274,28 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
assert_param(IS_SPI_MODE(hspi->Init.Mode));
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
+#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
- if(hspi->State == HAL_SPI_STATE_RESET)
+ if (hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
@@ -231,7 +310,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE(hspi);
/* Align by default the rs fifo threshold on the data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
}
@@ -241,17 +320,17 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
- if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
+ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
}
/* Align the CRC Length on the data size */
- if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
{
/* CRC Length aligned on the data size : value set by default */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
}
@@ -261,35 +340,46 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
}
}
- /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
- Communication speed, First bit, CRC calculation state, CRC Length */
- hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
-
- if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ Communication speed, First bit, CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
+#if (USE_SPI_CRC != 0U)
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- hspi->Instance->CR1|= SPI_CR1_CRCL;
+ hspi->Instance->CR1 |= SPI_CR1_CRCL;
}
+#endif /* USE_SPI_CRC */
- /* Configure : NSS management */
- /* Configure : Rx Fifo Threshold */
- hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
- hspi->Init.DataSize ) | frxth;
+ /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode |
+ hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
- /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
- hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State= HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the SPI peripheral
+ * @brief De-Initialize the SPI peripheral.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
@@ -297,21 +387,16 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check SPI Instance parameter */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
hspi->State = HAL_SPI_STATE_BUSY;
- /* check flag before the SPI disable */
- SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
- SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
- SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
-
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
@@ -321,32 +406,39 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
+ /* Release Lock */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
/**
- * @brief SPI MSP Init
+ * @brief Initialize the SPI MSP.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
- __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
- {
- /* NOTE : This function should not be modified, when the callback is needed,
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspInit should be implemented in the user file
*/
}
/**
- * @brief SPI MSP DeInit
+ * @brief De-Initialize the SPI MSP.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
- __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspDeInit should be implemented in the user file
*/
@@ -363,6 +455,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
==============================================================================
##### IO operation functions #####
===============================================================================
+ [..]
This subsection provides a set of functions allowing to manage the SPI
data transfers.
@@ -373,13 +466,13 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
exist for 1Line (simplex) and 2Lines (full duplex) modes.
@@ -389,7 +482,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
*/
/**
- * @brief Transmit an amount of data in blocking mode
+ * @brief Transmit an amount of data in blocking mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
@@ -399,142 +492,155 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return HAL_BUSY;
+ errorcode = HAL_BUSY;
+ goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ goto error;
}
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0)
+ while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return HAL_TIMEOUT;
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
}
}
/* Transmit data in 8 Bit mode */
else
{
- while (hspi->TxXferCount > 0)
+ while (hspi->TxXferCount > 0U)
{
- if(hspi->TxXferCount != 0x1)
+ /* Wait until TXE flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
{
- hspi->State = HAL_SPI_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return HAL_TIMEOUT;
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ hspi->TxXferCount--;
}
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
}
else
{
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
- return HAL_TIMEOUT;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
- *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
}
}
}
-
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+error:
+ hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_OK;
- }
+ return errorcode;
}
/**
- * @brief Receive an amount of data in blocking mode
+ * @brief Receive an amount of data in blocking mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
@@ -544,47 +650,63 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- __IO uint16_t tmpreg;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if(hspi->State != HAL_SPI_STATE_READY)
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
- return HAL_BUSY;
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
- if((pData == NULL ) || (Size == 0))
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
- return HAL_ERROR;
+ errorcode = HAL_BUSY;
+ goto error;
}
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ if ((pData == NULL) || (Size == 0U))
{
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the transmitReceive process */
- return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ errorcode = HAL_ERROR;
+ goto error;
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
/* this is done to handle the CRCNEXT before the latest data */
hspi->RxXferCount--;
}
+#endif /* USE_SPI_CRC */
- /* Set the Rx Fido threshold */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ /* Set the Rx Fifo threshold */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -595,139 +717,160 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
- /* Configure communication direction 1Line and enabled SPI if needed */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
{
- while(hspi->RxXferCount > 1)
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U)
{
- /* Wait until the RXNE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- return HAL_TIMEOUT;
+ /* read the received data */
+ (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ pData += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
- (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
- hspi->RxXferCount--;
}
}
- else /* Receive data in 16 Bit mode */
+ else
{
- while(hspi->RxXferCount > 1 )
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0U)
{
- /* Wait until RXNE flag is reset to read data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Check the RXNE flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- return HAL_TIMEOUT;
+ *((uint16_t *)pData) = hspi->Instance->DR;
+ pData += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
}
}
- /* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ /* Handle the CRC Transmission */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
- }
+ /* freeze the CRC before the latest data */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Wait until RXNE flag is set */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Read the latest data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ /* the latest data has not been received */
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
- /* Receive last data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- }
- /* Receive last data in 8 Bit mode */
- else
- {
- (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
- }
- hspi->RxXferCount--;
+ /* Receive last data in 16 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ *((uint16_t *)pData) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
+ else
+ {
+ (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ }
- /* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Wait the CRC data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
- /* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+
+ /* Read CRC to Flush DR and RXNE flag */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- hspi->State = HAL_SPI_STATE_READY;
-
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- return HAL_ERROR;
}
+#endif /* USE_SPI_CRC */
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- return HAL_ERROR;
- }
- else
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- return HAL_OK;
+ errorcode = HAL_ERROR;
}
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in blocking mode
+ * @brief Transmit and Receive an amount of data in blocking mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
@@ -736,44 +879,72 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
{
- __IO uint16_t tmpreg = 0;
- uint32_t tickstart = HAL_GetTick();
-
+ uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
- return HAL_BUSY;
+ errorcode = HAL_BUSY;
+ goto error;
}
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ goto error;
}
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pRxData;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = pTxData;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
- /* Set the Rx Fido threshold */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+ /* Set the Rx Fifo threshold */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -785,85 +956,113 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit and Receive data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
- if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
hspi->TxXferCount--;
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
- if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
}
- if(Timeout != HAL_MAX_DELAY)
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return HAL_TIMEOUT;
- }
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
}
}
/* Transmit and Receive data in 8 Bit mode */
else
{
- while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData);
+ pTxData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* check TXE flag */
- if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- if(hspi->TxXferCount > 1)
+ if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
hspi->TxXferCount--;
}
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
+ /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ }
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
- if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- if(hspi->RxXferCount > 1)
+ if (hspi->RxXferCount > 1U)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2;
- if(hspi->RxXferCount <= 1)
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount <= 1U)
{
/* set fiforxthreshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -871,91 +1070,91 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
else
{
- (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
hspi->RxXferCount--;
}
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
}
- if(Timeout != HAL_MAX_DELAY)
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hspi->State = HAL_SPI_STATE_READY;
- __HAL_UNLOCK(hspi);
- return HAL_TIMEOUT;
- }
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
}
}
+#if (USE_SPI_CRC != 0U)
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
-
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ /* Read CRC */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
- /* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
}
+#endif /* USE_SPI_CRC */
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- return HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- else
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- return HAL_OK;
+ errorcode = HAL_ERROR;
}
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
@@ -964,78 +1163,81 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- if(hspi->State == HAL_SPI_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ /* Process Locked */
+ __HAL_LOCK(hspi);
- /* Process Locked */
- __HAL_LOCK(hspi);
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /* Set the function for IT treatement */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->RxISR = NULL;
- hspi->TxISR = SPI_TxISR_16BIT;
- }
- else
- {
- hspi->RxISR = NULL;
- hspi->TxISR = SPI_TxISR_8BIT;
- }
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
- return HAL_OK;
- }
- else
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
- return HAL_BUSY;
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
}
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
@@ -1044,103 +1246,102 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State == HAL_SPI_STATE_READY)
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ HAL_StatusTypeDef errorcode = HAL_OK;
- /* Process Locked */
- __HAL_LOCK(hspi);
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
+ /* Process Locked */
+ __HAL_LOCK(hspi);
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this we call the transmitReceive process */
- return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
- }
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
- else
- {
- hspi->CRCSize = 0;
- }
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* check the data size to adapt Rx threshold and the set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- /* set fiforxthreshold according the reception data length: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_16BIT;
- hspi->TxISR = NULL;
- }
- else
- {
- /* set fiforxthreshold according the reception data length: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- hspi->RxISR = SPI_RxISR_8BIT;
- hspi->TxISR = NULL;
- }
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ /* check the data size to adapt Rx threshold and the set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthreshold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ /* set fiforxthreshold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
+ hspi->CRCSize = 2U;
}
-
- return HAL_OK;
+ SPI_RESET_CRC(hspi);
}
else
{
- return HAL_BUSY;
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
}
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
@@ -1150,95 +1351,105 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- if((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
- {
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hspi);
-
- hspi->CRCSize = 0;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
+ /* Process locked */
+ __HAL_LOCK(hspi);
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
- /* Set the function for IT treatement */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
- }
- else
- {
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
- }
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* check if packing mode is enabled and if there is more than 2 data to receive */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
- {
- /* set fiforxthreshold according the reception data length: 16 bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
- else
- {
- /* set fiforxthreshold according the reception data length: 8 bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
+ }
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
+ hspi->CRCSize = 2U;
}
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
- return HAL_OK;
+ /* check if packing mode is enabled and if there is more than 2 data to receive */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
+ {
+ /* set fiforxthreshold according the reception data length: 16 bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- return HAL_BUSY;
+ /* set fiforxthreshold according the reception data length: 8 bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit an amount of data in no-blocking mode with DMA
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
@@ -1247,41 +1458,53 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
- return HAL_BUSY;
+ errorcode = HAL_BUSY;
+ goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ goto error;
}
- /* Process Locked */
- __HAL_LOCK(hspi);
-
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* Set the SPI TxDMA Half transfer complete callback */
hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
@@ -1292,105 +1515,120 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
/* packing mode is enabled only if the DMA setting is HALWORD */
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Check the even/odd of the data size + crc if enabled */
- if((hspi->TxXferCount & 0x1) == 0)
+ if ((hspi->TxXferCount & 0x1U) == 0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U);
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
}
}
- /* Enable the Tx DMA channel */
+ /* Enable the Tx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
/* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
- return HAL_OK;
+ return errorcode;
}
/**
-* @brief Receive an amount of data in no-blocking mode with DMA
-* @param hspi: SPI handle
-* @param pData: pointer to data buffer
-* @param Size: amount of data to be sent
-* @retval HAL status
-*/
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State != HAL_SPI_STATE_READY)
- {
- return HAL_BUSY;
- }
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if((pData == NULL) || (Size == 0))
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
- return HAL_ERROR;
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
/* Process Locked */
__HAL_LOCK(hspi);
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the transmitReceive process */
- return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
- }
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* packing mode management is enabled by the DMA settings */
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
- /* Process Locked */
- __HAL_UNLOCK(hspi);
/* Restriction the DMA data received is not allowed in this mode */
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
+ goto error;
}
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -1410,180 +1648,498 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
- /* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
- /* Enable the Rx DMA channel */
+ /* Enable the Rx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
- return HAL_OK;
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
* @param Size: amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- if((hspi->State == HAL_SPI_STATE_READY) ||
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+ if (!((tmp == HAL_SPI_STATE_READY) ||
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /* Process locked */
- __HAL_LOCK(hspi);
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* check if the transmit Receive function is not called by a receive master */
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = (uint8_t *)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t *)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
+ /* Reset the threshold bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
- /* Reset CRC Calculation + increase the rxsize */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* the packing mode management is enabled by the DMA settings according the spi data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* set fiforxthreshold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
+ else
+ {
+ /* set fiforxthreshold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- SPI_RESET_CRC(hspi);
+ if ((hspi->TxXferSize & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = hspi->TxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
+ }
}
- /* Reset the threshold bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
-
- /* the packing mode management is enabled by the DMA settings according the spi data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
}
- else
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmatx != NULL)
{
- /* set fiforxthreshold according the reception data length: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
- if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
{
- if((hspi->TxXferSize & 0x1) == 0x0 )
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = hspi->TxXferCount >> 1;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
- }
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
- if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
- {
- /* set fiforxthreshold according the reception data length: 16bit */
- CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
- /* Size must include the CRC length */
- if((hspi->RxXferCount & 0x1) == 0x0 )
- {
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1;
- }
- else
- {
- SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
- }
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
- }
- /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
- the reception request (RXNE) */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
}
- else
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmarx != NULL)
{
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
}
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
- /* Enable Rx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
- /* Enable the Rx DMA channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt ;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
- if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
}
else
{
- hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmarx->XferAbortCallback = NULL;
}
+ }
- /* Enable the Tx DMA channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
{
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
- /* Enable Tx DMA Request */
- hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
}
+
+ return errorcode;
}
/**
- * @brief Pauses the DMA Transfer.
+ * @brief Pause the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
@@ -1603,7 +2159,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Resumes the DMA Transfer.
+ * @brief Resume the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
@@ -1623,7 +2179,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
}
/**
- * @brief Stops the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
@@ -1636,13 +2192,13 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
*/
- /* Abort the SPI DMA tx Stream */
- if(hspi->hdmatx != NULL)
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
{
HAL_DMA_Abort(hspi->hdmatx);
}
- /* Abort the SPI DMA rx Stream */
- if(hspi->hdmarx != NULL)
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
{
HAL_DMA_Abort(hspi->hdmarx);
}
@@ -1654,153 +2210,208 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
}
/**
- * @brief This function handles SPI interrupt request.
+ * @brief Handle SPI interrupt request.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
/* SPI in mode Receiver ----------------------------------------------------*/
- if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
- (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
+ if (((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
- /* SPI in mode Transmitter ---------------------------------------------------*/
- if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
- /* SPI in ERROR Treatment ---------------------------------------------------*/
- if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
{
- /* SPI Overrun error interrupt occurred -------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if ((itflag & SPI_FLAG_OVR) != RESET)
{
- if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
else
{
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
return;
}
}
- /* SPI Mode Fault error interrupt occurred -------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((itflag & SPI_FLAG_MODF) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
- /* SPI Frame error interrupt occurred ----------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((itflag & SPI_FLAG_FRE) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
__HAL_SPI_CLEAR_FREFLAG(hspi);
}
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmarx);
+ }
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
return;
}
}
/**
- * @brief Tx Transfer completed callback
+ * @brief Tx Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxCpltCallback should be implemented in the user file
*/
}
/**
- * @brief Rx Transfer completed callbacks
+ * @brief Rx Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxCpltCallback should be implemented in the user file
*/
}
/**
- * @brief Tx and Rx Transfer completed callback
+ * @brief Tx and Rx Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxCpltCallback should be implemented in the user file
*/
}
/**
- * @brief Tx Half Transfer completed callback
+ * @brief Tx Half Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
*/
}
/**
- * @brief Rx Half Transfer completed callback
+ * @brief Rx Half Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
*/
}
/**
- * @brief Tx and Rx Half Transfer callback
+ * @brief Tx and Rx Half Transfer callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
*/
}
/**
- * @brief SPI error callback
+ * @brief SPI error callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_ErrorCallback should be implemented in the user file
*/
@@ -1810,15 +2421,26 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
}
/**
- * @}
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
*/
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
/**
* @}
*/
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
+ * @brief SPI control functions
*
@verbatim
===============================================================================
@@ -1833,24 +2455,26 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
*/
/**
- * @brief Return the SPI state
+ * @brief Return the SPI handle state.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI handle state */
return hspi->State;
}
/**
- * @brief Return the SPI error code
+ * @brief Return the SPI error code.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI ErrorCode */
return hspi->ErrorCode;
}
@@ -1862,36 +2486,50 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
* @}
*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
* @{
*/
/**
- * @brief DMA SPI transmit process complete callback
+ * @brief DMA SPI transmit process complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
/* DMA Normal Mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
- /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- hspi->TxXferCount = 0;
+ hspi->TxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
return;
@@ -1901,215 +2539,380 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
}
/**
- * @brief DMA SPI receive process complete callback
+ * @brief DMA SPI receive process complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- __IO uint16_t tmpreg;
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- /* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ /* Wait until RXNE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ /* Read CRC */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
+#endif /* USE_SPI_CRC */
- /* Disable Rx DMA Request */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
- hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Check the end of the transaction */
- SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
- hspi->RxXferCount = 0;
+ hspi->RxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_RxCpltCallback(hspi);
}
- else
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
+ HAL_SPI_ErrorCallback(hspi);
+ return;
}
}
- else
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
+ HAL_SPI_RxCpltCallback(hspi);
}
/**
- * @brief DMA SPI transmit receive process complete callback
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- __IO int16_t tmpreg;
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- /* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
{
- /* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
- }
- else
- {
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ else
{
- /* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
}
- }
-
- /* Check the end of the transaction */
- SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
+#endif /* USE_SPI_CRC */
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- HAL_SPI_TxRxCpltCallback(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
- else
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
+ return;
}
}
+ HAL_SPI_TxRxCpltCallback(hspi);
}
/**
- * @brief DMA SPI half transmit process complete callback
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_SPI_TxHalfCpltCallback(hspi);
}
/**
- * @brief DMA SPI half receive process complete callback
+ * @brief DMA SPI half receive process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_SPI_RxHalfCpltCallback(hspi);
}
/**
- * @brief DMA SPI Half transmit receive process complete callback
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_SPI_TxRxHalfCpltCallback(hspi);
}
/**
- * @brief DMA SPI communication error callback
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI communication error callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
}
/**
- * @brief Rx Handler for Transmit and Receive in Interrupt mode
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2117,12 +2920,12 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma)
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in packing mode */
- if(hspi->RxXferCount > 1)
+ if (hspi->RxXferCount > 1U)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2;
- if(hspi->RxXferCount == 1)
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount == 1U)
{
/* set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -2136,55 +2939,62 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
}
/* check end of the reception */
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#if (USE_SPI_CRC != 0U)
/**
- * @brief Rx Handler for Transmit and Receive in Interrupt mode
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg;
+ __IO uint8_t tmpreg = 0U;
+ /* Read data register to flush CRC */
tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
- UNUSED(tmpreg); /* To avoid GCC warning */
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
/* check end of the reception */
- if(hspi->CRCSize == 0)
+ if (hspi->CRCSize == 0U)
{
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#endif /* USE_SPI_CRC */
/**
- * @brief Tx Handler for Transmit and Receive in Interrupt mode
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2192,11 +3002,11 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in packing Bit mode */
- if(hspi->TxXferCount >= 2)
+ if (hspi->TxXferCount >= 2U)
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->TxXferCount -= 2U;
}
/* Transmit data in 8 Bit mode */
else
@@ -2206,16 +3016,23 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
}
/* check the end of the transmission */
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
}
+#endif /* USE_SPI_CRC */
+
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2223,7 +3040,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
}
/**
- * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2231,30 +3048,33 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_16BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#if (USE_SPI_CRC != 0U)
/**
- * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2262,17 +3082,23 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
SPI_CloseRxTx_ISR(hspi);
}
+#endif /* USE_SPI_CRC */
/**
- * @brief Tx Handler for Transmit and Receive in Interrupt mode
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2285,44 +3111,57 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
}
+#endif /* USE_SPI_CRC */
+
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#if (USE_SPI_CRC != 0U)
/**
- * @brief Manage the CRC receive in Interrupt context
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg;
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
- UNUSED(tmpreg); /* To avoid GCC warning */
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
- if(hspi->CRCSize == 0)
+ if (hspi->CRCSize == 0U)
{
SPI_CloseRx_ISR(hspi);
}
}
+#endif /* USE_SPI_CRC */
/**
- * @brief Manage the receive in Interrupt context
+ * @brief Manage the receive 8-bit in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2332,44 +3171,53 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
hspi->RxXferCount--;
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_8BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
+#if (USE_SPI_CRC != 0U)
/**
- * @brief Manage the CRC 16bit receive in Interrupt context
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg;
+ __IO uint16_t tmpreg = 0U;
+ /* Read data register to flush CRC */
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
SPI_CloseRx_ISR(hspi);
}
+#endif /* USE_SPI_CRC */
/**
- * @brief Manage the 16Bit receive in Interrupt context
+ * @brief Manage the 16-bit receive in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2380,25 +3228,29 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_16BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
/**
- * @brief Handle the data 8Bit transmit in Interrupt mode
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2408,19 +3260,21 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
/**
- * @brief Handle the data 16Bit transmit in Interrupt mode
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2432,35 +3286,37 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
/**
- * @brief This function handles SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag : SPI flag to check
- * @param State : flag state to check
- * @param Timeout : Timeout duration
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param State: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = HAL_GetTick();
-
- while((hspi->Instance->SR & Flag) != State)
+ while ((hspi->Instance->SR & Flag) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -2469,19 +3325,20 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
- hspi->State= HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -2495,46 +3352,49 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
}
/**
- * @brief This function handles SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Fifo : Fifo to check
- * @param State : Fifo state to check
- * @param Timeout : Timeout duration
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo: Fifo to check
+ * @param State: Fifo state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
{
__IO uint8_t tmpreg;
- uint32_t tickstart = HAL_GetTick();
- while((hspi->Instance->SR & Fifo) != State)
+ while ((hspi->Instance->SR & Fifo) != State)
{
- if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
- UNUSED(tmpreg); /* To avoid GCC warning */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -2553,90 +3413,115 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
}
/**
- * @brief This function handles the check of the RX transaction complete.
+ * @brief Handle the check of the RX transaction complete.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Timeout : Timeout duration
- * @retval None
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval None.
*/
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
}
-
return HAL_OK;
}
/**
- * @brief This function handles the check of the RXTX or TX transaction complete.
+ * @brief Handle the check of the RXTX or TX transaction complete.
* @param hspi: SPI handle
- * @param Timeout : Timeout duration
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
*/
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
- /* Procedure to check the transaction complete */
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
+ /* Control if the TX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ /* Control if the RX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
return HAL_OK;
}
/**
- * @brief This function handles the close of the RXTX transaction.
+ * @brief Handle the end of the RXTX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->State = HAL_SPI_STATE_READY;
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
HAL_SPI_ErrorCallback(hspi);
}
else
{
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
- hspi->State = HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_RxCpltCallback(hspi);
}
else
{
- hspi->State = HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_TxRxCpltCallback(hspi);
}
}
@@ -2645,64 +3530,83 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
}
+#if (USE_SPI_CRC != 0U)
}
+#endif /* USE_SPI_CRC */
}
/**
- * @brief This function handles the close of the RX transaction.
+ * @brief Handle the end of the RX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
- hspi->State = HAL_SPI_STATE_READY;
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
+ HAL_SPI_RxCpltCallback(hspi);
}
else
{
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
+ HAL_SPI_ErrorCallback(hspi);
}
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
}
/**
- * @brief This function handles the close of the TX transaction.
+ * @brief Handle the end of the TX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
}
@@ -2712,11 +3616,73 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
}
}
+/**
+ * @brief Handle abort a Rx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @brief Handle abort a Tx or Rx/Tx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
/**
* @}
*/
#endif /* HAL_SPI_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_tim.c b/stmhal/hal/f7/src/stm32f7xx_hal_tim.c
index 147cd670f..3a6d7a9c9 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_tim.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -58,10 +58,10 @@
(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -265,6 +265,9 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
@@ -278,6 +281,9 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Base_MspDeInit could be implemented in the user file
*/
@@ -544,6 +550,9 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
@@ -557,6 +566,9 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OC_MspDeInit could be implemented in the user file
*/
@@ -1053,6 +1065,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
@@ -1066,6 +1081,9 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspDeInit could be implemented in the user file
*/
@@ -1144,7 +1162,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
* @brief Starts the PWM signal generation in interrupt mode.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1565,6 +1583,9 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_IC_MspInit could be implemented in the user file
*/
@@ -1578,6 +1599,9 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_IC_MspDeInit could be implemented in the user file
*/
@@ -2050,6 +2074,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
@@ -2063,6 +2090,9 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
*/
@@ -2366,6 +2396,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspInit could be implemented in the user file
*/
@@ -2379,6 +2412,9 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
*/
@@ -2948,9 +2984,6 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
/* Check input state */
__HAL_LOCK(htim);
@@ -3120,9 +3153,6 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
htim->State = HAL_TIM_STATE_BUSY;
@@ -3938,9 +3968,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
- assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
- assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
- assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
@@ -3961,6 +3988,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_ETRMODE1:
{
assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
@@ -3980,6 +4010,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_ETRMODE2:
{
assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
@@ -3993,6 +4027,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_TI1:
{
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
@@ -4002,6 +4041,11 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_TI2:
{
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
TIM_TI2_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
@@ -4011,6 +4055,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_TI1ED:
{
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
@@ -4374,6 +4422,9 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
@@ -4387,6 +4438,9 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
@@ -4399,6 +4453,9 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
@@ -4412,6 +4469,9 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
@@ -4425,6 +4485,9 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
@@ -4438,6 +4501,9 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIM_ErrorCallback could be implemented in the user file
*/
@@ -4793,8 +4859,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
@@ -4861,8 +4925,6 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c b/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c
index 0252db920..131d4a6fe 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -42,10 +42,10 @@
(++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -266,6 +266,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
*/
@@ -279,6 +282,9 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
*/
@@ -1634,7 +1640,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @arg TIM_CHANNEL_ALL: all output channels supported by the timer instance selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
@@ -1643,9 +1648,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
/* Check input state */
__HAL_LOCK(htim);
@@ -1738,7 +1740,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @arg TIM_CHANNEL_ALL: all PWM channels supported by the timer instance selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
@@ -1749,10 +1750,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
- assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
/* Check input state */
__HAL_LOCK(htim);
@@ -1906,6 +1904,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
{
case TIM_CLEARINPUTSOURCE_NONE:
{
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
/* Clear the OCREF clear selection bit */
tmpsmcr &= ~TIM_SMCR_OCCS;
@@ -2162,6 +2163,92 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
return HAL_OK;
}
+#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
+/**
+ * @brief Configures the break input source.
+ * @param htim: TIM handle.
+ * @param BreakInput: Break input to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @param sBreakInputConfig: Break input source configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+ uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+ uint32_t tmporx = 0;
+ uint32_t bkin_enable_mask = 0;
+ uint32_t bkin_enable_bitpos = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ switch(sBreakInputConfig->Source)
+ {
+ case TIM_BREAKINPUTSOURCE_BKIN:
+ {
+ bkin_enable_mask = TIM1_AF1_BKINE;
+ bkin_enable_bitpos = 0;
+ }
+ break;
+
+ case TIM_BREAKINPUTSOURCE_DFSDM1:
+ {
+ bkin_enable_mask = TIM1_AF1_BKDF1BKE;
+ bkin_enable_bitpos = 8;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ switch(BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Get the TIMx_AF1 register value */
+ tmporx = htim->Instance->AF1;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set TIMx_AF1 */
+ htim->Instance->AF1 = tmporx;
+ }
+ break;
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Get the TIMx_AF2 register value */
+ tmporx = htim->Instance->AF2;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set TIMx_AF2 */
+ htim->Instance->AF2 = tmporx;
+ }
+ break;
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
@@ -2265,6 +2352,9 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRe
*/
__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_CommutationCallback could be implemented in the user file
*/
@@ -2278,6 +2368,9 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
diff --git a/stmhal/hal/f7/src/stm32f7xx_hal_uart.c b/stmhal/hal/f7/src/stm32f7xx_hal_uart.c
index 3f3b06f53..060659414 100644
--- a/stmhal/hal/f7/src/stm32f7xx_hal_uart.c
+++ b/stmhal/hal/f7/src/stm32f7xx_hal_uart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_uart.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -126,7 +126,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -164,25 +164,41 @@
* @brief HAL UART module driver
* @{
*/
+
#ifdef HAL_UART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define HAL_UART_TXDMA_TIMEOUTVALUE 22000
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
@@ -243,7 +259,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
assert_param(IS_UART_INSTANCE(huart->Instance));
}
- if(huart->State == HAL_UART_STATE_RESET)
+ if(huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
@@ -252,7 +268,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
@@ -271,13 +287,13 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- /* TEACK and/or REACK to check before moving huart->State to Ready */
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
}
@@ -295,15 +311,16 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
return HAL_ERROR;
}
- if(huart->State == HAL_UART_STATE_RESET)
+ if(huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
@@ -322,28 +339,28 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- huart->Instance->CR3 |= USART_CR3_HDSEL;
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- /* TEACK and/or REACK to check before moving huart->State to Ready */
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
}
/**
- * @brief Initializes the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart: uart handle
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart: UART handle.
* @param BreakDetectLength: specifies the LIN break detection length.
* This parameter can be one of the following values:
- * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
- * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
@@ -359,15 +376,16 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));
- if(huart->State == HAL_UART_STATE_RESET)
+ if(huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
@@ -386,33 +404,32 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/* In LIN mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- huart->Instance->CR2 |= USART_CR2_LINEN;
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
/* Set the USART LIN Break detection length. */
MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
- /* Enable the Peripheral */
+ /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- /* TEACK and/or REACK to check before moving huart->State to Ready */
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
}
-
/**
- * @brief Initializes the multiprocessor mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: UART handle
- * @param Address: UART node address (4-, 6-, 7- or 8-bit long)
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart: UART handle.
+ * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
* @param WakeUpMethod: specifies the UART wakeup method.
* This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
- * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
* @note If the user resorts to idle line detection wake up, the Address parameter
* is useless and ignored by the initialization function.
* @note If the user resorts to address mark wake up, the address length detection
@@ -431,15 +448,16 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Check the wake up method parameter */
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
- if(huart->State == HAL_UART_STATE_RESET)
+ if(huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
@@ -458,8 +476,8 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* In multiprocessor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
{
@@ -473,12 +491,93 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- /* TEACK and/or REACK to check before moving huart->State to Ready */
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
}
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: UART handle.
+ * @param Polarity: select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime: Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime: Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+{
+ uint32_t temp = 0x0;
+
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+ }
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
/**
* @brief DeInitializes the UART peripheral
@@ -496,20 +595,21 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- huart->Instance->CR1 = 0x0;
- huart->Instance->CR2 = 0x0;
- huart->Instance->CR3 = 0x0;
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->State = HAL_UART_STATE_RESET;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(huart);
@@ -522,8 +622,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
* @param huart: uart handle
* @retval None
*/
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_MspInit can be implemented in the user file
*/
@@ -534,8 +637,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
* @param huart: uart handle
* @retval None
*/
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_MspDeInit can be implemented in the user file
*/
@@ -546,7 +652,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
*/
/** @defgroup UART_Exported_Functions_Group2 IO operation functions
- * @brief UART Transmit/Receive functions
+ * @brief UART Transmit/Receive functions
*
@verbatim
===============================================================================
@@ -557,9 +663,9 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
(#) There are two mode of transfer:
(+) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (+) No-Blocking mode: The communication is performed using Interrupts
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) Non-Blocking mode: The communication is performed using Interrupts
or DMA, These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
@@ -579,14 +685,14 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
(+) UART_Transmit_IT()
(+) UART_Receive_IT()
- (#) No-Blocking mode API's with DMA are :
+ (#) Non-Blocking mode API's with DMA are :
(+) HAL_UART_Transmit_DMA()
(+) HAL_UART_Receive_DMA()
(+) HAL_UART_DMAPause()
(+) HAL_UART_DMAResume()
(+) HAL_UART_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
(+) HAL_UART_TxHalfCpltCallback()
(+) HAL_UART_TxCpltCallback()
(+) HAL_UART_RxHalfCpltCallback()
@@ -602,20 +708,22 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
*/
/**
- * @brief Send an amount of data in blocking mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Send an amount of data in blocking mode.
+ * @param huart: UART handle.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
- if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -624,49 +732,38 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a non-blocking receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
huart->TxXferSize = Size;
huart->TxXferCount = Size;
- while(huart->TxXferCount > 0)
+ while(huart->TxXferCount > 0U)
{
huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
pData += 2;
}
else
{
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
}
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- /* Check if a non-blocking receive Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -680,21 +777,23 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
}
/**
- * @brief Receive an amount of data in blocking mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout : Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
uint16_t uhMask;
+ uint32_t tickstart = 0U;
- if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -703,15 +802,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a non-blocking transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
huart->RxXferSize = Size;
huart->RxXferCount = Size;
@@ -721,18 +815,18 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
uhMask = huart->Mask;
/* as long as data have to be received */
- while(huart->RxXferCount > 0)
+ while(huart->RxXferCount > 0U)
{
huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) pData ;
*tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- pData +=2;
+ pData +=2U;
}
else
{
@@ -740,15 +834,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
}
}
- /* Check if a non-blocking transmit Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -761,17 +849,18 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in interrupt mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -784,24 +873,13 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
huart->TxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+ huart->gState = HAL_UART_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Transmit Data Register Empty Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
@@ -812,17 +890,18 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
}
/**
- * @brief Receive an amount of data in interrupt mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @brief Receive an amount of data in interrupt mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -838,27 +917,16 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
UART_MASK_COMPUTATION(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
-
- /* Enable the UART Parity Error Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(huart);
- /* Enable the UART Data Register not empty Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
return HAL_OK;
}
@@ -869,19 +937,20 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
}
/**
- * @brief Send an amount of data in DMA mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in DMA mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -894,15 +963,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
huart->TxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
+ huart->gState = HAL_UART_STATE_BUSY_TX;
/* Set the UART DMA transfer complete callback */
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
@@ -913,6 +974,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
/* Enable the UART transmit DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
@@ -920,13 +984,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
- huart->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -937,21 +1000,22 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
}
/**
- * @brief Receive an amount of data in DMA mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @brief Receive an amount of data in DMA mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
* @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
+ * the parity bit (MSB position).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -963,15 +1027,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
huart->RxXferSize = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
/* Set the UART DMA transfer complete callback */
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
@@ -982,16 +1038,25 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/* Set the DMA error callback */
huart->hdmarx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- huart->Instance->CR3 |= USART_CR3_DMAR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
@@ -1002,31 +1067,30 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
}
/**
- * @brief Pauses the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @brief Pause the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
{
/* Disable the UART DMA Tx request */
- huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
{
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
/* Disable the UART DMA Rx request */
- huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
- }
- else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- /* Disable the UART DMA Tx request */
- huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
- /* Disable the UART DMA Rx request */
- huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
@@ -1036,42 +1100,35 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
}
/**
- * @brief Resumes the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @brief Resume the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
- huart->Instance->CR3 |= USART_CR3_DMAT;
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- else if(huart->State == HAL_UART_STATE_BUSY_RX)
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resuming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
- /* Enable the UART DMA Rx request */
- huart->Instance->CR3 |= USART_CR3_DMAR;
- }
- else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
- /* Enable the UART DMA Rx request before the DMA Tx request */
- huart->Instance->CR3 |= USART_CR3_DMAR;
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART DMA Tx request */
- huart->Instance->CR3 |= USART_CR3_DMAT;
+ /* Enable the UART DMA Rx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* If the UART peripheral is still not enabled, enable it */
- if ((huart->Instance->CR1 & USART_CR1_UE) == 0)
+ if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)
{
/* Enable UART peripheral */
__HAL_UART_ENABLE(huart);
@@ -1081,9 +1138,9 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
}
/**
- * @brief Stops the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @brief Stop the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
@@ -1094,22 +1151,35 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
- /* Disable the UART Tx/Rx DMA requests */
- huart->Instance->CR3 &= ~USART_CR3_DMAT;
- huart->Instance->CR3 &= ~USART_CR3_DMAR;
-
- /* Abort the UART DMA tx channel */
- if(huart->hdmatx != NULL)
+ /* Stop UART DMA Tx request if ongoing */
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
{
- HAL_DMA_Abort(huart->hdmatx);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+
+ UART_EndTxTransfer(huart);
}
- /* Abort the UART DMA rx channel */
- if(huart->hdmarx != NULL)
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
{
- HAL_DMA_Abort(huart->hdmarx);
- }
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
- huart->State = HAL_UART_STATE_READY;
+ UART_EndRxTransfer(huart);
+ }
return HAL_OK;
}
@@ -1121,144 +1191,175 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
- /* UART parity error interrupt occurred -------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
- {
- __HAL_UART_CLEAR_PEFLAG(huart);
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+ uint32_t errorflags;
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ return;
+ }
}
- /* UART frame error interrupt occurred --------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ /* If some errors occur */
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
{
- __HAL_UART_CLEAR_FEFLAG(huart);
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
- /* UART noise error interrupt occurred --------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_NEFLAG(huart);
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_OREFLAG(huart);
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
- }
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- HAL_UART_ErrorCallback(huart);
- }
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
- /* UART in mode Receiver ---------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
- {
- UART_Receive_IT(huart);
- /* Clear RXNE interrupt flag */
- __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
- }
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_UART_ErrorCallback(huart);
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
/* UART in mode Transmitter ------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
UART_Transmit_IT(huart);
+ return;
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
UART_EndTransmit_IT(huart);
+ return;
}
}
-
/**
* @brief This function handles UART Communication Timeout.
- * @param huart: UART handle
- * @param Flag: specifies the UART flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
+ * @param huart UART handle
+ * @param Flag specifies the UART flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State= HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
+ while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
{
- while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick()-Tickstart) >= Timeout))
{
- if((Timeout == 0)||((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- huart->State= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
-
-
/**
* @brief DMA UART transmit process complete callback
* @param hdma: DMA handle
@@ -1269,16 +1370,16 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode*/
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
- huart->TxXferCount = 0;
+ huart->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
@@ -1309,23 +1410,20 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
{
- huart->RxXferCount = 0;
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Check if a transmit Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
}
HAL_UART_RxCpltCallback(huart);
}
@@ -1350,10 +1448,37 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0;
- huart->TxXferCount = 0;
- huart->State= HAL_UART_STATE_READY;
- huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+ /* Stop UART DMA Tx request if ongoing */
+ if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ UART_EndRxTransfer(huart);
+ }
+ SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief DMA UART communication abort callback, when call by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
HAL_UART_ErrorCallback(huart);
}
@@ -1364,6 +1489,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback can be implemented in the user file
*/
@@ -1376,6 +1504,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxHalfCpltCallback can be implemented in the user file
*/
@@ -1388,6 +1519,9 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_RxCpltCallback can be implemented in the user file
*/
@@ -1400,6 +1534,9 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_RxHalfCpltCallback can be implemented in the user file
*/
@@ -1412,6 +1549,9 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file
*/
@@ -1428,34 +1568,17 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
uint16_t* tmp;
- if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
- if(huart->TxXferCount == 0)
+ if(huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Data Register Empty Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
- /* Check if a receive Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
- huart->State = HAL_UART_STATE_READY;
- }
-
- /* Wait on TC flag to be able to start a second transfer */
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- HAL_UART_TxCpltCallback(huart);
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
return HAL_OK;
}
@@ -1464,12 +1587,12 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- huart->pTxBuffPtr += 2;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ huart->pTxBuffPtr += 2U;
}
else
{
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
}
huart->TxXferCount--;
@@ -1492,20 +1615,10 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State = HAL_UART_STATE_READY;
- }
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
HAL_UART_TxCpltCallback(huart);
@@ -1524,7 +1637,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
uint16_t* tmp;
uint16_t uhMask = huart->Mask;
- if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ /* Check that a Rx process is ongoing */
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
@@ -1540,23 +1654,14 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
if(--huart->RxXferCount == 0)
{
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
- /* Check if a transmit Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- huart->State = HAL_UART_STATE_READY;
- }
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
HAL_UART_RxCpltCallback(huart);
@@ -1567,10 +1672,43 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
}
else
{
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
return HAL_BUSY;
}
}
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart: UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart: UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+}
+
/**
* @}
*/
@@ -1595,6 +1733,8 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
(+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
(+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
(+) HAL_LIN_SendBreak() API transmits the break characters
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
@endverbatim
* @{
*/
@@ -1610,12 +1750,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Enable USART mute mode by setting the MME bit in the CR1 register */
- huart->Instance->CR1 |= USART_CR1_MME;
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
return (UART_CheckIdleState(huart));
}
@@ -1631,12 +1771,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable USART mute mode by clearing the MME bit in the CR1 register */
- huart->Instance->CR1 &= ~(USART_CR1_MME);
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
return (UART_CheckIdleState(huart));
}
@@ -1661,7 +1801,11 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
- return huart->State;
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
}
/**
@@ -1682,10 +1826,10 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- uint32_t tmpreg = 0x00000000;
+ uint32_t tmpreg = 0x00000000U;
UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000;
- uint16_t usartdiv = 0x0000;
+ uint16_t brrtemp = 0x0000U;
+ uint16_t usartdiv = 0x0000U;
HAL_StatusTypeDef ret = HAL_OK;
/* Check the parameters */
@@ -1751,8 +1895,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
break;
}
- brrtemp = usartdiv & 0xFFF0;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
huart->Instance->BRR = brrtemp;
}
else
@@ -1868,14 +2012,19 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
+ uint32_t tickstart = 0U;
+
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Check if the Transmitter is enabled */
if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout Occurred */
return HAL_TIMEOUT;
@@ -1885,7 +2034,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout Occurred */
return HAL_TIMEOUT;
@@ -1893,7 +2042,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
}
/* Initialize the UART State */
- huart->State= HAL_UART_STATE_READY;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1911,14 +2061,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_TE);
- huart->State= HAL_UART_STATE_READY;
+ huart->gState= HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1934,14 +2084,14 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_RE);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1962,12 +2112,12 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Send break characters */
- huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+ SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1975,6 +2125,44 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
return HAL_OK;
}
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart: UART handle.
+ * @param AddressLength: this parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if(huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
/**
* @}
diff --git a/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c b/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c
index b14445c68..2ce401379 100644
--- a/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c
+++ b/stmhal/hal/f7/src/stm32f7xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -138,7 +138,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -239,7 +239,6 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
}
-
/**
* @}
*/
@@ -485,7 +484,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM
assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
/* Set SDMMC read wait mode */
- SDMMCx->DCTRL |= SDMMC_ReadWaitMode;
+ MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
return HAL_OK;
}
diff --git a/stmhal/hal/f7/src/stm32f7xx_ll_usb.c b/stmhal/hal/f7/src/stm32f7xx_ll_usb.c
index 8266b09a7..51983557b 100644
--- a/stmhal/hal/f7/src/stm32f7xx_ll_usb.c
+++ b/stmhal/hal/f7/src/stm32f7xx_ll_usb.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_usb.c
* @author MCD Application Team
- * @version V1.0.1
- * @date 25-June-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -28,7 +28,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2015 STMicroelectronics
+ * © COPYRIGHT(c) 2016 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -72,7 +72,8 @@
/* Private functions ---------------------------------------------------------*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-/** @defgroup PCD_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
* @{
*/
@@ -117,7 +118,6 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
}
else /* FS interface (embedded Phy) */
{
-
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
@@ -166,7 +166,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
* @brief USB_SetCurrentMode : Set functional mode
* @param USBx : Selected device
* @param mode : current core mode
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
* @arg USB_OTG_DRD_MODE: Dual Role Device mode
@@ -206,7 +206,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
if (cfg.vbus_sensing_enable == 0)
{
- /*Desactivate VBUS Sensing B */
+ /* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
/* B-peripheral session valid override enable*/
@@ -243,7 +243,6 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
USB_FlushRxFifo(USBx);
-
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0;
USBx_DEVICE->DOEPMSK = 0;
@@ -378,7 +377,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
* depending the PHY type and the enumeration speed of the device.
* @param USBx : Selected device
* @param speed : device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
@@ -395,7 +394,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
* @brief USB_GetDevSpeed :Return the Dev Speed
* @param USBx : Selected device
* @retval speed : device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -512,7 +511,6 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
}
else
{
-
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
@@ -547,7 +545,7 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -669,7 +667,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -705,6 +703,9 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
}
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
if (dma == 1)
{
USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
@@ -712,14 +713,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
else
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
+ if (ep->xfer_len > 0U)
{
- USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
+ USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
}
}
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else /* OUT endpoint */
{
@@ -758,7 +756,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to write
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL status
@@ -786,7 +784,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to read
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval pointer to destination buffer
@@ -1017,7 +1015,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
* @brief Returns USB core mode
* @param USBx : Selected device
* @retval return core mode : Host or Device
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : Host
* 1 : Device
*/
@@ -1051,7 +1049,7 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
* @brief Prepare the EP0 to start the first control setup
* @param USBx : Selected device
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @param psetup : pointer to setup packet
@@ -1162,16 +1160,13 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFF;
-
if(USBx == USB_OTG_FS)
{
/* set Rx FIFO size */
USBx->GRXFSIZ = (uint32_t )0x80;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
-
}
-
else
{
/* set Rx FIFO size */
@@ -1199,7 +1194,7 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef
* HCFG register on the PHY type and set the right frame interval
* @param USBx : Selected device
* @param freq : clock frequency
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* HCFG_48_MHZ : Full Speed 48 MHz Clock
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
@@ -1232,9 +1227,10 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
__IO uint32_t hprt0;
hprt0 = USBx_HPRT0;
+ hprt0 |= USB_OTG_HPRT_PENA ;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\
+ USB_OTG_HPRT_POCCHNG );
USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
HAL_Delay (10); /* See Note #1 */
@@ -1245,7 +1241,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
/**
* @brief USB_DriveVbus : activate or de-activate vbus
* @param state : VBUS state
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : VBUS Active
* 1 : VBUS Inactive
* @retval HAL status
@@ -1255,8 +1251,10 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
__IO uint32_t hprt0;
hprt0 = USBx_HPRT0;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ hprt0 |= USB_OTG_HPRT_PENA ;
+
+ hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\
+ USB_OTG_HPRT_POCCHNG );
if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
{
@@ -1273,7 +1271,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
* @brief Return Host Core speed
* @param USBx : Selected device
* @retval speed : Host speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
@@ -1306,12 +1304,12 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
* @param dev_address : Current device address
* This parameter can be a value from 0 to 255
* @param speed : Current device speed
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
* @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
@@ -1357,6 +1355,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
}
}
break;
+
case EP_TYPE_INTR:
USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
@@ -1414,7 +1413,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
* @param USBx : Selected device
* @param hc : pointer to host channel structure
* @param dma: USB dma enabled or disabled
- * This parameter can be one of the these values:
+ * This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
* @retval HAL state
@@ -1466,8 +1465,6 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
hc->xfer_len = num_packets * hc->max_packet;
}
-
-
/* Initialize the HCTSIZn register */
USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
@@ -1659,7 +1656,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
/* Halt all channels to put them into a known state. */
for (i = 0; i <= 15; i++)
{
-
value = USBx_HC(i)->HCCHAR ;
value |= USB_OTG_HCCHAR_CHDIS;
--
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