From 328708eb2504eae2ca8132c948bc3b1fc1c95243 Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 13 Jan 2014 00:20:06 +0000 Subject: stm: Re-instate C debugging USART port (disabled by default). See pyb_usart_global_debug variable. Also did some work on USB OTG, but nothing working yet. --- stm/main.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'stm/main.c') diff --git a/stm/main.c b/stm/main.c index 44db47f13..cdc4432c0 100644 --- a/stm/main.c +++ b/stm/main.c @@ -307,7 +307,9 @@ char *strdup(const char *str) { static const char *readline_hist[READLINE_HIST_SIZE] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; void stdout_tx_str(const char *str) { - //usart_tx_str(str); // disabled because usart is a Python object and we now need specify which USART port + if (pyb_usart_global_debug != PYB_USART_NONE) { + usart_tx_str(pyb_usart_global_debug, str); + } usb_vcp_send_str(str); } @@ -322,10 +324,10 @@ int readline(vstr_t *line, const char *prompt) { if (usb_vcp_rx_any() != 0) { c = usb_vcp_rx_get(); break; - } /*else if (usart_rx_any()) { // disabled because usart is a Python object and we now need specify which USART port - c = usart_rx_char(); + } else if (pyb_usart_global_debug != PYB_USART_NONE && usart_rx_any(pyb_usart_global_debug)) { + c = usart_rx_char(pyb_usart_global_debug); break; - }*/ + } sys_tick_delay_ms(1); if (storage_needs_flush()) { storage_flush(); @@ -775,7 +777,9 @@ int main(void) { switch_init(); storage_init(); - //usart_init(); disabled while wi-fi is enabled; also disabled because now usart is a proper Python object + // uncomment these 2 lines if you want REPL on USART_6 (or another usart) as well as on USB VCP + //pyb_usart_global_debug = PYB_USART_6; + //usart_init(pyb_usart_global_debug, 115200); int first_soft_reset = true; @@ -937,6 +941,9 @@ soft_reset: // USB usb_init(); + // USB host; not working! + //pyb_usbh_init(); + // MMA if (first_soft_reset) { // init and reset address to zero -- cgit v1.2.3