From abc24c187614e358faa10ed6a3e239151f70b9f8 Mon Sep 17 00:00:00 2001
From: Damien George
Date: Tue, 21 Jul 2015 23:37:45 +0100
Subject: stmhal: Allow DAC.write_timed to take Timer object in place of freq.

This allows the DAC to use a user-specified Timer for the triggering
(instead of the default Timer(6)), while still supporting original
behaviour.

Addresses issues #1129 and #1388.
---
 docs/library/pyb.DAC.rst | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'docs')

diff --git a/docs/library/pyb.DAC.rst b/docs/library/pyb.DAC.rst
index 5d4771a17..578a4d126 100644
--- a/docs/library/pyb.DAC.rst
+++ b/docs/library/pyb.DAC.rst
@@ -64,6 +64,16 @@ Methods
    Initiates a burst of RAM to DAC using a DMA transfer.
    The input data is treated as an array of bytes (8 bit data).
    
+   ``freq`` can be an integer specifying the frequency to write the DAC
+   samples at, using Timer(6).  Or it can be an already-initialised
+   Timer object which is used to trigger the DAC sample.  Valid timers
+   are 2, 4, 5, 6, 7 and 8.
+
    ``mode`` can be ``DAC.NORMAL`` or ``DAC.CIRCULAR``.
-   
-   TIM6 is used to control the frequency of the transfer.
+
+   Example using both DACs at the same time::
+
+     dac1 = DAC(1)
+     dac2 = DAC(2)
+     dac1.write_timed(buf1, pyb.Timer(6, freq=100), mode=DAC.CIRCULAR)
+     dac2.write_timed(buf2, pyb.Timer(7, freq=200), mode=DAC.CIRCULAR)
-- 
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