From 5fd62c899226fbaac96a758e9f2b4fef5afcf19b Mon Sep 17 00:00:00 2001 From: Damien George Date: Mon, 8 Jul 2019 15:16:26 +1000 Subject: stm32: Remove SystemInit funcs, use stm32lib versions instead. stm32lib now provides system_stm32XXxx.c source files for all MCU variants, which includes SystemInit and prescaler tables. Since these are quite standard and don't need to be changed, switch to use them instead of custom variants, making the start-up code cleaner. The SystemInit code in stm32lib was checked and is equivalent to what is removed from the stm32 port in this commit. --- ports/stm32/Makefile | 14 +-- ports/stm32/main.c | 8 ++ ports/stm32/system_stm32.c | 211 ------------------------------------------- ports/stm32/system_stm32f0.c | 184 ------------------------------------- 4 files changed, 15 insertions(+), 402 deletions(-) delete mode 100644 ports/stm32/system_stm32f0.c diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index cddebbf54..84ce01e8f 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -43,6 +43,7 @@ STFLASH ?= st-flash OPENOCD ?= openocd OPENOCD_CONFIG ?= boards/openocd_stm32f4.cfg STARTUP_FILE ?= lib/stm32lib/CMSIS/STM32$(MCU_SERIES_UPPER)xx/Source/Templates/gcc/startup_$(CMSIS_MCU_LOWER).o +SYSTEM_FILE ?= lib/stm32lib/CMSIS/STM32$(MCU_SERIES_UPPER)xx/Source/Templates/system_stm32$(MCU_SERIES)xx.o # Select the cross compile prefix CROSS_COMPILE ?= arm-none-eabi- @@ -284,23 +285,22 @@ SRC_C = \ adc.c \ $(wildcard $(BOARD_DIR)/*.c) -ifeq ($(MCU_SERIES),f0) SRC_O = \ $(STARTUP_FILE) \ - system_stm32f0.o \ + $(SYSTEM_FILE) + +ifeq ($(MCU_SERIES),f0) +SRC_O += \ resethandler_m0.o \ lib/utils/gchelper_m0.o else ifeq ($(MCU_SERIES),l0) CSUPEROPT = -Os # save some code space -SRC_O = \ - $(STARTUP_FILE) \ - lib/stm32lib/CMSIS/STM32$(MCU_SERIES_UPPER)xx/Source/Templates/system_stm32$(MCU_SERIES)xx.o \ +SRC_O += \ resethandler_m0.o \ lib/utils/gchelper_m0.o else -SRC_O = \ - $(STARTUP_FILE) \ +SRC_O += \ system_stm32.o \ resethandler.o \ lib/utils/gchelper_m3.o diff --git a/ports/stm32/main.c b/ports/stm32/main.c index cd4aaa484..c05781432 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -368,6 +368,14 @@ STATIC uint update_reset_mode(uint reset_mode) { #endif void stm32_main(uint32_t reset_mode) { + #if !defined(STM32F0) && defined(MICROPY_HW_VTOR) + // Change IRQ vector table if configured differently + SCB->VTOR = MICROPY_HW_VTOR; + #endif + + // Enable 8-byte stack alignment for IRQ handlers, in accord with EABI + SCB->CCR |= SCB_CCR_STKALIGN_Msk; + // Check if bootloader should be entered instead of main application powerctrl_check_enter_bootloader(); diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index be8badea4..deb23e2f5 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -75,222 +75,11 @@ ****************************************************************************** */ -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32fxxx_system - * @{ - */ - -/** @addtogroup STM32Fxxx_System_Private_Includes - * @{ - */ - #include "py/mphal.h" #include "powerctrl.h" void __fatal_error(const char *msg); -/** - * @} - */ - -/** @addtogroup STM32Fxxx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32Fxxx_System_Private_Defines - * @{ - */ - -#if defined(STM32F4) || defined(STM32F7) - -#define CONFIG_RCC_CR_1ST (RCC_CR_HSION) -#define CONFIG_RCC_CR_2ND (MICROPY_HW_RCC_CR_HSxON | RCC_CR_CSSON | RCC_CR_PLLON) -#define CONFIG_RCC_PLLCFGR (0x24003010) - -#if defined(STM32F4) -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -#elif defined(STM32F7) -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -#endif - -#elif defined(STM32L4) - -#define CONFIG_RCC_CR_1ST (RCC_CR_MSION) -#define CONFIG_RCC_CR_2ND (RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_HSION | RCC_CR_PLLON) -#define CONFIG_RCC_PLLCFGR (0x00001000) -/* - * FIXME Do not know why I have to define these arrays here! they should be defined in the - * hal_rcc-file!! - * - */ -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \ - 4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; -#elif defined(STM32H7) - -#define CONFIG_RCC_CR_1ST (RCC_CR_HSION) -#define CONFIG_RCC_CR_2ND (~0xEAF6ED7F) -#define CONFIG_RCC_PLLCFGR (0x00000000) - -#define SRAM_BASE D1_AXISRAM_BASE -#define FLASH_BASE FLASH_BANK1_BASE -uint32_t SystemD2Clock = 64000000; -const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -#else -#error Unknown processor -#endif - -/************************* Miscellaneous Configuration ************************/ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32Fxxx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32Fxxx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 16000000; - -/** - * @} - */ - -/** @addtogroup STM32Fxxx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32Fxxx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - - /* Set configured startup clk source */ - RCC->CR |= CONFIG_RCC_CR_1ST; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSxON, CSSON and PLLON bits */ - RCC->CR &= ~ CONFIG_RCC_CR_2ND; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = CONFIG_RCC_PLLCFGR; - - #if defined(STM32H7) - /* Reset D1CFGR register */ - RCC->D1CFGR = 0x00000000; - - /* Reset D2CFGR register */ - RCC->D2CFGR = 0x00000000; - - /* Reset D3CFGR register */ - RCC->D3CFGR = 0x00000000; - - /* Reset PLLCKSELR register */ - RCC->PLLCKSELR = 0x00000000; - - /* Reset PLL1DIVR register */ - RCC->PLL1DIVR = 0x00000000; - - /* Reset PLL1FRACR register */ - RCC->PLL1FRACR = 0x00000000; - - /* Reset PLL2DIVR register */ - RCC->PLL2DIVR = 0x00000000; - - /* Reset PLL2FRACR register */ - RCC->PLL2FRACR = 0x00000000; - - /* Reset PLL3DIVR register */ - RCC->PLL3DIVR = 0x00000000; - - /* Reset PLL3FRACR register */ - RCC->PLL3FRACR = 0x00000000; - #endif - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - #if defined(STM32F4) || defined(STM32F7) - RCC->CIR = 0x00000000; - #elif defined(STM32L4) || defined(STM32H7) - RCC->CIER = 0x00000000; - #endif - - #if defined(STM32H7) - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ - *((__IO uint32_t*)0x51008108) = 0x00000001; - #endif - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef MICROPY_HW_VTOR - SCB->VTOR = MICROPY_HW_VTOR; -#else -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -#endif - - /* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */ - SCB->CCR |= SCB_CCR_STKALIGN_Msk; -} - - /** * @brief System Clock Configuration * diff --git a/ports/stm32/system_stm32f0.c b/ports/stm32/system_stm32f0.c deleted file mode 100644 index 4f561145c..000000000 --- a/ports/stm32/system_stm32f0.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * Taken from ST Cube library and modified. See below for original header. - */ - -/** - ****************************************************************************** - * @file system_stm32f0xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "py/mphal.h" - -#ifndef HSE_VALUE -#define HSE_VALUE (8000000) -#endif - -#ifndef HSI_VALUE -#define HSI_VALUE (8000000) -#endif - -#ifndef HSI48_VALUE -#define HSI48_VALUE (48000000) -#endif - -/* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock there is no need to - call the 2 first functions listed above, since SystemCoreClock variable is - updated automatically. -*/ -uint32_t SystemCoreClock = 8000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -void SystemInit(void) { - // Set HSION bit - RCC->CR |= (uint32_t)0x00000001U; - - #if defined(STM32F051x8) || defined(STM32F058x8) - // Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits - RCC->CFGR &= (uint32_t)0xF8FFB80CU; - #else - // Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits - RCC->CFGR &= (uint32_t)0x08FFB80CU; - #endif - - // Reset HSEON, CSSON and PLLON bits - RCC->CR &= (uint32_t)0xFEF6FFFFU; - - // Reset HSEBYP bit - RCC->CR &= (uint32_t)0xFFFBFFFFU; - - // Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits - RCC->CFGR &= (uint32_t)0xFFC0FFFFU; - - // Reset PREDIV[3:0] bits - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; - - #if defined(STM32F072xB) || defined(STM32F078xx) - // Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; - #elif defined(STM32F071xB) - // Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; - #elif defined(STM32F091xC) || defined(STM32F098xx) - // Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; - #elif defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F030xC) - // Reset USART1SW[1:0], I2C1SW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; - #elif defined(STM32F051x8) || defined(STM32F058xx) - // Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; - #elif defined(STM32F042x6) || defined(STM32F048xx) - // Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; - #elif defined(STM32F070x6) || defined(STM32F070xB) - // Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits - RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; - // Set default USB clock to PLLCLK, since there is no HSI48 - RCC->CFGR3 |= (uint32_t)0x00000080U; - #else - #warning "No target selected" - #endif - - // Reset HSI14 bit - RCC->CR2 &= (uint32_t)0xFFFFFFFEU; - - // Disable all interrupts - RCC->CIR = 0x00000000U; - - // dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI - SCB->CCR |= SCB_CCR_STKALIGN_Msk; -} - -void SystemCoreClockUpdate(void) { - // Get SYSCLK source - uint32_t tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) { - case RCC_CFGR_SWS_HSI: - SystemCoreClock = HSI_VALUE; - break; - case RCC_CFGR_SWS_HSE: - SystemCoreClock = HSE_VALUE; - break; - case RCC_CFGR_SWS_PLL: { - /* Get PLL clock source and multiplication factor */ - uint32_t pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - uint32_t pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = (pllmull >> 18) + 2; - uint32_t predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) { - /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ - SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; - #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) \ - || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) - } else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) { - /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ - SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; - #endif - } else { - #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ - || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ - || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ - SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; - #else - /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - #endif - } - break; - } - case RCC_CFGR_SWS_HSI48: - SystemCoreClock = HSI48_VALUE; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - // Compute HCLK clock frequency - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - SystemCoreClock >>= tmp; -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3